Skip to content

W
White Rabbit Trigger Distribution
Commit 69f83f7c authored by Dimitris Lampridis's avatar Dimitris Lampridis
Browse files
Options

hdl: rework of timing constraints

parent 42ee5732
Hide whitespace changes
Inline Side-by-side
Showing with 31 additions and 20 deletions
fmc-delay-1ns-8cha @ eca0894f
Subproject commit 84dca3f543664b508445efb56e915275bb02cd19
Subproject commit eca0894f19702d58d1d16bd4037cca5abc883812
fmc-tdc-1ns-5cha-gw @ 57cd1fbe
Subproject commit 4db629ed018e3796834044803a438bb0a52250f2
Subproject commit 57cd1fbe6f79d5dc8bf2c82ee4af55b203c3cb4e
mock-turtle @ 1478ea04
Subproject commit 5c0ef2d1f2bc57726b0151ef440780404edc88e6
Subproject commit 1478ea049d6d0368661a2e9b25746d8a15053367
wr-cores @ 9810ef9a
Subproject commit 9a218b5250ba26d9e04382f54c93a06885a0a655
Subproject commit 9810ef9a94dad4067edcce32e2ce1e6f1d5188b3
hdl/syn/svec/list_tdc_fd/svec_list_top.ucf
View file @ 69f83f7c
......@@ -682,6 +682,8 @@ NET "fmc1_fd_dmtd_fb_in_i" IOSTANDARD = "LVCMOS25";
# Timing constraints and exceptions
#===============================================================================
# All input clocks
NET "clk_125m_pllref_n_i" TNM_NET = clk_125m_pllref_n_i;
TIMESPEC TS_clk_125m_pllref_n_i = PERIOD "clk_125m_pllref_n_i" 8 ns HIGH 50%;
......@@ -691,7 +693,6 @@ TIMESPEC TS_clk_125m_gtp_n_i = PERIOD "clk_125m_gtp_n_i" 8 ns HIGH 50%;
NET "clk_20m_vcxo_i" TNM_NET = "clk_20m_vcxo_i";
TIMESPEC TS_clk_20m_vcxo_i = PERIOD "clk_20m_vcxo_i" 50 ns HIGH 50%;
# external 10MHz clock input
NET "fp_gpio3_i" TNM_NET = fp_gpio3_i;
TIMESPEC TS_fp_gpio3_i = PERIOD "fp_gpio3_i" 100 ns HIGH 50%;
......@@ -701,7 +702,12 @@ TIMESPEC TS_fmc0_tdc_125m_clk_n_i = PERIOD "fmc0_tdc_125m_clk_n_i" 8 ns HIGH 50%
NET "fmc1_fd_clk_ref_n_i" TNM_NET = fmc1_fd_clk_ref_n_i;
TIMESPEC TS_fmc1_fd_clk_ref_n_i = PERIOD "fmc1_fd_clk_ref_n_i" 8 ns HIGH 50%;
# relax all paths through syncrhonisers
# relax all paths through syncrhonisers:
# 1. define groups for each clock domain
# 2. define group for all sync chains
# 3. create sync chain groups that exclude one clock domain each
# 4. relax path from each clock domain to respective sync chain group
NET "clk_ref_125m" TNM_NET = clk_125m_pllref;
NET "clk_sys_62m5" TNM_NET = clk_sys;
NET "dcm1_clk_ref_0" TNM_NET = dcm1_clk_ref_0;
......@@ -710,21 +716,26 @@ NET "cmp_xwrc_board_svec/phy8_to_wrc_rx_clk" TNM_NET = phy_rx_rbclk;
NET "*/gc_sync_ffs_in" TNM_NET = "sync_ffs";
NET "*/gc_sync_register_in[*]" TNM_NET = "sync_reg";
TIMEGRP "synchronizers"="sync_ffs" "sync_reg";
TIMESPEC TS_ref_sync_ffs = FROM clk_125m_pllref TO "synchronizers" 8ns DATAPATHONLY;
TIMESPEC TS_sys_sync_ffs = FROM clk_sys TO "synchronizers" 16ns DATAPATHONLY;
TIMESPEC TS_fdl_sync_ffs = FROM dcm1_clk_ref_0 TO "synchronizers" 8ns DATAPATHONLY;
TIMESPEC TS_tdc_sync_ffs = FROM tdc_clk_125m TO "synchronizers" 8ns DATAPATHONLY;
TIMESPEC TS_phy_sync_ffs = FROM phy_rx_rbclk TO "synchronizers" 8ns DATAPATHONLY;
TIMEGRP "ref_sync"="synchronizers" EXCEPT "clk_125m_pllref";
TIMEGRP "sys_sync"="synchronizers" EXCEPT "clk_sys";
TIMEGRP "fdl_sync"="synchronizers" EXCEPT "dcm1_clk_ref_0";
TIMEGRP "tdc_sync"="synchronizers" EXCEPT "tdc_clk_125m";
TIMEGRP "phy_sync"="synchronizers" EXCEPT "phy_rx_rbclk";
TIMESPEC TS_ref_sync_ffs = FROM clk_125m_pllref TO "ref_sync" 20ns DATAPATHONLY;
TIMESPEC TS_sys_sync_ffs = FROM clk_sys TO "sys_sync" 20ns DATAPATHONLY;
TIMESPEC TS_fdl_sync_ffs = FROM dcm1_clk_ref_0 TO "fdl_sync" 20ns DATAPATHONLY;
TIMESPEC TS_tdc_sync_ffs = FROM tdc_clk_125m TO "tdc_sync" 20ns DATAPATHONLY;
TIMESPEC TS_phy_sync_ffs = FROM phy_rx_rbclk TO "phy_sync" 20ns DATAPATHONLY;
# Relax the path where TAI time crosses from WR ref to MT sys clock
# This is already synced via a gc_pulse_synchronizer, which makes sure that
# TAI WR ref value is stable when sampled by the MT sys clock
NET "cmp_mock_turtle/gen_cpus[*].U_CPU_Block/tm_p_sys" TNM_NET = "tm_mt_sync";
TIMESPEC TS_tm_mt_sync = FROM clk_125m_pllref TO "tm_mt_sync" 16ns DATAPATHONLY;
TIMESPEC TS_tm_mt_sync = FROM clk_125m_pllref TO "tm_mt_sync" 20ns DATAPATHONLY;
# Relax timing from spll_aligner outputs cref and cin (driven by ref clock)
# to the spll registers (driven by sys clock). The two sides are already sychronized
......@@ -733,11 +744,8 @@ TIMESPEC TS_tm_mt_sync = FROM clk_125m_pllref TO "tm_mt_sync" 16ns DATAPATHONLY;
NET "*/WRPC/U_SOFTPLL/U_Wrapped_Softpll/aligner_sample_cref(*)" TNM_NET = "wr_spll_sync";
NET "*/WRPC/U_SOFTPLL/U_Wrapped_Softpll/aligner_sample_cin(*)" TNM_NET = "wr_spll_sync";
TIMESPEC TS_wr_spll_sync = FROM clk_125m_pllref TO "wr_spll_sync" 16ns DATAPATHONLY;
TIMESPEC TS_wr_spll_sync = FROM clk_125m_pllref TO "wr_spll_sync" 20ns DATAPATHONLY;
# External async resets
NET "rst_n_i" TIG;
NET "vme_sysreset_n_i" TIG;
# Force PPS output to always be placed as IOB register
INST "cmp_xwrc_board_svec/cmp_board_common/cmp_xwr_core/wrpc/pps_gen/wrapped_ppsgen/pps_out_o" IOB = FORCE;
hdl/syn/svec/list_tdc_fd/syn_extra_steps.tcl
View file @ 69f83f7c
......@@ -16,9 +16,9 @@ xilinx::project open $project_file
# 2. Register Duplication Map
xilinx::project set "Enable Multi-Threading" "2" -process "Map"
xilinx::project set "Enable Multi-Threading" "4" -process "Place & Route"
xilinx::project set "Pack I/O Registers into IOBs" "Yes"
xilinx::project set "Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs"
#xilinx::project set "Register Balancing" "Yes"
#xilinx::project set "Pack I/O Registers into IOBs" "Yes"
#xilinx::project set "Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs"
xilinx::project set "Register Balancing" "Yes"
xilinx::project set "Register Duplication Map" "On"
xilinx::project save
......
hdl/top/svec/list_tdc_fd/svec_list_top.vhd
View file @ 69f83f7c
......@@ -539,6 +539,9 @@ architecture arch of svec_list_top is
signal fmc0_scl_out : std_logic;
signal fmc0_sda_out : std_logic;
attribute iob : string;
attribute iob of pps : signal is "FORCE";
begin -- architecture arch
-----------------------------------------------------------------------------
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment