[hdl] convert WRTD SVEC TDC-FD reference node to the Convention (synthesized,…

[hdl] convert WRTD SVEC TDC-FD reference node to the Convention (synthesized, not tested, fails timing)

[hdl] convert WRTD SVEC TDC-FD reference node to the Convention (synthesized,…
[hdl] convert WRTD SVEC TDC-FD reference node to the Convention (synthesized, not tested, fails timing)
6118f656 · Dimitris Lampridis · fb152b67 · 6118f656 · 1a129390 · 5dde6da5
Commit 6118f656 authored Jul 25, 2019 by Dimitris Lampridis
15 changed files
--- a/.gitmodules
+++ b/.gitmodules
@@ -31,3 +31,6 @@
 [submodule "dependencies/spec"]
 	path = dependencies/spec
 	url = https://ohwr.org/project/spec.git
+[submodule "dependencies/svec"]
+	path = dependencies/svec
+	url = https://ohwr.org/project/svec.git
--- a/ddr3-sp6-core @ 1a129390
+++ b/ddr3-sp6-core @ 1a129390
-Subproject commit bb5b8f75e6f85335b43fef320375404686a74008
+Subproject commit 1a1293900e6334bc41251ee84d0ae7d19980e584
--- a/general-cores @ 5dde6da5
+++ b/general-cores @ 5dde6da5
-Subproject commit ac43a1dbde29bcbd9126d877477e77b620176bac
+Subproject commit 5dde6da558083312cfd98d721e14b36a03e2a0bc
--- a/svec @ 41b383af
+++ b/svec @ 41b383af
+Subproject commit 41b383af43d4ea5f8cc7e90555d78f41227dd0b2
--- a/vme64x-core @ 366ca4db
+++ b/vme64x-core @ 366ca4db
-Subproject commit 1204aeca29ec3c72b6fa615976f000c664c7d152
+Subproject commit 366ca4dbe1777f5bc98341d2878070a6c6fa350f
--- a/hdl/syn/wrtd_ref_svec_tdc_fd/Manifest.py
+++ b/hdl/syn/wrtd_ref_svec_tdc_fd/Manifest.py
-# HDLMake 'develop' branch required.
-#
-# Due to bugs in release v3.0 of hdlmake it is necessary to use the "develop"
-# branch of hdlmake, commit db4e1ab.
-
 board  = "svec"
 target = "xilinx"
 action = "synthesis"
@@ -14,19 +9,14 @@ syn_top     = "wrtd_ref_svec_tdc_fd"
 syn_project = "wrtd_ref_svec_tdc_fd.xise"
 syn_tool    = "ise"

-fetchto = "../../../dependencies"
-
-syn_pre_project_cmd = "make -C ../../../software/firmware"
-
-syn_post_project_cmd = (
-    "$(TCL_INTERPRETER) " + \
-    fetchto + "/general-cores/tools/sdb_desc_gen.tcl " + \
-    syn_tool + " $(PROJECT_FILE);" \
-    "$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
-)
+# Allow the user to override fetchto using:
+#  hdlmake -p "fetchto='xxx'"
+if locals().get('fetchto', None) is None:
+    fetchto = "../../../dependencies"

 files = [
    "wrtd_ref_svec_tdc_fd.ucf",
+    "buildinfo_pkg.vhd",
 ]

 modules = {
@@ -34,3 +24,17 @@ modules = {
        "../../top/wrtd_ref_svec_tdc_fd",
    ],
 }
+
+syn_pre_project_cmd = "make -C ../../../software/firmware"
+
+# Do not fail during hdlmake fetch
+try:
+  exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
+except:
+  pass
+
+syn_post_project_cmd = "$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
+
+svec_template_ucf = ['wr', 'led', 'gpio']
+
+ctrls = ["bank4_64b_32b", "bank5_64b_32b"]
--- a/hdl/syn/wrtd_ref_svec_tdc_fd/wrtd_ref_svec_tdc_fd.ucf
+++ b/hdl/syn/wrtd_ref_svec_tdc_fd/wrtd_ref_svec_tdc_fd.ucf
@@ -2,365 +2,10 @@
 # IO Location Constraints
 #===============================================================================

-#----------------------------------------
-# VME interface
-#----------------------------------------
-NET "vme_write_n_i" LOC = R1;
-NET "vme_sysreset_n_i" LOC = P4;
-NET "vme_retry_oe_o" LOC = R4;
-NET "vme_retry_n_o" LOC = AB2;
-NET "vme_lword_n_b" LOC = M7;
-NET "vme_iackout_n_o" LOC = N3;
-NET "vme_iackin_n_i" LOC = P7;
-NET "vme_iack_n_i" LOC = N1;
-NET "vme_dtack_oe_o" LOC = T1;
-NET "vme_dtack_n_o" LOC = R5;
-NET "vme_ds_n_i[1]" LOC = Y6;
-NET "vme_ds_n_i[0]" LOC = Y7;
-NET "vme_data_oe_n_o" LOC = P1;
-NET "vme_data_dir_o" LOC = P2;
-NET "vme_berr_o" LOC = R3;
-NET "vme_as_n_i" LOC = P6;
-NET "vme_addr_oe_n_o" LOC = N4;
-NET "vme_addr_dir_o" LOC = N5;
-NET "vme_irq_o[7]" LOC = R7;
-NET "vme_irq_o[6]" LOC = AH2;
-NET "vme_irq_o[5]" LOC = AF2;
-NET "vme_irq_o[4]" LOC = N9;
-NET "vme_irq_o[3]" LOC = N10;
-NET "vme_irq_o[2]" LOC = AH4;
-NET "vme_irq_o[1]" LOC = AG4;
-NET "vme_gap_i" LOC = M6;
-NET "vme_ga_i[4]" LOC = V9;
-NET "vme_ga_i[3]" LOC = V10;
-NET "vme_ga_i[2]" LOC = AJ1;
-NET "vme_ga_i[1]" LOC = AH1;
-NET "vme_ga_i[0]" LOC = V7;
-NET "vme_data_b[31]" LOC = AK3;
-NET "vme_data_b[30]" LOC = AH3;
-NET "vme_data_b[29]" LOC = T8;
-NET "vme_data_b[28]" LOC = T9;
-NET "vme_data_b[27]" LOC = AK4;
-NET "vme_data_b[26]" LOC = AJ4;
-NET "vme_data_b[25]" LOC = W6;
-NET "vme_data_b[24]" LOC = W7;
-NET "vme_data_b[23]" LOC = AB6;
-NET "vme_data_b[22]" LOC = AB7;
-NET "vme_data_b[21]" LOC = W9;
-NET "vme_data_b[20]" LOC = W10;
-NET "vme_data_b[19]" LOC = AK5;
-NET "vme_data_b[18]" LOC = AH5;
-NET "vme_data_b[17]" LOC = AD6;
-NET "vme_data_b[16]" LOC = AC6;
-NET "vme_data_b[15]" LOC = AA6;
-NET "vme_data_b[14]" LOC = AA7;
-NET "vme_data_b[13]" LOC = T6;
-NET "vme_data_b[12]" LOC = T7;
-NET "vme_data_b[11]" LOC = AG5;
-NET "vme_data_b[10]" LOC = AE5;
-NET "vme_data_b[9]" LOC = Y11;
-NET "vme_data_b[8]" LOC = W11;
-NET "vme_data_b[7]" LOC = AF6;
-NET "vme_data_b[6]" LOC = AE6;
-NET "vme_data_b[5]" LOC = Y8;
-NET "vme_data_b[4]" LOC = Y9;
-NET "vme_data_b[3]" LOC = AE7;
-NET "vme_data_b[2]" LOC = AD7;
-NET "vme_data_b[1]" LOC = AA9;
-NET "vme_data_b[0]" LOC = AA10;
-NET "vme_am_i[5]" LOC = V8;
-NET "vme_am_i[4]" LOC = AG3;
-NET "vme_am_i[3]" LOC = AF3;
-NET "vme_am_i[2]" LOC = AF4;
-NET "vme_am_i[1]" LOC = AE4;
-NET "vme_am_i[0]" LOC = AK2;
-NET "vme_addr_b[31]" LOC = T2;
-NET "vme_addr_b[30]" LOC = T3;
-NET "vme_addr_b[29]" LOC = T4;
-NET "vme_addr_b[28]" LOC = U1;
-NET "vme_addr_b[27]" LOC = U3;
-NET "vme_addr_b[26]" LOC = U4;
-NET "vme_addr_b[25]" LOC = U5;
-NET "vme_addr_b[24]" LOC = V1;
-NET "vme_addr_b[23]" LOC = V2;
-NET "vme_addr_b[22]" LOC = W1;
-NET "vme_addr_b[21]" LOC = W3;
-NET "vme_addr_b[20]" LOC = AA4;
-NET "vme_addr_b[19]" LOC = AA5;
-NET "vme_addr_b[18]" LOC = Y1;
-NET "vme_addr_b[17]" LOC = Y2;
-NET "vme_addr_b[16]" LOC = Y3;
-NET "vme_addr_b[15]" LOC = Y4;
-NET "vme_addr_b[14]" LOC = AC1;
-NET "vme_addr_b[13]" LOC = AC3;
-NET "vme_addr_b[12]" LOC = AD1;
-NET "vme_addr_b[11]" LOC = AD2;
-NET "vme_addr_b[10]" LOC = AB3;
-NET "vme_addr_b[9]" LOC = AB4;
-NET "vme_addr_b[8]" LOC = AD3;
-NET "vme_addr_b[7]" LOC = AD4;
-NET "vme_addr_b[6]" LOC = AC4;
-NET "vme_addr_b[5]" LOC = AC5;
-NET "vme_addr_b[4]" LOC = N7;
-NET "vme_addr_b[3]" LOC = N8;
-NET "vme_addr_b[2]" LOC = AE1;
-NET "vme_addr_b[1]" LOC = AE3;
-NET "vme_write_n_i" IOSTANDARD = "LVCMOS33";
-NET "vme_sysreset_n_i" IOSTANDARD = "LVCMOS33";
-NET "vme_retry_oe_o" IOSTANDARD = "LVCMOS33";
-NET "vme_retry_n_o" IOSTANDARD = "LVCMOS33";
-NET "vme_lword_n_b" IOSTANDARD = "LVCMOS33";
-NET "vme_iackout_n_o" IOSTANDARD = "LVCMOS33";
-NET "vme_iackin_n_i" IOSTANDARD = "LVCMOS33";
-NET "vme_iack_n_i" IOSTANDARD = "LVCMOS33";
-NET "vme_dtack_oe_o" IOSTANDARD = "LVCMOS33";
-NET "vme_dtack_n_o" IOSTANDARD = "LVCMOS33";
-NET "vme_ds_n_i[1]" IOSTANDARD = "LVCMOS33";
-NET "vme_ds_n_i[0]" IOSTANDARD = "LVCMOS33";
-NET "vme_data_oe_n_o" IOSTANDARD = "LVCMOS33";
-NET "vme_data_dir_o" IOSTANDARD = "LVCMOS33";
-NET "vme_berr_o" IOSTANDARD = "LVCMOS33";
-NET "vme_as_n_i" IOSTANDARD = "LVCMOS33";
-NET "vme_addr_oe_n_o" IOSTANDARD = "LVCMOS33";
-NET "vme_addr_dir_o" IOSTANDARD = "LVCMOS33";
-NET "vme_irq_o[7]" IOSTANDARD = "LVCMOS33";
-NET "vme_irq_o[6]" IOSTANDARD = "LVCMOS33";
-NET "vme_irq_o[5]" IOSTANDARD = "LVCMOS33";
-NET "vme_irq_o[4]" IOSTANDARD = "LVCMOS33";
-NET "vme_irq_o[3]" IOSTANDARD = "LVCMOS33";
-NET "vme_irq_o[2]" IOSTANDARD = "LVCMOS33";
-NET "vme_irq_o[1]" IOSTANDARD = "LVCMOS33";
-NET "vme_gap_i" IOSTANDARD = "LVCMOS33";
-NET "vme_ga_i[4]" IOSTANDARD = "LVCMOS33";
-NET "vme_ga_i[3]" IOSTANDARD = "LVCMOS33";
-NET "vme_ga_i[2]" IOSTANDARD = "LVCMOS33";
-NET "vme_ga_i[1]" IOSTANDARD = "LVCMOS33";
-NET "vme_ga_i[0]" IOSTANDARD = "LVCMOS33";
-NET "vme_data_b[31]" IOSTANDARD = "LVCMOS33";
-NET "vme_data_b[30]" IOSTANDARD = "LVCMOS33";
-NET "vme_data_b[29]" IOSTANDARD = "LVCMOS33";
-NET "vme_data_b[28]" IOSTANDARD = "LVCMOS33";
-NET "vme_data_b[27]" IOSTANDARD = "LVCMOS33";
-NET "vme_data_b[26]" IOSTANDARD = "LVCMOS33";
-NET "vme_data_b[25]" IOSTANDARD = "LVCMOS33";
-NET "vme_data_b[24]" IOSTANDARD = "LVCMOS33";
-NET "vme_data_b[23]" IOSTANDARD = "LVCMOS33";
-NET "vme_data_b[22]" IOSTANDARD = "LVCMOS33";
-NET "vme_data_b[21]" IOSTANDARD = "LVCMOS33";
-NET "vme_data_b[20]" IOSTANDARD = "LVCMOS33";
-NET "vme_data_b[19]" IOSTANDARD = "LVCMOS33";
-NET "vme_data_b[18]" IOSTANDARD = "LVCMOS33";
-NET "vme_data_b[17]" IOSTANDARD = "LVCMOS33";
-NET "vme_data_b[16]" IOSTANDARD = "LVCMOS33";
-NET "vme_data_b[15]" IOSTANDARD = "LVCMOS33";
-NET "vme_data_b[14]" IOSTANDARD = "LVCMOS33";
-NET "vme_data_b[13]" IOSTANDARD = "LVCMOS33";
-NET "vme_data_b[12]" IOSTANDARD = "LVCMOS33";
-NET "vme_data_b[11]" IOSTANDARD = "LVCMOS33";
-NET "vme_data_b[10]" IOSTANDARD = "LVCMOS33";
-NET "vme_data_b[9]" IOSTANDARD = "LVCMOS33";
-NET "vme_data_b[8]" IOSTANDARD = "LVCMOS33";
-NET "vme_data_b[7]" IOSTANDARD = "LVCMOS33";
-NET "vme_data_b[6]" IOSTANDARD = "LVCMOS33";
-NET "vme_data_b[5]" IOSTANDARD = "LVCMOS33";
-NET "vme_data_b[4]" IOSTANDARD = "LVCMOS33";
-NET "vme_data_b[3]" IOSTANDARD = "LVCMOS33";
-NET "vme_data_b[2]" IOSTANDARD = "LVCMOS33";
-NET "vme_data_b[1]" IOSTANDARD = "LVCMOS33";
-NET "vme_data_b[0]" IOSTANDARD = "LVCMOS33";
-NET "vme_am_i[5]" IOSTANDARD = "LVCMOS33";
-NET "vme_am_i[4]" IOSTANDARD = "LVCMOS33";
-NET "vme_am_i[3]" IOSTANDARD = "LVCMOS33";
-NET "vme_am_i[2]" IOSTANDARD = "LVCMOS33";
-NET "vme_am_i[1]" IOSTANDARD = "LVCMOS33";
-NET "vme_am_i[0]" IOSTANDARD = "LVCMOS33";
-NET "vme_addr_b[31]" IOSTANDARD = "LVCMOS33";
-NET "vme_addr_b[30]" IOSTANDARD = "LVCMOS33";
-NET "vme_addr_b[29]" IOSTANDARD = "LVCMOS33";
-NET "vme_addr_b[28]" IOSTANDARD = "LVCMOS33";
-NET "vme_addr_b[27]" IOSTANDARD = "LVCMOS33";
-NET "vme_addr_b[26]" IOSTANDARD = "LVCMOS33";
-NET "vme_addr_b[25]" IOSTANDARD = "LVCMOS33";
-NET "vme_addr_b[24]" IOSTANDARD = "LVCMOS33";
-NET "vme_addr_b[23]" IOSTANDARD = "LVCMOS33";
-NET "vme_addr_b[22]" IOSTANDARD = "LVCMOS33";
-NET "vme_addr_b[21]" IOSTANDARD = "LVCMOS33";
-NET "vme_addr_b[20]" IOSTANDARD = "LVCMOS33";
-NET "vme_addr_b[19]" IOSTANDARD = "LVCMOS33";
-NET "vme_addr_b[18]" IOSTANDARD = "LVCMOS33";
-NET "vme_addr_b[17]" IOSTANDARD = "LVCMOS33";
-NET "vme_addr_b[16]" IOSTANDARD = "LVCMOS33";
-NET "vme_addr_b[15]" IOSTANDARD = "LVCMOS33";
-NET "vme_addr_b[14]" IOSTANDARD = "LVCMOS33";
-NET "vme_addr_b[13]" IOSTANDARD = "LVCMOS33";
-NET "vme_addr_b[12]" IOSTANDARD = "LVCMOS33";
-NET "vme_addr_b[11]" IOSTANDARD = "LVCMOS33";
-NET "vme_addr_b[10]" IOSTANDARD = "LVCMOS33";
-NET "vme_addr_b[9]" IOSTANDARD = "LVCMOS33";
-NET "vme_addr_b[8]" IOSTANDARD = "LVCMOS33";
-NET "vme_addr_b[7]" IOSTANDARD = "LVCMOS33";
-NET "vme_addr_b[6]" IOSTANDARD = "LVCMOS33";
-NET "vme_addr_b[5]" IOSTANDARD = "LVCMOS33";
-NET "vme_addr_b[4]" IOSTANDARD = "LVCMOS33";
-NET "vme_addr_b[3]" IOSTANDARD = "LVCMOS33";
-NET "vme_addr_b[2]" IOSTANDARD = "LVCMOS33";
-NET "vme_addr_b[1]" IOSTANDARD = "LVCMOS33";
-
-#----------------------------------------
-# Clock and reset inputs
-#----------------------------------------
-NET "rst_n_i" LOC = AD28;
-NET "rst_n_i" IOSTANDARD = "LVCMOS33";
-
-NET "clk_20m_vcxo_i" LOC = V26;
-NET "clk_20m_vcxo_i" IOSTANDARD = "LVCMOS33";
-
-NET "clk_125m_pllref_n_i" LOC = AB30;
-NET "clk_125m_pllref_p_i" LOC = AB28;
-NET "clk_125m_pllref_n_i" IOSTANDARD = "LVDS_25";
-NET "clk_125m_pllref_n_i" IOSTANDARD = "LVDS_25";
-
-NET "clk_125m_gtp_p_i" LOC = B19;
-NET "clk_125m_gtp_n_i" LOC = A19;
-
-#----------------------------------------
-# SFP slot
-#----------------------------------------
-NET "sfp_txp_o" LOC = B23;
-NET "sfp_txn_o" LOC = A23;
-NET "sfp_rxp_i" LOC = D22;
-NET "sfp_rxn_i" LOC = C22;
-NET "sfp_los_i" LOC = W25;
-NET "sfp_mod_def0_i" LOC = Y26;
-NET "sfp_mod_def1_b" LOC = Y27;
-NET "sfp_mod_def2_b" LOC = AA24;
-NET "sfp_rate_select_o" LOC = W24;
-NET "sfp_tx_disable_o" LOC = AA25;
-NET "sfp_tx_fault_i" LOC = AA27;
-NET "sfp_los_i" IOSTANDARD = "LVCMOS33";
-NET "sfp_mod_def0_i" IOSTANDARD = "LVCMOS33";
-NET "sfp_mod_def1_b" IOSTANDARD = "LVCMOS33";
-NET "sfp_mod_def2_b" IOSTANDARD = "LVCMOS33";
-NET "sfp_rate_select_o" IOSTANDARD = "LVCMOS33";
-NET "sfp_tx_disable_o" IOSTANDARD = "LVCMOS33";
-NET "sfp_tx_fault_i" IOSTANDARD = "LVCMOS33";
-
-#----------------------------------------
-# Clock controls
-#----------------------------------------
-NET "pll20dac_din_o" LOC = U28;
-NET "pll20dac_sclk_o" LOC = AA28;
-NET "pll20dac_sync_n_o" LOC = N28;
-NET "pll25dac_din_o" LOC = P25;
-NET "pll25dac_sclk_o" LOC = N27;
-NET "pll25dac_sync_n_o" LOC = P26;
-NET "pll20dac_din_o" IOSTANDARD = "LVCMOS33";
-NET "pll20dac_sclk_o" IOSTANDARD = "LVCMOS33";
-NET "pll20dac_sync_n_o" IOSTANDARD = "LVCMOS33";
-NET "pll25dac_din_o" IOSTANDARD = "LVCMOS33";
-NET "pll25dac_sclk_o" IOSTANDARD = "LVCMOS33";
-NET "pll25dac_sync_n_o" IOSTANDARD = "LVCMOS33";
-
-#----------------------------------------
-# SPI FLASH
-#----------------------------------------
-NET "spi_ncs_o"  LOC = AG27;
-NET "spi_ncs_o"  IOSTANDARD = "LVCMOS33";
-NET "spi_sclk_o" LOC = AG26;
-NET "spi_sclk_o"  IOSTANDARD = "LVCMOS33";
-NET "spi_mosi_o" LOC = AH26;
-NET "spi_mosi_o"  IOSTANDARD = "LVCMOS33";
-NET "spi_miso_i" LOC = AH27;
-NET "spi_miso_i"  IOSTANDARD = "LVCMOS33";
-
-#----------------------------------------
-# UART
-#----------------------------------------
-NET "uart_txd_o" LOC = U27;
-NET "uart_rxd_i" LOC = U25;
-NET "uart_txd_o" IOSTANDARD = "LVCMOS33";
-NET "uart_rxd_i" IOSTANDARD = "LVCMOS33";
-
-#----------------------------------------
-# 1-wire thermoeter + unique ID
-#----------------------------------------
-NET "carrier_onewire_b" LOC = AC30;
-NET "carrier_onewire_b" IOSTANDARD = "LVCMOS33";
-
-#----------------------------------------
-# Front panel LEDs
-#----------------------------------------
-NET "fp_led_line_oen_o[0]" LOC = AD26;
-NET "fp_led_line_oen_o[1]" LOC = AD27;
-NET "fp_led_line_o[0]" LOC = AC27;
-NET "fp_led_line_o[1]" LOC = AC28;
-NET "fp_led_column_o[0]" LOC = AE30;
-NET "fp_led_column_o[1]" LOC = AE27;
-NET "fp_led_column_o[2]" LOC = AE28;
-NET "fp_led_column_o[3]" LOC = AF28;
-NET "fp_led_line_oen_o[0]" IOSTANDARD="LVCMOS33";
-NET "fp_led_line_oen_o[1]" IOSTANDARD="LVCMOS33";
-NET "fp_led_line_o[0]" IOSTANDARD="LVCMOS33";
-NET "fp_led_line_o[1]" IOSTANDARD="LVCMOS33";
-NET "fp_led_column_o[0]" IOSTANDARD="LVCMOS33";
-NET "fp_led_column_o[1]" IOSTANDARD="LVCMOS33";
-NET "fp_led_column_o[2]" IOSTANDARD="LVCMOS33";
-NET "fp_led_column_o[3]" IOSTANDARD="LVCMOS33";
-
-#----------------------------------------
-# Front panel IOs
-#----------------------------------------
-NET "fp_gpio1_o"      LOC = T28;
-NET "fp_gpio2_o"      LOC = R30;
-NET "fp_gpio3_i"      LOC = V27;
-NET "fp_gpio4_i"      LOC = U29;
-NET "fp_gpio1_a2b_o"  LOC = T30;
-NET "fp_gpio2_a2b_o"  LOC = R29;
-NET "fp_gpio34_a2b_o" LOC = V28;
-NET "fp_term_en_o[1]" LOC = AB1;
-NET "fp_term_en_o[2]" LOC = W5;
-NET "fp_term_en_o[3]" LOC = W4;
-NET "fp_term_en_o[4]" LOC = V4;
-NET "fp_gpio1_o"      IOSTANDARD = "LVCMOS33";
-NET "fp_gpio2_o"      IOSTANDARD = "LVCMOS33";
-NET "fp_gpio3_i"      IOSTANDARD = "LVCMOS33";
-NET "fp_gpio4_i"      IOSTANDARD = "LVCMOS33";
-NET "fp_gpio1_a2b_o"  IOSTANDARD = "LVCMOS33";
-NET "fp_gpio2_a2b_o"  IOSTANDARD = "LVCMOS33";
-NET "fp_gpio34_a2b_o" IOSTANDARD = "LVCMOS33";
-NET "fp_term_en_o[1]" IOSTANDARD = "LVCMOS33";
-NET "fp_term_en_o[2]" IOSTANDARD = "LVCMOS33";
-NET "fp_term_en_o[3]" IOSTANDARD = "LVCMOS33";
-NET "fp_term_en_o[4]" IOSTANDARD = "LVCMOS33";
-
-#----------------------------------------
-# Carrier I2C EEPROM
-#----------------------------------------
-NET "carrier_scl_b" LOC = AC29;
-NET "carrier_sda_b" LOC = AA30;
-NET "carrier_scl_b" IOSTANDARD = "LVCMOS33";
-NET "carrier_sda_b" IOSTANDARD = "LVCMOS33";
-
 #----------------------------------------
 # FMCs
 #----------------------------------------
-NET "fmc0_prsntm2c_n_i" LOC = N30;
-NET "fmc0_scl_b" LOC = P28;
-NET "fmc0_sda_b" LOC = P30;

-NET "fmc1_prsntm2c_n_i" LOC = AE29;
-NET "fmc1_scl_b" LOC = W29;
-NET "fmc1_sda_b" LOC = V30;
-
-NET "fmc1_prsntm2c_n_i" IOSTANDARD = "LVCMOS33";
-NET "fmc1_scl_b" IOSTANDARD = "LVCMOS33";
-NET "fmc1_sda_b" IOSTANDARD = "LVCMOS33";
-
-NET "fmc0_prsntm2c_n_i" IOSTANDARD = "LVCMOS33";
-NET "fmc0_scl_b" IOSTANDARD = "LVCMOS33";
-NET "fmc0_sda_b" IOSTANDARD = "LVCMOS33";
-
-# ucfgen pin assignments for mezzanine fmc-tdc-v3 slot 0
 NET "fmc0_tdc_acam_refclk_p_i" LOC = "H15";
 NET "fmc0_tdc_acam_refclk_p_i" IOSTANDARD = "LVDS_25";
 NET "fmc0_tdc_acam_refclk_n_i" LOC = "G15";
@@ -502,7 +147,6 @@ NET "fmc0_tdc_enable_inputs_o" IOSTANDARD = "LVCMOS25";
 NET "fmc0_tdc_one_wire_b" LOC = "H12";
 NET "fmc0_tdc_one_wire_b" IOSTANDARD = "LVCMOS25";

-# ucfgen pin assignments for mezzanine fmc-delay-v4 slot 1
 NET "fmc1_fd_clk_ref_p_i" LOC = "AH16";
 NET "fmc1_fd_clk_ref_p_i" IOSTANDARD = "LVDS_25";
 NET "fmc1_fd_clk_ref_n_i" LOC = "AK16";
@@ -690,19 +334,8 @@ NET "fmc1_fd_dmtd_fb_in_i" IOSTANDARD = "LVCMOS25";
 # Timing constraints and exceptions
 #===============================================================================

-# All input clocks
-
-NET "clk_125m_pllref_n_i" TNM_NET = clk_125m_pllref_n_i;
-TIMESPEC TS_clk_125m_pllref_n_i = PERIOD "clk_125m_pllref_n_i" 8 ns HIGH 50%;
-
-NET "clk_125m_gtp_n_i" TNM_NET = clk_125m_gtp_n_i;
-TIMESPEC TS_clk_125m_gtp_n_i = PERIOD "clk_125m_gtp_n_i" 8 ns HIGH 50%;
-
-NET "clk_20m_vcxo_i" TNM_NET = "clk_20m_vcxo_i";
-TIMESPEC TS_clk_20m_vcxo_i = PERIOD "clk_20m_vcxo_i" 50 ns HIGH 50%;
-
-NET "fp_gpio3_i" TNM_NET = fp_gpio3_i;
-TIMESPEC TS_fp_gpio3_i = PERIOD "fp_gpio3_i" 100 ns HIGH 50%;
+NET "fp_gpio3_b" TNM_NET = fp_gpio3;
+TIMESPEC TS_fp_gpio3 = PERIOD "fp_gpio3" 100 ns HIGH 50%;

 NET "fmc0_tdc_125m_clk_n_i" TNM_NET = fmc0_tdc_125m_clk_n_i;
 TIMESPEC TS_fmc0_tdc_125m_clk_n_i = PERIOD "fmc0_tdc_125m_clk_n_i" 8 ns HIGH 50%;
@@ -710,59 +343,27 @@ TIMESPEC TS_fmc0_tdc_125m_clk_n_i = PERIOD "fmc0_tdc_125m_clk_n_i" 8 ns HIGH 50%
 NET "fmc1_fd_clk_ref_n_i" TNM_NET = fmc1_fd_clk_ref_n_i;
 TIMESPEC TS_fmc1_fd_clk_ref_n_i = PERIOD "fmc1_fd_clk_ref_n_i" 8 ns HIGH 50%;

-#----------------------------------------
-# WR DMTD tweaks
-#----------------------------------------
-
-INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds*/clk_in" TNM = skew_limit;
-INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds*/clk_in"      TNM = skew_limit;
-
-TIMESPEC TS_dmtd_skew = FROM "skew_limit" TO "FFS" 1 ns DATAPATHONLY;
-
-#----------------------------------------
-# Asynchronous resets
-#----------------------------------------
-
-NET "rst_n_i" TIG;
-NET "vme_sysreset_n_i" TIG;
-
 #----------------------------------------
 # Cross-clock domain sync
 #----------------------------------------

+# IMPORTANT: timing constraints are also coming from SVEC template UCF files
+
 # Declaration of domains
-NET "clk_ref_125m" TNM_NET = clk_125m_pllref;
-NET "clk_sys_62m5" TNM_NET = clk_sys;
-NET "dcm1_clk_ref_0" TNM_NET = dcm1_clk_ref_0;
-NET "tdc_clk_125m" TNM_NET = tdc_clk_125m;
-NET "cmp_xwrc_board_svec/phy8_to_wrc_rx_clk" TNM_NET = phy_rx_rbclk;
+NET "dcm1_clk_ref_0" TNM_NET = fdl_clk;
+NET "tdc_clk_125m"   TNM_NET = tdc_clk;

 # Exceptions for crossings via gc_sync_ffs
-NET "*/gc_sync_ffs_in" TNM = FFS "sync_ffs";
-
-TIMEGRP "ref_sync_ffs" = "sync_ffs" EXCEPT "clk_125m_pllref";
-TIMEGRP "sys_sync_ffs" = "sync_ffs" EXCEPT "clk_sys";
-TIMEGRP "fdl_sync_ffs" = "sync_ffs" EXCEPT "dcm1_clk_ref_0";
-TIMEGRP "tdc_sync_ffs" = "sync_ffs" EXCEPT "tdc_clk_125m";
-TIMEGRP "phy_sync_ffs" = "sync_ffs" EXCEPT "phy_rx_rbclk";
+TIMEGRP "fdl_sync_ffs" = "sync_ffs" EXCEPT "fdl_clk";
+TIMEGRP "tdc_sync_ffs" = "sync_ffs" EXCEPT "tdc_clk";

-TIMESPEC TS_ref_sync_ffs = FROM clk_125m_pllref TO "ref_sync_ffs" TIG;
-TIMESPEC TS_sys_sync_ffs = FROM clk_sys         TO "sys_sync_ffs" TIG;
-TIMESPEC TS_fdl_sync_ffs = FROM dcm1_clk_ref_0  TO "fdl_sync_ffs" TIG;
-TIMESPEC TS_tdc_sync_ffs = FROM tdc_clk_125m    TO "tdc_sync_ffs" TIG;
-TIMESPEC TS_phy_sync_ffs = FROM phy_rx_rbclk    TO "phy_sync_ffs" TIG;
+TIMESPEC TS_fdl_sync_ffs = FROM fdl_clk TO "fdl_sync_ffs" TIG;
+TIMESPEC TS_tdc_sync_ffs = FROM tdc_clk TO "tdc_sync_ffs" TIG;

 # Exceptions for crossings via gc_sync_register
-#NET "*/gc_sync_register_in[*]" TNM = FFS "sync_reg";

-#TIMEGRP "ref_sync_reg" = "sync_reg" EXCEPT "clk_125m_pllref";
-#TIMEGRP "sys_sync_reg" = "sync_reg" EXCEPT "clk_sys";
-#TIMEGRP "fdl_sync_reg" = "sync_reg" EXCEPT "dcm1_clk_ref_0";
-#TIMEGRP "tdc_sync_reg" = "sync_reg" EXCEPT "tdc_clk_125m";
-#TIMEGRP "phy_sync_reg" = "sync_reg" EXCEPT "phy_rx_rbclk";
+#TIMEGRP "fdl_sync_reg" = "sync_reg" EXCEPT "fdl_clk";
+#TIMEGRP "tdc_sync_reg" = "sync_reg" EXCEPT "tdc_clk";

-#TIMESPEC TS_ref_sync_reg = FROM clk_125m_pllref TO "ref_sync_reg" 8ns  DATAPATHONLY;
-#TIMESPEC TS_sys_sync_reg = FROM clk_sys         TO "sys_sync_reg" 16ns DATAPATHONLY;
-#TIMESPEC TS_fdl_sync_reg = FROM dcm1_clk_ref_0  TO "fdl_sync_reg" 8ns  DATAPATHONLY;
-#TIMESPEC TS_tdc_sync_reg = FROM tdc_clk_125m    TO "tdc_sync_reg" 8ns  DATAPATHONLY;
-#TIMESPEC TS_phy_sync_reg = FROM phy_rx_rbclk    TO "phy_sync_reg" 8ns  DATAPATHONLY;
+#TIMESPEC TS_fdl_sync_reg = FROM fdl_clk TO "fdl_sync_reg" 8ns DATAPATHONLY;
+#TIMESPEC TS_tdc_sync_reg = FROM tdc_clk TO "tdc_sync_reg" 8ns DATAPATHONLY;
--- a/hdl/testbench/wrtd_ref_spec150t_adc/buildinfo_pkg.vhd
+++ b/hdl/testbench/wrtd_ref_spec150t_adc/buildinfo_pkg.vhd
-- Buildinfo for project blah
--
-- This file was automatically generated; do not edit
-
-package buildinfo_pkg is
-  constant buildinfo : string :=
-       "buildinfo:1" & LF
-     & "module:wrtd_ref_spec150t_adc" & LF
-     & "commit:cb32df93f503c2ec56ef759ec063dd8557848e2b" & LF
-     & "syntool:modelsim" & LF
-     & "syndate:Wednesday, July 17 2019" & LF
-     & "synauth:Dimitris Lampridis" & LF;
-end buildinfo_pkg;
--- a/hdl/testbench/wrtd_ref_svec_tdc_fd/.gitignore
+++ b/hdl/testbench/wrtd_ref_svec_tdc_fd/.gitignore
@@ -3,3 +3,4 @@ Makefile
 modelsim.ini
 transcript*
 *.wlf
+buildinfo_pkg.vhd
--- a/hdl/testbench/wrtd_ref_svec_tdc_fd/Manifest.py
+++ b/hdl/testbench/wrtd_ref_svec_tdc_fd/Manifest.py
@@ -6,7 +6,10 @@ target     = "xilinx"
 syn_device = "xc6slx150t"
 vcom_opt   = "-93 -mixedsvvh"

-fetchto="../../../dependencies"
+# Allow the user to override fetchto using:
+#  hdlmake -p "fetchto='xxx'"
+if locals().get('fetchto', None) is None:
+    fetchto = "../../../dependencies"

 sim_pre_cmd = "EXTRA2_CFLAGS='-DSIMULATION' make -C ../../../software/firmware"

@@ -14,12 +17,13 @@ include_dirs = [
    "../include",
    fetchto + "/general-cores/sim/",
    fetchto + "/mock-turtle/hdl/testbench/include/",
+    fetchto + "/vme64x-core/hdl/sim/vme64x_bfm/",
 ]

 files = [
    "main.sv",
    "dut_env.sv",
-    "synthesis_descriptor.vhd",
+    "buildinfo_pkg.vhd",
 ]

 modules = {
@@ -27,3 +31,13 @@ modules = {
        "../../top/wrtd_ref_svec_tdc_fd",
    ],
 }
+
+ctrls = ["bank4_64b_32b", "bank5_64b_32b"]
+
+svec_template_ucf = []
+
+# Do not fail during hdlmake fetch
+try:
+  exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
+except:
+  pass
--- a/hdl/testbench/wrtd_ref_svec_tdc_fd/dut_env.sv
+++ b/hdl/testbench/wrtd_ref_svec_tdc_fd/dut_env.sv
@@ -25,7 +25,8 @@

 `timescale 1ns/1ps

-`include "vhd_wishbone_master.svh"
+`include "vme64x_bfm.svh"
+`include "svec_vme_buffers.svh"

 module simple_tdc_driver
  (
@@ -211,7 +212,7 @@ endmodule // simple_fdelay_mon

 module dut_env
  (
-   IVHDWishboneMaster host,
+   IVME64X VME,
   output clk_sys, rst_sys_n,
          sfp_txp_o, sfp_txn_o,
   input  sfp_rxp_i, sfp_rxn_i
@@ -247,24 +248,47 @@ module dut_env
   // The DUT
   //---------------------------------------------------------------------------

+   `DECLARE_VME_BUFFERS(VME.slave);
+
+   bit [4:0] slot_id = 8;
+
   wrtd_ref_svec_tdc_fd #
     (
      .g_SIMULATION     (1),
-      .g_SIM_BYPASS_VME (1),
      .g_WRPC_INITF     ("../../../dependencies/wr-cores/bin/wrpc/wrc_phy8_sim.bram")
      )
   DUT
     (
      .rst_n_i                    (1'b1),
-      .vme_sysreset_n_i           (1'b1),
+      .vme_sysreset_n_i           (VME_RST_n),
+      .vme_as_n_i                 (VME_AS_n),
+      .vme_write_n_i              (VME_WRITE_n),
+      .vme_am_i                   (VME_AM),
+      .vme_ds_n_i                 (VME_DS_n),
+      .vme_gap_i                  (^slot_id),
+      .vme_ga_i                   (~slot_id),
+      .vme_berr_o                 (VME_BERR),
+      .vme_dtack_n_o              (VME_DTACK_n),
+      .vme_retry_n_o              (VME_RETRY_n),
+      .vme_retry_oe_o             (VME_RETRY_OE),
+      .vme_lword_n_b              (VME_LWORD_n),
+      .vme_addr_b                 (VME_ADDR),
+      .vme_data_b                 (VME_DATA),
+      .vme_irq_o                  (VME_IRQ_n),
+      .vme_iack_n_i               (VME_IACK_n),
+      .vme_iackin_n_i             (VME_IACKIN_n),
+      .vme_iackout_n_o            (VME_IACKOUT_n),
+      .vme_dtack_oe_o             (VME_DTACK_OE),
+      .vme_data_dir_o             (VME_DATA_DIR),
+      .vme_data_oe_n_o            (VME_DATA_OE_N),
+      .vme_addr_dir_o             (VME_ADDR_DIR),
+      .vme_addr_oe_n_o            (VME_ADDR_OE_N),
      .clk_125m_pllref_p_i        (clk_125m_pll),
      .clk_125m_pllref_n_i        (~clk_125m_pll),
      .clk_125m_gtp_p_i           (clk_125m_gtp),
      .clk_125m_gtp_n_i           (~clk_125m_gtp),
      .clk_20m_vcxo_i             (clk_20m_vcxo),
-      .sim_wb_i                   (host.out),
-      .sim_wb_o                   (host.in),
-      .carrier_onewire_b          (),
+      .onewire_b                  (),
      .sfp_txp_o                  (sfp_txp_o),
      .sfp_txn_o                  (sfp_txn_o),
      .sfp_rxp_i                  (sfp_rxp_i),
@@ -363,7 +387,7 @@ module dut_env

   initial begin
      //  No pulse before: WR (300us) + TDC setup.
-      automatic time start = 480us;
+      automatic time start = 850us;

      push_pulse(0, start + 10us);
      push_pulse(1, start + 30us);
@@ -376,16 +400,16 @@ module dut_env

   initial begin
      // Skip WR SoftPLL lock
-      force DUT.cmp_xwrc_board_svec.cmp_board_common.cmp_xwr_core.
+      force DUT.inst_svec_template.gen_wr.cmp_xwrc_board_svec.cmp_board_common.cmp_xwr_core.
        WRPC.U_SOFTPLL.U_Wrapped_Softpll.out_locked_o = 3'b111;
      // Silence Xilinx unisim DSP48A1 warnings about invalid OPMODE
-      force DUT.cmp_xwrc_board_svec.cmp_board_common.cmp_xwr_core.
+      force DUT.inst_svec_template.gen_wr.cmp_xwrc_board_svec.cmp_board_common.cmp_xwr_core.
        WRPC.LM32_CORE.gen_profile_medium_icache.U_Wrapped_LM32.cpu.
          multiplier.D1.OPMODE_dly = 0;
-      force DUT.cmp_xwrc_board_svec.cmp_board_common.cmp_xwr_core.
+      force DUT.inst_svec_template.gen_wr.cmp_xwrc_board_svec.cmp_board_common.cmp_xwr_core.
        WRPC.LM32_CORE.gen_profile_medium_icache.U_Wrapped_LM32.cpu.
          multiplier.D2.OPMODE_dly = 0;
-      force DUT.cmp_xwrc_board_svec.cmp_board_common.cmp_xwr_core.
+      force DUT.inst_svec_template.gen_wr.cmp_xwrc_board_svec.cmp_board_common.cmp_xwr_core.
        WRPC.LM32_CORE.gen_profile_medium_icache.U_Wrapped_LM32.cpu.
          multiplier.D3.OPMODE_dly = 0;
   end // initial begin

--- a/hdl/testbench/wrtd_ref_svec_tdc_fd/main.sv
+++ b/hdl/testbench/wrtd_ref_svec_tdc_fd/main.sv
@@ -24,10 +24,13 @@

 `timescale 1ns/1ps

+`include "vme64x_bfm.svh"
 `include "wrtd_driver.svh"
-`include "vhd_wishbone_master.svh"

-`define TDC_DIRECT_BASE 'h18000
+`define VME_OFFSET      'h8000_0000
+`define TDC_DIRECT_BASE `VME_OFFSET + 'h0001_8000
+`define MT_BASE         `VME_OFFSET + 'h0002_0000
+

 module main;

@@ -35,9 +38,9 @@ module main;

   wire sfp_txp, sfp_txn, sfp_rxp, sfp_rxn;

-   IVHDWishboneMaster host (clk_sys, rst_sys_n);
+   IVME64X VME(rst_sys_n);

-   dut_env DUT (host, clk_sys, rst_sys_n, sfp_txp, sfp_txn, sfp_rxp, sfp_rxn);
+   dut_env DUT (VME, clk_sys, rst_sys_n, sfp_txp, sfp_txn, sfp_rxp, sfp_rxn);

   IMockTurtleIRQ MtIrqMonitor (`MT_ATTACH_IRQ(DUT.DUT.cmp_mock_turtle));

@@ -46,18 +49,35 @@ module main;

   WrtdDrv dev;

-   const uint64_t MT_BASE = 'h0002_0000;
+   initial begin

-   CBusAccessor acc;
+      CBusAccessor_VME64x acc;

-   initial begin
+      acc = new(VME.tb);

      $timeformat (-6, 3, "us", 10);

-      #10us;
-      acc = host.get_accessor();
-      acc.set_default_xfer_size(4);
-      dev = new (acc, MT_BASE, MtIrqMonitor, "DUT");
+      #5us;
+
+      /* map func0 to 0x80000000, A32 */
+      acc.write('h7ff63, 'h80, A32|CR_CSR|D08Byte3);
+      acc.write('h7ff67, 0, CR_CSR|A32|D08Byte3);
+      acc.write('h7ff6b, 0, CR_CSR|A32|D08Byte3);
+      acc.write('h7ff6f, 36, CR_CSR|A32|D08Byte3);
+      acc.write('h7ff33, 1, CR_CSR|A32|D08Byte3);
+      acc.write('h7fffb, 'h10, CR_CSR|A32|D08Byte3); /* enable module (BIT_SET = 0x10) */
+
+      acc.set_default_modifiers(A32 | D32 | SINGLE);
+      /* Hack around CBusAccessor to make it work like CBusAccessor_VME64x. This is needed
+       because WrtdDev expects a CBusAccesor and will not respect the m_default_modifiers value
+       of CBusAccessor_VME64x when performing reads/writes. */
+      acc.set_default_xfer_size(A32 | D32 | SINGLE);
+
+      acc.write(`TDC_DIRECT_BASE + 'h4, 'h40);
+      #5us;
+
+      dev = new (acc, `MT_BASE, MtIrqMonitor, "DUT");
+
      dev.init();

      dev.add_rule ( "rule0" );
@@ -86,8 +106,19 @@ module main;

      // Set dead-time
      acc.write(`TDC_DIRECT_BASE + 'h4, 'h40);
+
+      #5us;
+
      // Enable channels
      acc.write(`TDC_DIRECT_BASE + 'h0, 'h1f);
+
+      // Force start_fpga from TDC to make sure that the FSM has been started
+      force DUT.DUT.U_TDC_Core.cmp_tdc_mezz.cmp_tdc_core.start_from_fpga = 'b1;
+      #100ns;
+      release DUT.DUT.U_TDC_Core.cmp_tdc_mezz.cmp_tdc_core.start_from_fpga;
+
+      dev.mdisplay("Configuration complete, ready to accept pulses...");
+
   end

   initial begin

--- a/hdl/testbench/wrtd_ref_svec_tdc_fd/synthesis_descriptor.vhd
+++ b/hdl/testbench/wrtd_ref_svec_tdc_fd/synthesis_descriptor.vhd
--------------------------------------------------------------------------------
-- SDB meta information for svec_list_tdc_fd.xise.
--
-- This file was automatically generated by ../../../ip_cores/general-cores/tools/sdb_desc_gen.tcl on:
-- Friday, July 20 2018
--
-- ../../../ip_cores/general-cores/tools/sdb_desc_gen.tcl is part of OHWR general-cores:
-- https://www.ohwr.org/projects/general-cores/wiki
--
-- For more information on SDB meta information, see also:
-- https://www.ohwr.org/projects/sdb/wiki
--------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-use work.wishbone_pkg.all;
-
-package synthesis_descriptor is
-
-  constant c_sdb_synthesis_info : t_sdb_synthesis := (
-    syn_module_name  => "svec_list_tdc_fd",
-    syn_commit_id    => "4a68a12eede44d878435d25c3c7eaaf4",
-    syn_tool_name    => "ISE     ",
-    syn_tool_version => x"00000147",
-    syn_date         => x"20180720",
-    syn_username     => "Dimitris Lampri");
-
-  constant c_sdb_repo_url : t_sdb_repo_url := (
-    repo_url => "ssh://git@gitlab.cern.ch:7999/coht/wr-trigger-distribution.git ");
-
-end package synthesis_descriptor;
--- a/hdl/top/wrtd_ref_svec_tdc_fd/Manifest.py
+++ b/hdl/top/wrtd_ref_svec_tdc_fd/Manifest.py
@@ -6,6 +6,7 @@ fetchto = "../../../dependencies"

 modules = {
    "git" : [
+        "https://ohwr.org/project/svec.git",
        "https://ohwr.org/project/general-cores.git",
        "https://ohwr.org/project/wr-cores.git",
        "https://ohwr.org/project/vme64x-core.git",
@@ -13,5 +14,6 @@ modules = {
        "https://ohwr.org/project/mock-turtle.git",
        "https://ohwr.org/project/fmc-tdc-1ns-5cha-gw.git",
        "https://ohwr.org/project/fmc-delay-1ns-8cha.git",
+        "https://ohwr.org/project/ddr3-sp6-core.git",
    ],
 }
--- a/hdl/top/wrtd_ref_svec_tdc_fd/wrtd_ref_svec_tdc_fd.vhd
+++ b/hdl/top/wrtd_ref_svec_tdc_fd/wrtd_ref_svec_tdc_fd.vhd
@@ -37,15 +37,10 @@ use ieee.numeric_std.all;
 library work;
 use work.gencores_pkg.all;
 use work.wishbone_pkg.all;
-use work.vme64x_pkg.all;
-use work.wr_board_pkg.all;
-use work.wr_svec_pkg.all;
-use work.wr_fabric_pkg.all;
 use work.mt_mqueue_pkg.all;
 use work.mock_turtle_pkg.all;
-use work.tdc_core_pkg.all;
-use work.fine_delay_pkg.all;
-use work.synthesis_descriptor.all;
+use work.wr_board_pkg.all;
+use work.wr_fabric_pkg.all;

 library unisim;
 use unisim.vcomponents.all;
@@ -59,9 +54,7 @@ entity wrtd_ref_svec_tdc_fd is
    -- changed to non-zero in the instantiation of the top level DUT in the
    -- testbench. Its purpose is to reduce some internal counters/timeouts
    -- to speed up simulations.
-    g_SIMULATION     : integer := 0;
-    -- Bypass VME core, useful only in simulation
-    g_SIM_BYPASS_VME : boolean := FALSE);
+    g_SIMULATION     : integer := 0);
  port (
    ---------------------------------------------------------------------------
    -- Clocks/resets
@@ -83,12 +76,6 @@ entity wrtd_ref_svec_tdc_fd is
    -- VME interface
    ---------------------------------------------------------------------------

-    -- Bypass VME core, useful only in simulation
-    -- synthesis translate_off
-    sim_wb_i : in  t_wishbone_slave_in := cc_dummy_slave_in;
-    sim_wb_o : out t_wishbone_slave_out;
-    -- synthesis translate_on
-
    vme_write_n_i    : in    std_logic;
    vme_sysreset_n_i : in    std_logic;
    vme_retry_oe_o   : out   std_logic;
@@ -147,11 +134,16 @@ entity wrtd_ref_svec_tdc_fd is
    carrier_scl_b : inout std_logic;
    carrier_sda_b : inout std_logic;

+    ---------------------------------------------------------------------------
+    -- PCB version
+    ---------------------------------------------------------------------------
+    pcbrev_i : in std_logic_vector(4 downto 0);
+
    ---------------------------------------------------------------------------
    -- Onewire interface
    ---------------------------------------------------------------------------

-    carrier_onewire_b : inout std_logic;
+    onewire_b : inout std_logic;

    ---------------------------------------------------------------------------
    -- UART
@@ -178,10 +170,10 @@ entity wrtd_ref_svec_tdc_fd is
    fp_led_line_o     : out std_logic_vector(1 downto 0);
    fp_led_column_o   : out std_logic_vector(3 downto 0);

-    fp_gpio1_o      : out std_logic;  -- PPS output
-    fp_gpio2_o      : out std_logic;  -- Ref clock div2 output
-    fp_gpio3_i      : in  std_logic;  -- ext 10MHz clock input
-    fp_gpio4_i      : in  std_logic;  -- ext PPS input
+    fp_gpio1_b      : out std_logic;  -- PPS output
+    fp_gpio2_b      : out std_logic;  -- Ref clock div2 output
+    fp_gpio3_b      : in  std_logic;  -- ext 10MHz clock input
+    fp_gpio4_b      : in  std_logic;  -- ext PPS input
    fp_term_en_o    : out std_logic_vector(4 downto 1);
    fp_gpio1_a2b_o  : out std_logic;
    fp_gpio2_a2b_o  : out std_logic;
@@ -243,7 +235,7 @@ entity wrtd_ref_svec_tdc_fd is
    fmc0_tdc_led_trig4_o  : out std_logic;
    fmc0_tdc_led_trig5_o  : out std_logic;

-    fmc0_prsntm2c_n_i : in std_logic;
+    fmc0_prsnt_m2c_n_i : in std_logic;

    fmc0_scl_b : inout std_logic;
    fmc0_sda_b : inout std_logic;
@@ -288,7 +280,7 @@ entity wrtd_ref_svec_tdc_fd is

    fmc1_fd_onewire_b : inout std_logic;

-    fmc1_prsntm2c_n_i : in std_logic;
+    fmc1_prsnt_m2c_n_i : in std_logic;

    fmc1_scl_b : inout std_logic;
    fmc1_sda_b : inout std_logic);
@@ -297,20 +289,6 @@ end entity wrtd_ref_svec_tdc_fd;

 architecture arch of wrtd_ref_svec_tdc_fd is

-  -----------------------------------------------------------------------------
-  -- Components
-  -----------------------------------------------------------------------------
-
-  component fd_ddr_pll
-    port (
-      RST       : in  std_logic;
-      LOCKED    : out std_logic;
-      CLK_IN1_P : in  std_logic;
-      CLK_IN1_N : in  std_logic;
-      CLK_OUT1  : out std_logic;
-      CLK_OUT2  : out std_logic);
-  end component;
-
  -----------------------------------------------------------------------------
  -- Constants
  -----------------------------------------------------------------------------
@@ -319,49 +297,34 @@ architecture arch of wrtd_ref_svec_tdc_fd is
  constant c_NUM_WB_MASTERS : integer := 1;

  -- Number of slaves attached to the primary wishbone crossbar
-  constant c_NUM_WB_SLAVES : integer := 5;
+  constant c_NUM_WB_SLAVES : integer := 4;

  -- Primary Wishbone master(s) offsets
  constant c_WB_MASTER_VME : integer := 0;

  -- Primary Wishbone slave(s) offsets
-  constant c_WB_SLAVE_VIC : integer := 0;
-  constant c_WB_SLAVE_FDL : integer := 1;
-  constant c_WB_SLAVE_TDC : integer := 2;
-  constant c_WB_SLAVE_MT  : integer := 3;
-  constant c_WB_SLAVE_WRC : integer := 4;
-  constant c_WB_DESC_SYN  : integer := c_NUM_WB_SLAVES;
-  constant c_WB_DESC_URL  : integer := c_NUM_WB_SLAVES + 1;
-
-  -- sdb header address on primary crossbar
-  constant c_SDB_ADDRESS : t_wishbone_address := x"00000000";
-
-  -- f_xwb_bridge_manual_sdb(size, sdb_addr)
-  -- Note: sdb_addr is the sdb records address relative to the bridge base address
-  constant c_WRC_BRIDGE_SDB : t_sdb_bridge :=
-    f_xwb_bridge_manual_sdb(x"0003ffff", x"00030000");
+  constant c_WB_SLAVE_METADATA : integer := 0;
+  constant c_WB_SLAVE_FDL      : integer := 1;
+  constant c_WB_SLAVE_TDC      : integer := 2;
+  constant c_WB_SLAVE_MT       : integer := 3;

-  constant c_TDC_BRIDGE_SDB : t_sdb_bridge :=
-    f_xwb_bridge_manual_sdb(x"0000ffff", x"00000000");
+  -- Convention metadata base address
+  constant c_METADATA_ADDR : t_wishbone_address := x"0000_2000";

  -- Primary wishbone crossbar layout
-  constant c_WB_LAYOUT : t_sdb_record_array(c_NUM_WB_SLAVES + 1 downto 0) := (
-    c_WB_SLAVE_VIC => f_sdb_embed_device(c_XWB_VIC_SDB,     x"00002000"),
-    c_WB_SLAVE_FDL => f_sdb_embed_device(c_FD_SDB_DEVICE,   x"00008000"),
-    c_WB_SLAVE_TDC => f_sdb_embed_bridge(c_TDC_BRIDGE_SDB,  x"00010000"),
-    c_WB_SLAVE_MT  => f_sdb_embed_device(c_MOCK_TURTLE_SDB, x"00020000"),
-    c_WB_SLAVE_WRC => f_sdb_embed_bridge(c_WRC_BRIDGE_SDB,  x"00040000"),
-    c_WB_DESC_SYN  => f_sdb_embed_synthesis(c_SDB_SYNTHESIS_INFO),
-    c_WB_DESC_URL  => f_sdb_embed_repo_url(c_SDB_REPO_URL));
-
-  -- not really used, will be reprogrammed by software
-  constant c_VIC_VECTOR_TABLE : t_wishbone_address_array(0 to 5) := (
-    0 => x"00013000",   -- FMC TDC
-    1 => x"00018000",   -- FMC Fine Delay
-    2 => x"00020000",   -- MT Mqueue in interrupt
-    3 => x"00020001",   -- MT Mqueue out interrupt
-    4 => x"00020002",   -- MT Console interrupt
-    5 => x"00020003");  -- MT Notify interrupt
+  constant c_WB_LAYOUT_ADDR :
+    t_wishbone_address_array(c_NUM_WB_SLAVES - 1 downto 0) := (
+      c_WB_SLAVE_METADATA => c_METADATA_ADDR,
+      c_WB_SLAVE_FDL      => x"0000_8000",
+      c_WB_SLAVE_TDC      => x"0001_0000",
+      c_WB_SLAVE_MT       => x"0002_0000");
+
+  constant c_WB_LAYOUT_MASK :
+    t_wishbone_address_array(c_NUM_WB_SLAVES - 1 downto 0) := (
+      c_WB_SLAVE_METADATA => x"0003_ffc0",  --    0x40 bytes
+      c_WB_SLAVE_FDL      => x"0003_fe00",  --   0x200 bytes
+      c_WB_SLAVE_TDC      => x"0003_0000",  -- 0x10000 bytes
+      c_WB_SLAVE_MT       => x"0002_0000"); -- 0x20000 bytes

  constant c_FMC_MUX_ADDR : t_wishbone_address_array(0 downto 0) :=
    (0 => x"00000000");
@@ -424,8 +387,6 @@ architecture arch of wrtd_ref_svec_tdc_fd is
  signal dcm1_clk_ref_180 : std_logic;

  attribute keep                   : string;
-  attribute keep of clk_sys_62m5   : signal is "TRUE";
-  attribute keep of clk_ref_125m   : signal is "TRUE";
  attribute keep of tdc_clk_125m   : signal is "TRUE";
  attribute keep of dcm1_clk_ref_0 : signal is "TRUE";

@@ -452,10 +413,6 @@ architecture arch of wrtd_ref_svec_tdc_fd is
  signal sfp_scl_in  : std_logic;
  signal sfp_scl_out : std_logic;

-  -- OneWire
-  signal onewire_data : std_logic;
-  signal onewire_oe   : std_logic;
-
  -- LEDs and GPIO
  signal pps         : std_logic;
  signal pps_led     : std_logic;
@@ -464,13 +421,8 @@ architecture arch of wrtd_ref_svec_tdc_fd is
  signal wr_led_link : std_logic;
  signal wr_led_act  : std_logic;

-  -- VIC
-  signal fmc_host_irq   : std_logic_vector(1 downto 0);
-  signal mt_hmq_in_irq  : std_logic;
-  signal mt_hmq_out_irq : std_logic;
-  signal mt_console_irq : std_logic;
-  signal mt_notify_irq  : std_logic;
-  signal vic_master_irq : std_logic;
+  -- Interrupts
+  signal irq_vector : std_logic_vector(5 downto 0);

  --  MT endpoints
  signal rmq_endpoint_out : t_mt_rmq_endpoint_iface_out;
@@ -522,35 +474,148 @@ architecture arch of wrtd_ref_svec_tdc_fd is
  signal fmc1_fd_tdc_data_oe  : std_logic;

  signal fmc1_fd_owr_en, fmc1_fd_owr_in  : std_logic;
-  signal fmc1_fd_scl_out, fmc1_fd_scl_in : std_logic;
-  signal fmc1_fd_sda_out, fmc1_fd_sda_in : std_logic;
-
-  signal fmc0_scl_out : std_logic;
-  signal fmc0_sda_out : std_logic;

  attribute iob        : string;
  attribute iob of pps : signal is "FORCE";

 begin  -- architecture arch

-  -----------------------------------------------------------------------------
-  -- System reset
-  -----------------------------------------------------------------------------
  areset_n <= vme_sysreset_n_i and rst_n_i;

+  cmp_xwb_metadata : entity work.xwb_metadata
+    generic map (
+      g_VENDOR_ID    => x"0000_10DC",
+      g_DEVICE_ID    => x"574E_0002", -- WRTD Node (WN) 2
+      g_VERSION      => x"0100_0000",
+      g_CAPABILITIES => x"0000_0000",
+      g_COMMIT_ID    => (others => '0'))
+    port map (
+      clk_i   => clk_sys_62m5,
+      rst_n_i => rst_sys_62m5_n,
+      wb_i    => cnx_slave_in(c_WB_SLAVE_METADATA),
+      wb_o    => cnx_slave_out(c_WB_SLAVE_METADATA));
+
+  inst_svec_template : entity work.svec_template_wr
+    generic map (
+      g_WITH_VIC           => TRUE,
+      g_WITH_ONEWIRE       => FALSE,
+      g_WITH_SPI           => FALSE,
+      g_WITH_WR            => TRUE,
+      g_WITH_DDR4          => FALSE,
+      g_WITH_DDR5          => FALSE,
+      g_APP_OFFSET         => c_METADATA_ADDR,
+      g_NUM_USER_IRQ       => 6,
+      g_DPRAM_INITF        => g_WRPC_INITF,
+      g_AUX_CLKS           => 2,
+      g_FABRIC_IFACE       => plain,
+      g_SIMULATION         => g_SIMULATION,
+      g_VERBOSE            => FALSE)
+    port map (
+      rst_n_i              => areset_n,
+      clk_125m_pllref_p_i  => clk_125m_pllref_p_i,
+      clk_125m_pllref_n_i  => clk_125m_pllref_n_i,
+      clk_20m_vcxo_i       => clk_20m_vcxo_i,
+      clk_125m_gtp_n_i     => clk_125m_gtp_n_i,
+      clk_125m_gtp_p_i     => clk_125m_gtp_p_i,
+      clk_aux_i(0)         => tdc_clk_125m,
+      clk_aux_i(1)         => dcm1_clk_ref_0,
+      clk_10m_ext_i        => clk_ext_ref,
+      pps_ext_i            => pps_ext_in,
+      vme_write_n_i        => vme_write_n_i,
+      vme_sysreset_n_i     => vme_sysreset_n_i,
+      vme_retry_oe_o       => vme_retry_oe_o,
+      vme_retry_n_o        => vme_retry_n_o,
+      vme_lword_n_b        => vme_lword_n_b,
+      vme_iackout_n_o      => vme_iackout_n_o,
+      vme_iackin_n_i       => vme_iackin_n_i,
+      vme_iack_n_i         => vme_iack_n_i,
+      vme_gap_i            => vme_gap_i,
+      vme_dtack_oe_o       => vme_dtack_oe_o,
+      vme_dtack_n_o        => vme_dtack_n_o,
+      vme_ds_n_i           => vme_ds_n_i,
+      vme_data_oe_n_o      => vme_data_oe_n_o,
+      vme_data_dir_o       => vme_data_dir_o,
+      vme_berr_o           => vme_berr_o,
+      vme_as_n_i           => vme_as_n_i,
+      vme_addr_oe_n_o      => vme_addr_oe_n_o,
+      vme_addr_dir_o       => vme_addr_dir_o,
+      vme_irq_o            => vme_irq_o,
+      vme_ga_i             => vme_ga_i,
+      vme_data_b           => vme_data_b,
+      vme_am_i             => vme_am_i,
+      vme_addr_b           => vme_addr_b,
+      fmc0_scl_b           => fmc0_scl_b,
+      fmc0_sda_b           => fmc0_sda_b,
+      fmc1_scl_b           => fmc1_scl_b,
+      fmc1_sda_b           => fmc1_sda_b,
+      fmc0_prsnt_m2c_n_i   => fmc0_prsnt_m2c_n_i,
+      fmc1_prsnt_m2c_n_i   => fmc1_prsnt_m2c_n_i,
+      onewire_b            => onewire_b,
+      carrier_scl_b        => carrier_scl_b,
+      carrier_sda_b        => carrier_sda_b,
+      spi_sclk_o           => spi_sclk_o,
+      spi_ncs_o            => spi_ncs_o,
+      spi_mosi_o           => spi_mosi_o,
+      spi_miso_i           => spi_miso_i,
+      uart_rxd_i           => uart_rxd_i,
+      uart_txd_o           => uart_txd_o,
+      plldac_sclk_o        => pll20dac_sclk_o,
+      plldac_din_o         => pll20dac_din_o,
+      pll20dac_din_o       => pll20dac_din_o,
+      pll20dac_sclk_o      => pll20dac_sclk_o,
+      pll20dac_sync_n_o    => pll20dac_sync_n_o,
+      pll25dac_din_o       => pll25dac_din_o,
+      pll25dac_sclk_o      => pll25dac_sclk_o,
+      pll25dac_sync_n_o    => pll25dac_sync_n_o,
+      sfp_txp_o            => sfp_txp_o,
+      sfp_txn_o            => sfp_txn_o,
+      sfp_rxp_i            => sfp_rxp_i,
+      sfp_rxn_i            => sfp_rxn_i,
+      sfp_mod_def0_i       => sfp_mod_def0_i,
+      sfp_mod_def1_b       => sfp_mod_def1_b,
+      sfp_mod_def2_b       => sfp_mod_def2_b,
+      sfp_rate_select_o    => sfp_rate_select_o,
+      sfp_tx_fault_i       => sfp_tx_fault_i,
+      sfp_tx_disable_o     => sfp_tx_disable_o,
+      sfp_los_i            => sfp_los_i,
+      pcbrev_i             => pcbrev_i,
+      clk_sys_62m5_o       => clk_sys_62m5,
+      rst_sys_62m5_n_o     => rst_sys_62m5_n,
+      clk_ref_125m_o       => clk_ref_125m,
+      rst_ref_125m_n_o     => open,
+      irq_user_i           => irq_vector,
+      wrf_src_o            => eth_rx_in,
+      wrf_src_i            => eth_rx_out,
+      wrf_snk_o            => eth_tx_in,
+      wrf_snk_i            => eth_tx_out,
+      tm_link_up_o         => tm_link_up,
+      tm_time_valid_o      => tm_time_valid,
+      tm_tai_o             => tm_tai,
+      tm_cycles_o          => tm_cycles,
+      tm_dac_value_o       => tm_dac_value,
+      tm_dac_wr_o          => tm_dac_wr,
+      tm_clk_aux_lock_en_i => tm_clk_aux_lock_en,
+      tm_clk_aux_locked_o  => tm_clk_aux_locked,
+      pps_p_o              => pps,
+      pps_led_o            => pps_led,
+      link_ok_o            => open,
+      led_link_o           => wr_led_link,
+      led_act_o            => wr_led_act,
+      app_wb_o             => cnx_master_out(c_WB_MASTER_VME),
+      app_wb_i             => cnx_master_in(c_WB_MASTER_VME));
+
  -----------------------------------------------------------------------------
  -- Primary wishbone Crossbar
  -----------------------------------------------------------------------------

-  cmp_sdb_crossbar : xwb_sdb_crossbar
+  cmp_sdb_crossbar : xwb_crossbar
    generic map (
      g_VERBOSE     => FALSE,
      g_NUM_MASTERS => c_NUM_WB_MASTERS,
      g_NUM_SLAVES  => c_NUM_WB_SLAVES,
      g_REGISTERED  => TRUE,
-      g_WRAPAROUND  => TRUE,
-      g_LAYOUT      => c_WB_LAYOUT,
-      g_SDB_ADDR    => c_SDB_ADDRESS)
+      g_ADDRESS     => c_WB_LAYOUT_ADDR,
+      g_MASK        => c_WB_LAYOUT_MASK)
    port map (
      clk_sys_i => clk_sys_62m5,
      rst_n_i   => rst_sys_62m5_n,
@@ -559,73 +624,6 @@ begin  -- architecture arch
      master_i  => cnx_slave_out,
      master_o  => cnx_slave_in);

-  -----------------------------------------------------------------------------
-  -- VME64x Core (WB Master)
-  -----------------------------------------------------------------------------
-
-  gen_with_vme64_core : if not g_SIM_BYPASS_VME generate
-    cmp_vme_core : xvme64x_core
-      generic map (
-        g_CLOCK_PERIOD    => 16,
-        g_DECODE_AM       => TRUE,
-        g_USER_CSR_EXT    => FALSE,
-        g_WB_GRANULARITY  => BYTE,
-        g_MANUFACTURER_ID => c_CERN_ID,
-        g_BOARD_ID        => c_SVEC_ID,
-        g_REVISION_ID     => c_SVEC_REVISION_ID,
-        g_PROGRAM_ID      => c_SVEC_PROGRAM_ID)
-      port map (
-        clk_i           => clk_sys_62m5,
-        rst_n_i         => rst_sys_62m5_n,
-        vme_i.as_n      => vme_as_n_i,
-        vme_i.rst_n     => vme_sysreset_n_i,
-        vme_i.write_n   => vme_write_n_i,
-        vme_i.am        => vme_am_i,
-        vme_i.ds_n      => vme_ds_n_i,
-        vme_i.ga        => vme_ga,
-        vme_i.lword_n   => vme_lword_n_b,
-        vme_i.addr      => vme_addr_b,
-        vme_i.data      => vme_data_b,
-        vme_i.iack_n    => vme_iack_n_i,
-        vme_i.iackin_n  => vme_iackin_n_i,
-        vme_o.berr_n    => vme_berr_n,
-        vme_o.dtack_n   => vme_dtack_n_o,
-        vme_o.retry_n   => vme_retry_n_o,
-        vme_o.retry_oe  => vme_retry_oe_o,
-        vme_o.lword_n   => vme_lword_n_b_out,
-        vme_o.data      => vme_data_b_out,
-        vme_o.addr      => vme_addr_b_out,
-        vme_o.irq_n     => vme_irq_n,
-        vme_o.iackout_n => vme_iackout_n_o,
-        vme_o.dtack_oe  => vme_dtack_oe_o,
-        vme_o.data_dir  => vme_data_dir_int,
-        vme_o.data_oe_n => vme_data_oe_n_o,
-        vme_o.addr_dir  => vme_addr_dir_int,
-        vme_o.addr_oe_n => vme_addr_oe_n_o,
-        wb_o            => cnx_master_out(c_WB_MASTER_VME),
-        wb_i            => cnx_master_in(c_WB_MASTER_VME),
-        int_i           => vic_master_irq);
-
-    vme_ga     <= vme_gap_i & vme_ga_i;
-    vme_berr_o <= not vme_berr_n;
-    vme_irq_o  <= not vme_irq_n;
-
-    -- VME tri-state buffers
-    vme_data_b    <= vme_data_b_out    when vme_data_dir_int = '1' else (others => 'Z');
-    vme_addr_b    <= vme_addr_b_out    when vme_addr_dir_int = '1' else (others => 'Z');
-    vme_lword_n_b <= vme_lword_n_b_out when vme_addr_dir_int = '1' else 'Z';
-
-    vme_addr_dir_o <= vme_addr_dir_int;
-    vme_data_dir_o <= vme_data_dir_int;
-  end generate gen_with_vme64_core;
-
-  gen_without_vme64_core : if g_SIM_BYPASS_VME generate
-    -- synthesis translate_off
-    cnx_master_out(c_WB_MASTER_VME) <= sim_wb_i;
-    sim_wb_o                        <= cnx_master_in(c_WB_MASTER_VME);
-  -- synthesis translate_on
-  end generate gen_without_vme64_core;
-
  cmp_vme_led_extend : gc_extend_pulse
    generic map (
      g_width => 5000000)
@@ -635,29 +633,6 @@ begin  -- architecture arch
      pulse_i    => cnx_slave_in(c_WB_MASTER_VME).cyc,
      extended_o => vme_access_led);

-  -----------------------------------------------------------------------------
-  -- Vectored Interrupt Controller (WB Slave)
-  -----------------------------------------------------------------------------
-
-  cmp_vic : xwb_vic
-    generic map (
-      g_INTERFACE_MODE      => PIPELINED,
-      g_ADDRESS_GRANULARITY => BYTE,
-      g_NUM_INTERRUPTS      => 6,
-      g_INIT_VECTORS        => c_VIC_VECTOR_TABLE)
-    port map (
-      clk_sys_i    => clk_sys_62m5,
-      rst_n_i      => rst_sys_62m5_n,
-      slave_i      => cnx_slave_in(c_WB_SLAVE_VIC),
-      slave_o      => cnx_slave_out(c_WB_SLAVE_VIC),
-      irqs_i(0)    => fmc_host_irq(0),
-      irqs_i(1)    => fmc_host_irq(1),
-      irqs_i(2)    => mt_hmq_in_irq,
-      irqs_i(3)    => mt_hmq_out_irq,
-      irqs_i(4)    => mt_console_irq,
-      irqs_i(5)    => mt_notify_irq,
-      irq_master_o => vic_master_irq);
-
  -----------------------------------------------------------------------------
  -- Mock Turtle (WB Slave)
  -----------------------------------------------------------------------------
@@ -681,10 +656,10 @@ begin  -- architecture arch
      host_slave_o   => cnx_slave_out(c_WB_SLAVE_MT),
      clk_ref_i      => clk_ref_125m,
      tm_i           => tm,
-      hmq_in_irq_o   => mt_hmq_in_irq,
-      hmq_out_irq_o  => mt_hmq_out_irq,
-      notify_irq_o   => mt_notify_irq,
-      console_irq_o  => mt_console_irq);
+      hmq_in_irq_o   => irq_vector(2),
+      hmq_out_irq_o  => irq_vector(3),
+      notify_irq_o   => irq_vector(5),
+      console_irq_o  => irq_vector(4));

  tm.cycles                 <= tm_cycles;
  tm.tai                    <= tm_tai;
@@ -730,102 +705,11 @@ begin  -- architecture arch

  end process p_rmq_assign;

-  -----------------------------------------------------------------------------
-  -- The WR PTP core SVEC board package (WB Slave)
-  -----------------------------------------------------------------------------
-
-  cmp_xwrc_board_svec : xwrc_board_svec
-    generic map (
-      g_SIMULATION                => g_SIMULATION,
-      g_VERBOSE                   => FALSE,
-      g_WITH_EXTERNAL_CLOCK_INPUT => TRUE,
-      g_DPRAM_INITF               => g_WRPC_INITF,
-      g_AUX_CLKS                  => 2)
-    port map (
-      clk_20m_vcxo_i       => clk_20m_vcxo_i,
-      clk_125m_pllref_p_i  => clk_125m_pllref_p_i,
-      clk_125m_pllref_n_i  => clk_125m_pllref_n_i,
-      clk_125m_gtp_n_i     => clk_125m_gtp_n_i,
-      clk_125m_gtp_p_i     => clk_125m_gtp_p_i,
-      clk_10m_ext_i        => clk_ext_ref,
-      clk_aux_i(0)         => tdc_clk_125m,
-      clk_aux_i(1)         => dcm1_clk_ref_0,
-      areset_n_i           => areset_n,
-      clk_sys_62m5_o       => clk_sys_62m5,
-      clk_ref_125m_o       => clk_ref_125m,
-      rst_sys_62m5_n_o     => rst_sys_62m5_n,
-      pll20dac_din_o       => pll20dac_din_o,
-      pll20dac_sclk_o      => pll20dac_sclk_o,
-      pll20dac_sync_n_o    => pll20dac_sync_n_o,
-      pll25dac_din_o       => pll25dac_din_o,
-      pll25dac_sclk_o      => pll25dac_sclk_o,
-      pll25dac_sync_n_o    => pll25dac_sync_n_o,
-      sfp_txp_o            => sfp_txp_o,
-      sfp_txn_o            => sfp_txn_o,
-      sfp_rxp_i            => sfp_rxp_i,
-      sfp_rxn_i            => sfp_rxn_i,
-      sfp_det_i            => sfp_mod_def0_i,
-      sfp_sda_i            => sfp_sda_in,
-      sfp_sda_o            => sfp_sda_out,
-      sfp_scl_i            => sfp_scl_in,
-      sfp_scl_o            => sfp_scl_out,
-      sfp_rate_select_o    => sfp_rate_select_o,
-      sfp_tx_fault_i       => sfp_tx_fault_i,
-      sfp_tx_disable_o     => sfp_tx_disable_o,
-      sfp_los_i            => sfp_los_i,
-      eeprom_sda_i         => eeprom_sda_in,
-      eeprom_sda_o         => eeprom_sda_out,
-      eeprom_scl_i         => eeprom_scl_in,
-      eeprom_scl_o         => eeprom_scl_out,
-      onewire_i            => onewire_data,
-      onewire_oen_o        => onewire_oe,
-      uart_rxd_i           => uart_rxd_i,
-      uart_txd_o           => uart_txd_o,
-      spi_sclk_o           => spi_sclk_o,
-      spi_ncs_o            => spi_ncs_o,
-      spi_mosi_o           => spi_mosi_o,
-      spi_miso_i           => spi_miso_i,
-      wb_slave_o           => cnx_slave_out(c_WB_SLAVE_WRC),
-      wb_slave_i           => cnx_slave_in(c_WB_SLAVE_WRC),
-      wrf_src_o            => eth_rx_in,
-      wrf_src_i            => eth_rx_out,
-      wrf_snk_o            => eth_tx_in,
-      wrf_snk_i            => eth_tx_out,
-      tm_link_up_o         => tm_link_up,
-      tm_time_valid_o      => tm_time_valid,
-      tm_tai_o             => tm_tai,
-      tm_cycles_o          => tm_cycles,
-      tm_dac_value_o       => tm_dac_value,
-      tm_dac_wr_o          => tm_dac_wr,
-      tm_clk_aux_lock_en_i => tm_clk_aux_lock_en,
-      tm_clk_aux_locked_o  => tm_clk_aux_locked,
-      pps_ext_i            => pps_ext_in,
-      pps_p_o              => pps,
-      pps_led_o            => pps_led,
-      led_link_o           => wr_led_link,
-      led_act_o            => wr_led_act);
-
-  -- tri-state Carrier EEPROM
-  carrier_sda_b <= '0' when (eeprom_sda_out = '0') else 'Z';
-  eeprom_sda_in <= carrier_sda_b;
-  carrier_scl_b <= '0' when (eeprom_scl_out = '0') else 'Z';
-  eeprom_scl_in <= carrier_scl_b;
-
-  -- Tristates for SFP EEPROM
-  sfp_mod_def1_b <= '0' when sfp_scl_out = '0' else 'Z';
-  sfp_mod_def2_b <= '0' when sfp_sda_out = '0' else 'Z';
-  sfp_scl_in     <= sfp_mod_def1_b;
-  sfp_sda_in     <= sfp_mod_def2_b;
-
-  -- tri-state onewire access
-  carrier_onewire_b    <= '0' when (onewire_oe = '1') else 'Z';
-  onewire_data         <= carrier_onewire_b;
-
  -----------------------------------------------------------------------------
  -- FMC TDC (SVEC slot #1)
  -----------------------------------------------------------------------------

-  U_TDC_Core : fmc_tdc_wrapper
+  U_TDC_Core : entity work.fmc_tdc_wrapper
    generic map (
      g_SIMULATION          => f_int2bool(g_SIMULATION),
      g_WITH_DIRECT_READOUT => TRUE)
@@ -868,10 +752,10 @@ begin  -- architecture arch
      tdc_led_trig3_o      => fmc0_tdc_led_trig3_o,
      tdc_led_trig4_o      => fmc0_tdc_led_trig4_o,
      tdc_led_trig5_o      => fmc0_tdc_led_trig5_o,
-      mezz_scl_i           => fmc0_scl_b,
-      mezz_sda_i           => fmc0_sda_b,
-      mezz_scl_o           => fmc0_scl_out,
-      mezz_sda_o           => fmc0_sda_out,
+      mezz_scl_i           => '0',
+      mezz_sda_i           => '0',
+      mezz_scl_o           => open,
+      mezz_sda_o           => open,
      mezz_one_wire_b      => fmc0_tdc_one_wire_b,
      tm_link_up_i         => tm_link_up,
      tm_time_valid_i      => tm_time_valid,
@@ -886,17 +770,13 @@ begin  -- architecture arch
      direct_slave_o       => fmc_dp_wb_in(0),
      slave_i              => cnx_slave_in(c_WB_SLAVE_TDC),
      slave_o              => cnx_slave_out(c_WB_SLAVE_TDC),
-      irq_o                => fmc_host_irq(0),
+      irq_o                => irq_vector(0),
      clk_125m_tdc_o       => tdc_clk_125m);

-  fmc0_scl_b <= '0' when fmc0_scl_out = '0' else 'Z';
-  fmc0_sda_b <= '0' when fmc0_sda_out = '0' else 'Z';
-
  -----------------------------------------------------------------------------
  -- FMC FDELAY (SVEC slot #2)
  -----------------------------------------------------------------------------

-
  cmp_fd_tdc_start1 : IBUFDS
    generic map (
      DIFF_TERM    => TRUE,
@@ -906,7 +786,7 @@ begin  -- architecture arch
      I  => fmc1_fd_tdc_start_p_i,
      IB => fmc1_fd_tdc_start_n_i);

-  U_DDR_PLL1 : fd_ddr_pll
+  U_DDR_PLL1 : entity work.fd_ddr_pll
    port map (
      RST       => ddr1_pll_reset,
      LOCKED    => ddr1_pll_locked,
@@ -918,7 +798,7 @@ begin  -- architecture arch
  ddr1_pll_reset     <= not fmc1_fd_pll_status_i;
  fmc1_fd_pll_status <= fmc1_fd_pll_status_i and ddr1_pll_locked;

-  U_FineDelay_Core : fine_delay_core
+  U_FineDelay_Core : entity work.fine_delay_core
    generic map (
      g_WITH_WR_CORE        => TRUE,
      g_SIMULATION          => f_int2bool(g_SIMULATION),
@@ -970,11 +850,11 @@ begin  -- architecture arch
      tm_dac_wr_i          => tm_dac_wr(1),
      owr_en_o             => fmc1_fd_owr_en,
      owr_i                => fmc1_fd_owr_in,
-      i2c_scl_oen_o        => fmc1_fd_scl_out,
-      i2c_scl_i            => fmc1_fd_scl_in,
-      i2c_sda_oen_o        => fmc1_fd_sda_out,
-      i2c_sda_i            => fmc1_fd_sda_in,
-      fmc_present_n_i      => fmc1_prsntm2c_n_i,
+      i2c_scl_oen_o        => open,
+      i2c_scl_i            => '0',
+      i2c_sda_oen_o        => open,
+      i2c_sda_i            => '0',
+      fmc_present_n_i      => '0',
      wb_adr_i             => fmc1_mux_wb_out.adr,
      wb_dat_i             => fmc1_mux_wb_out.dat,
      wb_dat_o             => fmc1_mux_wb_in.dat,
@@ -984,7 +864,7 @@ begin  -- architecture arch
      wb_we_i              => fmc1_mux_wb_out.we,
      wb_ack_o             => fmc1_mux_wb_in.ack,
      wb_stall_o           => fmc1_mux_wb_in.stall,
-      wb_irq_o             => fmc_host_irq(1));
+      wb_irq_o             => irq_vector(1));

  cmp_fmc1_wb_mux : xwb_crossbar
    generic map (
@@ -1015,11 +895,6 @@ begin  -- architecture arch
  fmc1_fd_onewire_b <= '0' when fmc1_fd_owr_en = '1' else 'Z';
  fmc1_fd_owr_in    <= fmc1_fd_onewire_b;

-  fmc1_scl_b     <= '0' when (fmc1_fd_scl_out = '0') else 'Z';
-  fmc1_sda_b     <= '0' when (fmc1_fd_sda_out = '0') else 'Z';
-  fmc1_fd_scl_in <= fmc1_scl_b;
-  fmc1_fd_sda_in <= fmc1_sda_b;
-
  -----------------------------------------------------------------------------
  -- Carrier front panel LEDs and LEMOs
  -----------------------------------------------------------------------------
@@ -1069,10 +944,10 @@ begin  -- architecture arch
  end process;

  -- Front panel IO configuration
-  fp_gpio1_o      <= pps;
-  fp_gpio2_o      <= clk_ref_div2;
-  clk_ext_ref     <= fp_gpio3_i;
-  pps_ext_in      <= fp_gpio4_i;
+  fp_gpio1_b      <= pps;
+  fp_gpio2_b      <= clk_ref_div2;
+  clk_ext_ref     <= fp_gpio3_b;
+  pps_ext_in      <= fp_gpio4_b;
  fp_term_en_o    <= (others => '0');
  fp_gpio1_a2b_o  <= '1';
  fp_gpio2_a2b_o  <= '1';