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White Rabbit Trigger Distribution
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White Rabbit Trigger Distribution
Commits
59fd5f6f
Commit
59fd5f6f
authored
Aug 22, 2018
by
Tristan Gingold
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testbench: now PASS/FAIL tb.
parent
3958abbf
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2 changed files
with
66 additions
and
12 deletions
+66
-12
main.sv
hdl/testbench/wrtd-system/main.sv
+65
-11
wrtd-rt-fd.c
software/firmware/fd/wrtd-rt-fd.c
+1
-1
No files found.
hdl/testbench/wrtd-system/main.sv
View file @
59fd5f6f
...
...
@@ -62,7 +62,7 @@ module simple_tdc_driver
assign
data
=
rdata
;
assign
intflag
=
start
[
7
]
;
task
pulse
(
int
channel
,
time
ts
)
;
task
pu
sh_pu
lse
(
int
channel
,
time
ts
)
;
pulses
.
push_back
(
'
{
channel
:
channel
,
ts
:
ts
}
)
;
endtask
...
...
@@ -159,8 +159,52 @@ module simple_fdelay_mon
input
[
3
:
0
]
pulse
)
;
always
@
pulse
begin
$
display
(
"[FDEL] <%t> Pulse: len=%x, val=%x, out=%x"
,
$
time
,
len
,
val
,
pulse
)
;
typedef
struct
{
int
channel
;
time
ts
;
}
fifo_entry
;
fifo_entry
pulses
[$]
;
task
push_pulse
(
int
channel
,
time
ts
)
;
pulses
.
push_back
(
'
{
channel
:
channel
,
ts
:
ts
}
)
;
endtask
initial
begin
reg
[
3
:
0
]
prev
;
time
now
;
// Do nothing before 100us, hw is not initialized.
#
100u
s
;
prev
=
0
;
while
(
pulses
.
size
()
!=
0
)
begin
@
pulse
;
now
=
$
time
;
$
display
(
"[FDEL] <%t> Pulse: len=%x, val=%x, out=%x"
,
now
,
len
,
val
,
pulse
)
;
for
(
int
i
=
0
;
i
<
4
;
i
++
)
begin
if
(
prev
[
i
]
==
1'b0
&&
pulse
[
i
]
==
1'b1
)
begin
automatic
fifo_entry
e
=
pulses
.
pop_front
()
;
automatic
time
diff
;
$
display
(
"[FDEL] pulse on channel %d"
,
i
)
;
if
(
e
.
channel
!=
i
)
begin
$
display
(
"FAIL: [FDEL] Bad channel (expected %d)"
,
e
.
channel
)
;
$
finish
(
1
)
;
end
diff
=
now
-
e
.
ts
;
if
(
diff
>
2u
s
&&
diff
<
-
2u
s
)
begin
$
display
(
"FAIL: [FDEL] Bad timestamp: pulse at %t, expected at %t"
,
now
,
e
.
ts
)
;
$
finish
(
1
)
;
end
end
end
prev
=
pulse
;
end
$
display
(
"SUCCESS: done"
)
;
$
finish
(
0
)
;
end
endmodule
// simple_fdelay_mon
...
...
@@ -372,16 +416,26 @@ module main;
force
DUT_B
.
cmp_xwrc_board_svec
.
cmp_board_common
.
cmp_xwr_core
.
WRPC
.
LM32_CORE
.
gen_profile_medium_icache
.
U_Wrapped_LM32
.
cpu
.
multiplier
.
D3
.
OPMODE_dly
=
0
;
end
// initial begin
#
200u
s
;
task
push_pulse
(
int
channel
,
time
ts
)
;
TDC
.
push_pulse
(
channel
,
ts
)
;
FDL
.
push_pulse
(
channel
,
ts
+
100u
s
)
;
// Delay time (from fd firmware)
endtask
forever
begin
#
200u
s
;
TDC
.
pulse
(
0
,
$
time
+
10u
s
)
;
TDC
.
pulse
(
1
,
$
time
+
20u
s
)
;
TDC
.
pulse
(
2
,
$
time
+
30u
s
)
;
end
initial
begin
// No pulse before: WR (300us) + TDC setup.
automatic
time
start
=
480u
s
;
push_pulse
(
0
,
start
+
10u
s
)
;
push_pulse
(
1
,
start
+
30u
s
)
;
push_pulse
(
2
,
start
+
50u
s
)
;
end
// initial begin others
#(
start
+
200u
s
)
;
// Should have been finished by the FD monitor.
$
display
(
"FAILED"
)
;
$
finish
(
1
)
;
end
endmodule
// main
software/firmware/fd/wrtd-rt-fd.c
View file @
59fd5f6f
...
...
@@ -911,7 +911,7 @@ static int wrtd_o_sim_init(void)
triggers
[
i
].
id
.
source_port
=
i
;
triggers
[
i
].
id
.
trigger
=
i
;
triggers
[
i
].
flags
=
ENTRY_FLAG_VALID
;
triggers
[
i
].
ocfg
[
i
].
delay_cycles
=
2
00
*
125
;
// 1 cycle is 8ns
triggers
[
i
].
ocfg
[
i
].
delay_cycles
=
1
00
*
125
;
// 1 cycle is 8ns
triggers
[
i
].
ocfg
[
i
].
delay_frac
=
0
;
triggers
[
i
].
ocfg
[
i
].
state
=
HASH_ENT_DIRECT
;
...
...
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