Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
W
White Rabbit Trigger Distribution
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
0
Issues
0
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Projects
White Rabbit Trigger Distribution
Commits
578850fb
Commit
578850fb
authored
Jul 12, 2019
by
Dimitris Lampridis
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
[hdl] convert WRTD SPEC FMC-ADC reference node to the Convention (synthesized, not tested)
parent
308fb6b2
Expand all
Hide whitespace changes
Inline
Side-by-side
Showing
6 changed files
with
181 additions
and
602 deletions
+181
-602
.gitmodules
.gitmodules
+3
-0
general-cores
dependencies/general-cores
+1
-1
spec
dependencies/spec
+1
-0
wrtd_ref_spec150t_adc.ucf
hdl/syn/wrtd_ref_spec150t_adc/wrtd_ref_spec150t_adc.ucf
+14
-14
Manifest.py
hdl/top/wrtd_ref_spec150t_adc/Manifest.py
+1
-0
wrtd_ref_spec150t_adc.vhd
hdl/top/wrtd_ref_spec150t_adc/wrtd_ref_spec150t_adc.vhd
+161
-587
No files found.
.gitmodules
View file @
578850fb
...
...
@@ -28,3 +28,6 @@
[submodule "dependencies/gn4124-core"]
path = dependencies/gn4124-core
url = https://ohwr.org/project/gn4124-core.git
[submodule "dependencies/spec"]
path = dependencies/spec
url = https://ohwr.org/project/spec.git
general-cores
@
c010febb
Subproject commit
28cd756047ce9f85cf7c134367c7439f1189114d
Subproject commit
c010febba58a1b616c971f6fd8c953df51e411b6
spec
@
ed94f859
Subproject commit ed94f8594009fda6deafde22532fb48c321792b9
hdl/syn/wrtd_ref_spec150t_adc/wrtd_ref_spec150t_adc.ucf
View file @
578850fb
...
...
@@ -222,7 +222,7 @@ TIMESPEC TS_clk_125m_gtp_n_i = PERIOD "clk_125m_gtp_n_i" 8 ns HIGH 50%;
NET "clk_20m_vcxo_i" TNM_NET = "clk_20m_vcxo_i";
TIMESPEC TS_clk_20m_vcxo_i = PERIOD "clk_20m_vcxo_i" 50 ns HIGH 50%;
NET "cmp_xwrc_board_spec/*/gen_phy_spartan6.cmp_gtp/ch1_gtp_clkout_int<1>" TNM_NET = wrc_gtp_clk;
NET "
*/
cmp_xwrc_board_spec/*/gen_phy_spartan6.cmp_gtp/ch1_gtp_clkout_int<1>" TNM_NET = wrc_gtp_clk;
TIMESPEC TS_wrc_gtp_clk = PERIOD "wrc_gtp_clk" 8 ns HIGH 50%;
NET "gn_p2l_clk_n_i" TNM_NET = "p2l_clk";
...
...
@@ -252,13 +252,13 @@ NET "*/gc_reset_async_in" TIG;
#----------------------------------------
# Declaration of domains
NET "c
lk_sys_62m5"
TNM_NET = sys_clk_62_5;
NET "c
lk_ref_125m"
TNM_NET = clk_125m_pllref;
NET "c
lk_ddr_333m"
TNM_NET = ddr_clk_333m;
NET "
cmp_xwrc_board_spec/clk_pll_dmtd"
TNM_NET = clk_dmtd;
NET "
cmp_xwrc_board_spec/phy8_to_wrc_rx_clk"
TNM_NET = phy_clk;
NET "cmp_gn4124_core/cmp_wrapped_gn4124/sys_clk" TNM_NET = pci_sys_clk;
NET "cmp_gn4124_core/cmp_wrapped_gn4124/io_clk" TNM_NET = pci_io_clk;
NET "c
mp_spec_template_wr/clk_sys_62m5"
TNM_NET = sys_clk_62_5;
NET "c
mp_spec_template_wr/clk_ref_125m"
TNM_NET = clk_125m_pllref;
NET "c
mp_spec_template_wr/clk_ddr_333m"
TNM_NET = ddr_clk_333m;
NET "
*/cmp_xwrc_board_spec/clk_pll_dmtd"
TNM_NET = clk_dmtd;
NET "
*/cmp_xwrc_board_spec/phy8_to_wrc_rx_clk"
TNM_NET = phy_clk;
NET "
*/
cmp_gn4124_core/cmp_wrapped_gn4124/sys_clk" TNM_NET = pci_sys_clk;
NET "
*/
cmp_gn4124_core/cmp_wrapped_gn4124/io_clk" TNM_NET = pci_io_clk;
TIMEGRP "sys_clk" = "sys_clk_62_5" "clk_125m_pllref";
TIMEGRP "pci_clk" = "pci_sys_clk" "pci_io_clk";
...
...
@@ -479,17 +479,17 @@ TIMESPEC TS_fmc0_adc_dco_n_i = PERIOD "fmc0_adc_dco_n_i" 2.5 ns HIGH 50%;
# These are suggested by the Xilinx-generated MCB.
# More info in the UCF file found in the "user_design/par" of the generated core.
NET "
cmp_ddr0_ctrl_bank
/*/c?_pll_lock" TIG;
NET "
cmp_ddr0_ctrl_bank
/*/memc?_mcb_raw_wrapper_inst/selfrefresh_mcb_mode" TIG;
NET "
cmp_ddr0_ctrl_bank
/*/mcb_soft_calibration_inst/DONE_SOFTANDHARD_CAL*" TIG;
#ERR NET "
cmp_ddr0_ctrl_bank
/*/mcb_soft_calibration_inst/SELFREFRESH_MCB_REQ" TIG;
NET "
*/cmp_ddr_ctrl_bank3
/*/c?_pll_lock" TIG;
NET "
*/cmp_ddr_ctrl_bank3
/*/memc?_mcb_raw_wrapper_inst/selfrefresh_mcb_mode" TIG;
NET "
*/cmp_ddr_ctrl_bank3
/*/mcb_soft_calibration_inst/DONE_SOFTANDHARD_CAL*" TIG;
#ERR NET "
*/cmp_ddr_ctrl_bank3
/*/mcb_soft_calibration_inst/SELFREFRESH_MCB_REQ" TIG;
#----------------------------------------
# Asynchronous resets
#----------------------------------------
# Ignore async reset to DDR controller
NET "
ddr0
_rst" TPTHRU = ddr_rst;
NET "
cmp_spec_template_wr/ddr
_rst" TPTHRU = ddr_rst;
TIMESPEC TS_ddr_rst_tig = FROM FFS THRU ddr_rst TIG;
#----------------------------------------
...
...
@@ -498,7 +498,7 @@ TIMESPEC TS_ddr_rst_tig = FROM FFS THRU ddr_rst TIG;
NET "cmp0_fmc_adc_mezzanine/cmp_fmc_adc_100Ms_core/fs_clk" TNM_NET = fs_clk;
NET "
cmp_ddr0_ctrl_bank
/*/memc3_infrastructure_inst/mcb_drp_clk_bufg_in" TNM_NET = ddr0_bank3_clk;
NET "
*/cmp_ddr_ctrl_bank3
/*/memc3_infrastructure_inst/mcb_drp_clk_bufg_in" TNM_NET = ddr0_bank3_clk;
TIMEGRP "ddr0_clk" = "ddr0_clk_333m" "ddr0_bank3_clk";
...
...
hdl/top/wrtd_ref_spec150t_adc/Manifest.py
View file @
578850fb
...
...
@@ -15,6 +15,7 @@ modules = {
"https://ohwr.org/project/mock-turtle.git"
,
"https://ohwr.org/project/ddr3-sp6-core.git"
,
"https://ohwr.org/project/gn4124-core.git"
,
"https://ohwr.org/project/spec.git"
,
"https://ohwr.org/project/fmc-adc-100m14b4cha-gw.git"
,
],
}
hdl/top/wrtd_ref_spec150t_adc/wrtd_ref_spec150t_adc.vhd
View file @
578850fb
This diff is collapsed.
Click to expand it.
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment