Skip to content

W
White Rabbit Trigger Distribution
Commit 42c26287 authored by Dimitris Lampridis's avatar Dimitris Lampridis
Browse files
Options

hdl: move and rename old list project to wrtd_ref_svec_tdc_fd

parent f883a9ab
Hide whitespace changes
Inline Side-by-side
Showing with 29 additions and 24 deletions
hdl/syn/svec/list_tdc_fd/Manifest.py → hdl/syn/wrtd_ref_svec_tdc_fd/Manifest.py
View file @ 42c26287
......@@ -10,11 +10,11 @@ action = "synthesis"
syn_device = "xc6slx150t"
syn_grade = "-3"
syn_package = "fgg900"
syn_top = "svec_list_top"
syn_project = "svec_list_tdc_fd.xise"
syn_top = "wrtd_ref_svec_tdc_fd"
syn_project = "wrtd_ref_svec_tdc_fd.xise"
syn_tool = "ise"
fetchto = "../../../../dependencies"
fetchto = "../../../dependencies"
syn_post_project_cmd = (
"$(TCL_INTERPRETER) " + \
......@@ -24,11 +24,11 @@ syn_post_project_cmd = (
)
files = [
"svec_list_top.ucf",
"wrtd_ref_svec_tdc_fd.ucf",
]
modules = {
"local" : [
"../../../top/svec/list_tdc_fd",
"../../top/wrtd_ref_svec_tdc_fd",
],
}
hdl/testbench/Makefile
View file @ 42c26287
......@@ -3,7 +3,7 @@
#
# Author: Adam Wujek, CERN 2017
TB_DIRS=list
TB_DIRS=wrtd_ref_svec_tdc_fd
test_results_xml=test_results.xml
.PHONY: $(TB_DIRS)
......
hdl/testbench/list/Manifest.py → hdl/testbench/wrtd_ref_svec_tdc_fd/Manifest.py
View file @ 42c26287
......@@ -27,6 +27,6 @@ files = [
modules = {
"local" : [
"../../top/svec/list_tdc_fd",
"../../top/wrtd_ref_svec_tdc_fd",
],
}
hdl/testbench/list/main.sv → hdl/testbench/wrtd_ref_svec_tdc_fd/main.sv
View file @ 42c26287
......@@ -259,7 +259,7 @@ module main;
.intflag(tdc_int)
);
svec_list_top #
wrtd_ref_svec_tdc_fd #
(
.g_simulation (1),
.g_sim_bypass_vme (1),
......@@ -334,7 +334,7 @@ module main;
.pulse (fdl_pulse)
);
svec_list_top #
wrtd_ref_svec_tdc_fd #
(
.g_simulation (1),
.g_sim_bypass_vme (1),
......
hdl/top/svec/list_tdc_fd/Manifest.py → hdl/top/wrtd_ref_svec_tdc_fd/Manifest.py
View file @ 42c26287
files = [
"svec_list_top.vhd",
"wrtd_ref_svec_tdc_fd.vhd",
]
fetchto = "../../../../dependencies"
fetchto = "../../../dependencies"
modules = {
"git" : [
......
hdl/top/svec/list_tdc_fd/svec_list_top.vhd → hdl/top/wrtd_ref_svec_tdc_fd/wrtd_ref_svec_tdc_fd.vhd
View file @ 42c26287
--------------------------------------------------------------------------------
-- CERN BE-CO-HT
-- LHC Instability Trigger Distribution (LIST)
-- https://ohwr.org/projects/list
-- White Rabbit Trigger Distribution
-- https://ohwr-gitlab.cern.ch/projects/wrtd
--------------------------------------------------------------------------------
--
-- unit name: svec_list_top
-- unit name: wrtd_ref_svec_tdc_fd
--
-- description: Top entity for LHC Instability Trigger Distribution project
-- description: Top entity for WRTD reference design
--
-- Top level design of the SVEC-based LIST WR trigger distribution node, with
-- an FMC TDC in slot and an FMC Fine Delay in slot 2.
-- Top level design of the SVEC-based WRTD node, with
-- an FMC TDC in slot 1 and an FMC Fine Delay in slot 2.
--
-- This is the standard pulse-in/pulse-out WRTD node, with the FMC TDC
-- injecting pulses into the WR network in the form of WRTD messages and
-- the FMC Fine Delay converting those messages back to pulses at the
-- destination.
--
--------------------------------------------------------------------------------
-- Copyright CERN 2014-2018
-- Copyright CERN 2014-2019
--------------------------------------------------------------------------------
-- Copyright and related rights are licensed under the Solderpad Hardware
-- License, Version 2.0 (the "License"); you may not use this file except
......@@ -45,11 +50,11 @@ use work.synthesis_descriptor.all;
library unisim;
use unisim.vcomponents.all;
entity svec_list_top is
entity wrtd_ref_svec_tdc_fd is
generic (
g_WR_DPRAM_INITF : string := "../../../../dependencies/wr-cores/bin/wrpc/wrc_phy8.bram";
g_MT_CPU0_INITF : string := "../../../../software/firmware/tdc/wrtd-rt-tdc.bram";
g_MT_CPU1_INITF : string := "../../../../software/firmware/fd/wrtd-rt-fd.bram";
g_WR_DPRAM_INITF : string := "../../../dependencies/wr-cores/bin/wrpc/wrc_phy8.bram";
g_MT_CPU0_INITF : string := "../../../software/firmware/tdc/wrtd-rt-tdc.bram";
g_MT_CPU1_INITF : string := "../../../software/firmware/fd/wrtd-rt-fd.bram";
-- Simulation-mode enable parameter. Set by default (synthesis) to 0, and
-- changed to non-zero in the instantiation of the top level DUT in the
-- testbench. Its purpose is to reduce some internal counters/timeouts
......@@ -296,9 +301,9 @@ entity svec_list_top is
fmc1_scl_b : inout std_logic;
fmc1_sda_b : inout std_logic);
end entity svec_list_top;
end entity wrtd_ref_svec_tdc_fd;
architecture arch of svec_list_top is
architecture arch of wrtd_ref_svec_tdc_fd is
-----------------------------------------------------------------------------
-- Components
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment