[hdl] fix FMC slot identification of FMC-DEL in SVEC_TDC_FD ref design

2fbd1d5e · Dimitris Lampridis · 5d422f50 · 9b7a0f77 · 2fbd1d5e
Commit 2fbd1d5e authored Sep 25, 2019 by Dimitris Lampridis
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fmc-delay-1ns-8cha dependencies/fmc-delay-1ns-8cha +1 -1

wrtd_ref_svec_tdc_fd.vhd hdl/top/wrtd_ref_svec_tdc_fd/wrtd_ref_svec_tdc_fd.vhd +1 -0

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--- a/fmc-delay-1ns-8cha @ 9b7a0f77
+++ b/fmc-delay-1ns-8cha @ 9b7a0f77
-Subproject commit eca0894f19702d58d1d16bd4037cca5abc883812
+Subproject commit 9b7a0f777b2478fec19d9aa261c5ed12d6b082d2
--- a/hdl/top/wrtd_ref_svec_tdc_fd/wrtd_ref_svec_tdc_fd.vhd
+++ b/hdl/top/wrtd_ref_svec_tdc_fd/wrtd_ref_svec_tdc_fd.vhd
@@ -800,6 +800,7 @@ begin  -- architecture arch

  U_FineDelay_Core : entity work.fine_delay_core
    generic map (
+      g_FMC_SLOT_ID         => 1,
      g_WITH_WR_CORE        => TRUE,
      g_SIMULATION          => f_int2bool(g_SIMULATION),
      g_INTERFACE_MODE      => PIPELINED,