Commit 293ed47e authored by Dimitris Lampridis's avatar Dimitris Lampridis

Removed reference design files

All reference designs were moved to the wrtd-ref-designs repository.

https://ohwr.org/project/wrtd-ref-designs
parent 6e4b4ef4
[submodule "dependencies/mock-turtle"]
path = dependencies/mock-turtle
url = https://ohwr.org/project/mock-turtle.git
[submodule "dependencies/fine-delay"]
path = dependencies/fmc-delay-1ns-8cha
url = https://ohwr.org/project/fmc-delay-1ns-8cha.git
[submodule "dependencies/vme64x-core"]
path = dependencies/vme64x-core
url = https://ohwr.org/project/vme64x-core.git
[submodule "dependencies/general-cores"]
path = dependencies/general-cores
url = https://ohwr.org/project/general-cores.git
[submodule "dependencies/wr-cores"]
path = dependencies/wr-cores
url = https://ohwr.org/project/wr-cores.git
[submodule "dependencies/urv-core"]
path = dependencies/urv-core
url = https://ohwr.org/project/urv-core.git
[submodule "dependencies/ddr3-sp6-core"]
path = dependencies/ddr3-sp6-core
url = https://ohwr.org/project/ddr3-sp6-core.git
[submodule "dependencies/gn4124-core"]
path = dependencies/gn4124-core
url = https://ohwr.org/project/gn4124-core.git
[submodule "dependencies/spec"]
path = dependencies/spec
url = https://ohwr.org/project/spec.git
[submodule "dependencies/svec"]
path = dependencies/svec
url = https://ohwr.org/project/svec.git
[submodule "dependencies/fmc-tdc"]
path = dependencies/fmc-tdc
url = https://ohwr.org/project/fmc-tdc.git
branch = develop
[submodule "dependencies/fmc-adc-100m14b4cha"]
path = dependencies/fmc-adc-100m14b4cha
url = https://ohwr.org/project/fmc-adc-100m14b4cha.git
branch = master
Subproject commit 2b8c861b05504e2ebcc94c8f9f4746798a2c2a8a
Subproject commit b077d94f6bd7bd7834307fa3602ff4d3f526c33d
Subproject commit 2bdeecbd4f349f3e72c42373de84432286ae3306
Subproject commit 008e1996bce9d07f61fcc39a064ad6f4da18b97c
Subproject commit 1621d6d1f0c3040284136ce4b3b662269d6868d0
Subproject commit 461b30fe1f5e4e0c99f2265cdbf5843d31e31a4b
Subproject commit 483c3fc7306cec24a5e770dd548820c8cc3147f7
Subproject commit c0d76b045da18a333b11c35f3f0ed5c270790fa6
Subproject commit 193f15dbf7516fa1e0163156bbf41168c1f3044a
Subproject commit ca57317a1e4342d29791b77db10ff83364e6c8ac
Subproject commit 3884a65545907de3a0d41d549a4be9e6cccb4916
*
!.gitignore
!Manifest.py
!*.ucf
!syn_extra_steps.tcl
board = "spec"
target = "xilinx"
action = "synthesis"
syn_device = "xc6slx150t"
syn_grade = "-3"
syn_package = "fgg484"
syn_top = "wrtd_ref_spec150t_adc"
syn_project = "wrtd_ref_spec150t_adc.xise"
syn_tool = "ise"
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto = "../../../dependencies"
files = [
"wrtd_ref_spec150t_adc.ucf",
"buildinfo_pkg.vhd",
]
modules = {
"local" : [
"../../top/wrtd_ref_spec150t_adc",
],
}
syn_pre_project_cmd = "make -C ../../../software/firmware"
# Do not fail during hdlmake fetch
try:
exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
except:
pass
syn_post_project_cmd = "$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
spec_base_ucf = ['wr', 'ddr3', 'onewire', 'spi']
ctrls = ["bank3_64b_32b"]
# get project file from 1st command-line argument
set project_file [lindex $argv 0]
if {![file exists $project_file]} {
report ERROR "Missing file $project_file, exiting."
exit -1
}
xilinx::project open $project_file
# Some of these are not respected by ISE when passed through hdlmake,
# so we add them all ourselves after creating the project
#
# Not respected by ISE when passed through hdlmake:
# 1. Pack I/O Registers/Latches into IOBs
# 2. Register Duplication Map
xilinx::project set "Enable Multi-Threading" "2" -process "Map"
xilinx::project set "Enable Multi-Threading" "4" -process "Place & Route"
xilinx::project set "Pack I/O Registers into IOBs" "Yes"
xilinx::project set "Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs"
xilinx::project set "Register Balancing" "Yes"
xilinx::project set "Register Duplication Map" "On"
#xilinx::project set "Placer Extra Effort Map" "Normal"
#xilinx::project set "Extra Effort (Highest PAR level only)" "Normal"
xilinx::project save
xilinx::project close
#===============================================================================
# IO Location Constraints
#===============================================================================
#----------------------------------------
# FMC slot
#----------------------------------------
NET "fmc0_adc_ext_trigger_n_i" LOC = AB13;
NET "fmc0_adc_ext_trigger_p_i" LOC = Y13;
# dco_p and dco_n are swapped compared to the FMC ADC schematics
# this is to be coherent in the hdl design
NET "fmc0_adc_dco_n_i" LOC = AB11;
NET "fmc0_adc_dco_p_i" LOC = Y11;
# fr_p and fr_n are swapped compared to the FMC ADC schematics
# this is to be coherent in the hdl design
NET "fmc0_adc_fr_n_i" LOC = AB12;
NET "fmc0_adc_fr_p_i" LOC = AA12;
NET "fmc0_adc_outa_n_i[0]" LOC = AB4;
NET "fmc0_adc_outa_p_i[0]" LOC = AA4;
NET "fmc0_adc_outb_n_i[0]" LOC = W11;
NET "fmc0_adc_outb_p_i[0]" LOC = V11;
NET "fmc0_adc_outa_n_i[1]" LOC = Y12;
NET "fmc0_adc_outa_p_i[1]" LOC = W12;
NET "fmc0_adc_outb_n_i[1]" LOC = AB9;
NET "fmc0_adc_outb_p_i[1]" LOC = Y9;
NET "fmc0_adc_outa_n_i[2]" LOC = AB8;
NET "fmc0_adc_outa_p_i[2]" LOC = AA8;
NET "fmc0_adc_outb_n_i[2]" LOC = AB7;
NET "fmc0_adc_outb_p_i[2]" LOC = Y7;
NET "fmc0_adc_outa_n_i[3]" LOC = V9;
NET "fmc0_adc_outa_p_i[3]" LOC = U9;
NET "fmc0_adc_outb_n_i[3]" LOC = AB6;
NET "fmc0_adc_outb_p_i[3]" LOC = AA6;
NET "fmc0_adc_spi_din_i" LOC = T15;
NET "fmc0_adc_spi_dout_o" LOC = C18;
NET "fmc0_adc_spi_sck_o" LOC = D17;
NET "fmc0_adc_spi_cs_adc_n_o" LOC = V17;
NET "fmc0_adc_spi_cs_dac1_n_o" LOC = B20;
NET "fmc0_adc_spi_cs_dac2_n_o" LOC = A20;
NET "fmc0_adc_spi_cs_dac3_n_o" LOC = C19;
NET "fmc0_adc_spi_cs_dac4_n_o" LOC = A19;
NET "fmc0_adc_gpio_dac_clr_n_o" LOC = W18;
NET "fmc0_adc_gpio_led_acq_o" LOC = W15;
NET "fmc0_adc_gpio_led_trig_o" LOC = Y16;
NET "fmc0_adc_gpio_ssr_ch1_o[0]" LOC = Y17;
NET "fmc0_adc_gpio_ssr_ch1_o[1]" LOC = AB17;
NET "fmc0_adc_gpio_ssr_ch1_o[2]" LOC = AB18;
NET "fmc0_adc_gpio_ssr_ch1_o[3]" LOC = U15;
NET "fmc0_adc_gpio_ssr_ch1_o[4]" LOC = W14;
NET "fmc0_adc_gpio_ssr_ch1_o[5]" LOC = Y14;
NET "fmc0_adc_gpio_ssr_ch1_o[6]" LOC = W17;
NET "fmc0_adc_gpio_ssr_ch2_o[0]" LOC = R11;
NET "fmc0_adc_gpio_ssr_ch2_o[1]" LOC = AB15;
NET "fmc0_adc_gpio_ssr_ch2_o[2]" LOC = R13;
NET "fmc0_adc_gpio_ssr_ch2_o[3]" LOC = T14;
NET "fmc0_adc_gpio_ssr_ch2_o[4]" LOC = V13;
NET "fmc0_adc_gpio_ssr_ch2_o[5]" LOC = AA18;
NET "fmc0_adc_gpio_ssr_ch2_o[6]" LOC = W13;
NET "fmc0_adc_gpio_ssr_ch3_o[0]" LOC = R9;
NET "fmc0_adc_gpio_ssr_ch3_o[1]" LOC = R8;
NET "fmc0_adc_gpio_ssr_ch3_o[2]" LOC = T10;
NET "fmc0_adc_gpio_ssr_ch3_o[3]" LOC = U10;
NET "fmc0_adc_gpio_ssr_ch3_o[4]" LOC = W10;
NET "fmc0_adc_gpio_ssr_ch3_o[5]" LOC = Y10;
NET "fmc0_adc_gpio_ssr_ch3_o[6]" LOC = T11;
NET "fmc0_adc_gpio_ssr_ch4_o[0]" LOC = W6;
NET "fmc0_adc_gpio_ssr_ch4_o[1]" LOC = Y6;
NET "fmc0_adc_gpio_ssr_ch4_o[2]" LOC = V7;
NET "fmc0_adc_gpio_ssr_ch4_o[3]" LOC = W8;
NET "fmc0_adc_gpio_ssr_ch4_o[4]" LOC = T8;
NET "fmc0_adc_gpio_ssr_ch4_o[5]" LOC = Y5;
NET "fmc0_adc_gpio_ssr_ch4_o[6]" LOC = U8;
NET "fmc0_adc_gpio_si570_oe_o" LOC = AB5;
NET "fmc0_adc_si570_scl_b" LOC = U12;
NET "fmc0_adc_si570_sda_b" LOC = T12;
NET "fmc0_adc_one_wire_b" LOC = Y18;
# IO standards
NET "fmc0_adc_ext_trigger_?_i" IOSTANDARD = "LVDS_25";
NET "fmc0_adc_dco_?_i" IOSTANDARD = "LVDS_25";
NET "fmc0_adc_fr_?_i" IOSTANDARD = "LVDS_25";
NET "fmc0_adc_out?_?_i[*]" IOSTANDARD = "LVDS_25";
NET "fmc0_adc_spi_din_i" IOSTANDARD = "LVCMOS25";
NET "fmc0_adc_spi_dout_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_adc_spi_sck_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_adc_spi_cs_adc_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_adc_spi_cs_dac?_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_adc_gpio_dac_clr_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_adc_gpio_led_acq_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_adc_gpio_led_trig_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_adc_gpio_ssr_ch?_o[*]" IOSTANDARD = "LVCMOS25";
NET "fmc0_adc_gpio_si570_oe_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_adc_si570_scl_b" IOSTANDARD = "LVCMOS25";
NET "fmc0_adc_si570_sda_b" IOSTANDARD = "LVCMOS25";
NET "fmc0_adc_one_wire_b" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# PCB LEDs
#----------------------------------------
NET "aux_leds_o[0]" LOC = G19;
NET "aux_leds_o[1]" LOC = F20;
NET "aux_leds_o[2]" LOC = F18;
NET "aux_leds_o[3]" LOC = C20;
NET "aux_leds_o[*]" IOSTANDARD = "LVCMOS18";
#===============================================================================
# Timing constraints and exceptions
#===============================================================================
# Tightly constrain the location and max delay from the external trigger input
# to its synchroniser. This is needed to have consistent alignment between trigger
# and data across implementations. Note that due to RLOC constraints in the
# gc_sync_ffs, the synchroniser cannot be placed on the single FF of the IOB.
NET "cmp0_fmc_adc_mezzanine/*/cmp_ext_trig_sync/gc_sync_ffs_in" MAXDELAY = 1.5 ns;
INST "cmp0_fmc_adc_mezzanine/*/cmp_ext_trig_sync/sync0" RLOC_ORIGIN = X68Y2;
#----------------------------------------
# IOB exceptions
#----------------------------------------
INST "cmp0_fmc_adc_mezzanine/cmp_fmc_spi/*/Wrapped_SPI/shift/s_out" IOB = FALSE;
INST "cmp0_fmc_adc_mezzanine/cmp_fmc_spi/*/Wrapped_SPI/clgen/clk_out" IOB = FALSE;
INST "cmp0_fmc_adc_mezzanine/cmp_fmc_onewire/i_readout/*" IOB = FALSE;
#----------------------------------------
# Clocks
#----------------------------------------
NET "fmc0_adc_dco_p_i" TNM_NET = "fmc0_adc_dco";
NET "fmc0_adc_dco_n_i" TNM_NET = "fmc0_adc_dco";
TIMESPEC TS_fmc0_adc_dco_n_i = PERIOD "fmc0_adc_dco" 2.5 ns HIGH 50%;
#----------------------------------------
# Cross-clock domain sync
#----------------------------------------
NET "cmp0_fmc_adc_mezzanine/cmp_fmc_adc_100Ms_core/fs_clk" TNM_NET = fs_clk;
TIMEGRP "fmc_adc_sync_ffs" = "sync_ffs" EXCEPT "fs_clk";
TIMESPEC TS_adc_sync_ffs = FROM fs_clk TO "fmc_adc_sync_ffs" TIG;
TIMEGRP "fmc_adc_sync_reg" = "sync_reg" EXCEPT "fs_clk";
TIMESPEC TS_adc_sync_reg = FROM fs_clk TO "fmc_adc_sync_reg" 10ns DATAPATHONLY;
TIMESPEC TS_adc_sync_word = FROM sync_word TO fs_clk 30ns DATAPATHONLY;
*
!.gitignore
!Manifest.py
!*.ucf
!syn_extra_steps.tcl
board = "svec"
target = "xilinx"
action = "synthesis"
syn_device = "xc6slx150t"
syn_grade = "-3"
syn_package = "fgg900"
syn_top = "wrtd_ref_svec_adc_x2"
syn_project = "wrtd_ref_svec_adc_x2.xise"
syn_tool = "ise"
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto = "../../../dependencies"
files = [
"buildinfo_pkg.vhd",
# fetchto + "/fmc-tdc/hdl/syn/svec/svec-tdc0.ucf",
# fetchto + "/fmc-tdc/hdl/syn/svec/svec-tdc1.ucf",
"wrtd_ref_svec_adc_x2.ucf",
]
modules = {
"local" : [
"../../top/wrtd_ref_svec_adc_x2",
],
}
syn_pre_project_cmd = "make -C ../../../software/firmware"
# Do not fail during hdlmake fetch
try:
exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
except:
pass
syn_post_project_cmd = "$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
svec_base_ucf = ['wr', 'ddr4', 'ddr5', 'led', 'gpio']
ctrls = ["bank4_64b_32b", "bank5_64b_32b"]
# get project file from 1st command-line argument
set project_file [lindex $argv 0]
if {![file exists $project_file]} {
report ERROR "Missing file $project_file, exiting."
exit -1
}
xilinx::project open $project_file
# Some of these are not respected by ISE when passed through hdlmake,
# so we add them all ourselves after creating the project
#
# Not respected by ISE when passed through hdlmake:
# 1. Pack I/O Registers/Latches into IOBs
# 2. Register Duplication Map
xilinx::project set "Enable Multi-Threading" "2" -process "Map"
xilinx::project set "Enable Multi-Threading" "4" -process "Place & Route"
xilinx::project set "Pack I/O Registers into IOBs" "Yes"
xilinx::project set "Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs"
xilinx::project set "Register Balancing" "Yes"
xilinx::project set "Register Duplication Map" "On"
#xilinx::project set "Placer Extra Effort Map" "Normal"
#xilinx::project set "Extra Effort (Highest PAR level only)" "Normal"
xilinx::project save
xilinx::project close
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
#===============================================================================
# IO Constraints
#===============================================================================
#----------------------------------------
# FMC slots
#----------------------------------------
# FMC0
NET "adc_ext_trigger_n_i[0]" LOC = "A15";
NET "adc_ext_trigger_p_i[0]" LOC = "B15";
NET "adc_dco_n_i[0]" LOC = "A16";
NET "adc_dco_p_i[0]" LOC = "C16";
NET "adc_fr_n_i[0]" LOC = "G21";
NET "adc_fr_p_i[0]" LOC = "H21";
NET "adc_outa_n_i[0]" LOC = "E17";
NET "adc_outa_p_i[0]" LOC = "F17";
NET "adc_outb_n_i[0]" LOC = "G16";
NET "adc_outb_p_i[0]" LOC = "H16";
NET "adc_outa_n_i[1]" LOC = "E19";
NET "adc_outa_p_i[1]" LOC = "F19";
NET "adc_outb_n_i[1]" LOC = "F18";
NET "adc_outb_p_i[1]" LOC = "G18";
NET "adc_outa_n_i[2]" LOC = "K21";
NET "adc_outa_p_i[2]" LOC = "L21";
NET "adc_outb_n_i[2]" LOC = "L20";
NET "adc_outb_p_i[2]" LOC = "M20";
NET "adc_outa_n_i[3]" LOC = "F22";
NET "adc_outa_p_i[3]" LOC = "G22";
NET "adc_outb_n_i[3]" LOC = "L19";
NET "adc_outb_p_i[3]" LOC = "M19";
NET "adc_spi_din_i[0]" LOC = "F11";
NET "adc_spi_dout_o[0]" LOC = "K11";
NET "adc_spi_sck_o[0]" LOC = "L11";
NET "adc_spi_cs_adc_n_o[0]" LOC = "J13";
NET "adc_spi_cs_dac1_n_o[0]" LOC = "H11";
NET "adc_spi_cs_dac2_n_o[0]" LOC = "G11";
NET "adc_spi_cs_dac3_n_o[0]" LOC = "J12";
NET "adc_spi_cs_dac4_n_o[0]" LOC = "H12";
NET "adc_gpio_dac_clr_n_o[0]" LOC = "H13";
NET "adc_gpio_led_acq_o[0]" LOC = "K12";
NET "adc_gpio_led_trig_o[0]" LOC = "L12";
NET "adc_gpio_ssr_ch1_o[0]" LOC = "L14";
NET "adc_gpio_ssr_ch1_o[1]" LOC = "K14";
NET "adc_gpio_ssr_ch1_o[2]" LOC = "L13";
NET "adc_gpio_ssr_ch1_o[3]" LOC = "E11";
NET "adc_gpio_ssr_ch1_o[4]" LOC = "G10";
NET "adc_gpio_ssr_ch1_o[5]" LOC = "F10";
NET "adc_gpio_ssr_ch1_o[6]" LOC = "F9";
NET "adc_gpio_ssr_ch2_o[0]" LOC = "F15";
NET "adc_gpio_ssr_ch2_o[1]" LOC = "F14";
NET "adc_gpio_ssr_ch2_o[2]" LOC = "F13";
NET "adc_gpio_ssr_ch2_o[3]" LOC = "E13";
NET "adc_gpio_ssr_ch2_o[4]" LOC = "G12";
NET "adc_gpio_ssr_ch2_o[5]" LOC = "M13";
NET "adc_gpio_ssr_ch2_o[6]" LOC = "F12";
NET "adc_gpio_ssr_ch3_o[0]" LOC = "F23";
NET "adc_gpio_ssr_ch3_o[1]" LOC = "E23";
NET "adc_gpio_ssr_ch3_o[2]" LOC = "F21";
NET "adc_gpio_ssr_ch3_o[3]" LOC = "E21";
NET "adc_gpio_ssr_ch3_o[4]" LOC = "G20";
NET "adc_gpio_ssr_ch3_o[5]" LOC = "F20";
NET "adc_gpio_ssr_ch3_o[6]" LOC = "E15";
NET "adc_gpio_ssr_ch4_o[0]" LOC = "J22";
NET "adc_gpio_ssr_ch4_o[1]" LOC = "H22";
NET "adc_gpio_ssr_ch4_o[2]" LOC = "E25";
NET "adc_gpio_ssr_ch4_o[3]" LOC = "D25";
NET "adc_gpio_ssr_ch4_o[4]" LOC = "D24";
NET "adc_gpio_ssr_ch4_o[5]" LOC = "B25";
NET "adc_gpio_ssr_ch4_o[6]" LOC = "C24";
NET "adc_gpio_si570_oe_o[0]" LOC = "A25";
NET "adc_si570_scl_b[0]" LOC = "H14";
NET "adc_si570_sda_b[0]" LOC = "J14";
NET "adc_one_wire_b[0]" LOC = "E9";
# FMC1
NET "adc_ext_trigger_n_i[1]" LOC = "AD16";
NET "adc_ext_trigger_p_i[1]" LOC = "AC16";
NET "adc_dco_n_i[1]" LOC = "AK17";
NET "adc_dco_p_i[1]" LOC = "AJ17";
NET "adc_fr_n_i[1]" LOC = "AH8";
NET "adc_fr_p_i[1]" LOC = "AG8";
NET "adc_outa_n_i[4]" LOC = "AA15";
NET "adc_outa_p_i[4]" LOC = "Y15";
NET "adc_outb_n_i[4]" LOC = "AA17";
NET "adc_outb_p_i[4]" LOC = "Y17";
NET "adc_outa_n_i[5]" LOC = "AC14";
NET "adc_outa_p_i[5]" LOC = "AB14";
NET "adc_outb_n_i[5]" LOC = "AD15";
NET "adc_outb_p_i[5]" LOC = "AC15";
NET "adc_outa_n_i[6]" LOC = "AA14";
NET "adc_outa_p_i[6]" LOC = "Y14";
NET "adc_outb_n_i[6]" LOC = "Y13";
NET "adc_outb_p_i[6]" LOC = "W14";
NET "adc_outa_n_i[7]" LOC = "AE12";
NET "adc_outa_p_i[7]" LOC = "AD12";
NET "adc_outb_n_i[7]" LOC = "AF11";
NET "adc_outb_p_i[7]" LOC = "AE11";
NET "adc_spi_din_i[1]" LOC = "AB17";
NET "adc_spi_dout_o[1]" LOC = "AA21";
NET "adc_spi_sck_o[1]" LOC = "Y21";
NET "adc_spi_cs_adc_n_o[1]" LOC = "W20";
NET "adc_spi_cs_dac1_n_o[1]" LOC = "W19";
NET "adc_spi_cs_dac2_n_o[1]" LOC = "Y19";
NET "adc_spi_cs_dac3_n_o[1]" LOC = "AA19";
NET "adc_spi_cs_dac4_n_o[1]" LOC = "AB19";
NET "adc_gpio_dac_clr_n_o[1]" LOC = "Y20";
NET "adc_gpio_led_acq_o[1]" LOC = "AC22";
NET "adc_gpio_led_trig_o[1]" LOC = "AA22";
NET "adc_gpio_ssr_ch1_o[7]" LOC = "AC19";
NET "adc_gpio_ssr_ch1_o[8]" LOC = "AD19";
NET "adc_gpio_ssr_ch1_o[9]" LOC = "AC20";
NET "adc_gpio_ssr_ch1_o[10]" LOC = "AD17";
NET "adc_gpio_ssr_ch1_o[11]" LOC = "AB21";
NET "adc_gpio_ssr_ch1_o[12]" LOC = "AC21";
NET "adc_gpio_ssr_ch1_o[13]" LOC = "AC24";
NET "adc_gpio_ssr_ch2_o[7]" LOC = "AE19";
NET "adc_gpio_ssr_ch2_o[8]" LOC = "AF23";
NET "adc_gpio_ssr_ch2_o[9]" LOC = "AE24";
NET "adc_gpio_ssr_ch2_o[10]" LOC = "AF24";
NET "adc_gpio_ssr_ch2_o[11]" LOC = "AD22";
NET "adc_gpio_ssr_ch2_o[12]" LOC = "AB20";
NET "adc_gpio_ssr_ch2_o[13]" LOC = "AE22";
NET "adc_gpio_ssr_ch3_o[7]" LOC = "AB12";
NET "adc_gpio_ssr_ch3_o[8]" LOC = "AC12";
NET "adc_gpio_ssr_ch3_o[9]" LOC = "AE15";
NET "adc_gpio_ssr_ch3_o[10]" LOC = "AF15";
NET "adc_gpio_ssr_ch3_o[11]" LOC = "Y16";
NET "adc_gpio_ssr_ch3_o[12]" LOC = "AB16";
NET "adc_gpio_ssr_ch3_o[13]" LOC = "AF19";
NET "adc_gpio_ssr_ch4_o[7]" LOC = "AC11";
NET "adc_gpio_ssr_ch4_o[8]" LOC = "AD11";
NET "adc_gpio_ssr_ch4_o[9]" LOC = "AE13";
NET "adc_gpio_ssr_ch4_o[10]" LOC = "AF13";
NET "adc_gpio_ssr_ch4_o[11]" LOC = "AJ15";
NET "adc_gpio_ssr_ch4_o[12]" LOC = "AD10";
NET "adc_gpio_ssr_ch4_o[13]" LOC = "AK15";
NET "adc_gpio_si570_oe_o[1]" LOC = "AE10";
NET "adc_si570_scl_b[1]" LOC = "AF21";
NET "adc_si570_sda_b[1]" LOC = "AE21";
NET "adc_one_wire_b[1]" LOC = "AD24";
# IO standards
NET "adc_ext_trigger_?_i[*]" IOSTANDARD = "LVDS_25";
NET "adc_dco_?_i[*]" IOSTANDARD = "LVDS_25";
NET "adc_fr_?_i[*]" IOSTANDARD = "LVDS_25";
NET "adc_out?_?_i[*]" IOSTANDARD = "LVDS_25";
NET "adc_spi_din_i[*]" IOSTANDARD = "LVCMOS25";
NET "adc_spi_dout_o[*]" IOSTANDARD = "LVCMOS25";
NET "adc_spi_sck_o[*]" IOSTANDARD = "LVCMOS25";
NET "adc_spi_cs_adc_n_o[*]" IOSTANDARD = "LVCMOS25";
NET "adc_spi_cs_dac?_n_o[*]" IOSTANDARD = "LVCMOS25";
NET "adc_gpio_dac_clr_n_o[*]" IOSTANDARD = "LVCMOS25";
NET "adc_gpio_led_acq_o[*]" IOSTANDARD = "LVCMOS25";
NET "adc_gpio_led_trig_o[*]" IOSTANDARD = "LVCMOS25";
NET "adc_gpio_ssr_ch?_o[*]" IOSTANDARD = "LVCMOS25";
NET "adc_gpio_si570_oe_o[*]" IOSTANDARD = "LVCMOS25";
NET "adc_si570_scl_b[*]" IOSTANDARD = "LVCMOS25";
NET "adc_si570_sda_b[*]" IOSTANDARD = "LVCMOS25";
NET "adc_one_wire_b[*]" IOSTANDARD = "LVCMOS25";
#===============================================================================
# Timing constraints and exceptions
#===============================================================================
# Tightly constrain the location and max delay from the external trigger input
# to its synchroniser. This is needed to have consistent alignment between trigger
# and data across implementations. Note that due to RLOC constraints in the
# gc_sync_ffs, the synchroniser cannot be placed on the single FF of the IOB.
NET "gen_fmc_mezzanine[?].*/*/cmp_ext_trig_sync/gc_sync_ffs_in" MAXDELAY = 2.0 ns;
INST "gen_fmc_mezzanine[0].*/*/cmp_ext_trig_sync/sync0" RLOC_ORIGIN = X66Y189;
INST "gen_fmc_mezzanine[1].*/*/cmp_ext_trig_sync/sync0" RLOC_ORIGIN = X69Y2;
#----------------------------------------
# IOB exceptions
#----------------------------------------
INST "gen_fmc_mezzanine[*].*/cmp_fmc_spi/*/Wrapped_SPI/shift/s_out" IOB = FALSE;
INST "gen_fmc_mezzanine[*].*/cmp_fmc_spi/*/Wrapped_SPI/clgen/clk_out" IOB = FALSE;
INST "gen_fmc_mezzanine[*].*/cmp_fmc_i2c/U_Wrapped_I2C/*" IOB = FALSE;
INST "gen_fmc_mezzanine[*].*/cmp_fmc_onewire/*" IOB = FALSE;
#----------------------------------------
# Clocks
#----------------------------------------
NET "adc_dco_p_i[0]" TNM_NET = adc0_dco;
NET "adc_dco_n_i[0]" TNM_NET = adc0_dco;
TIMESPEC TS_adc0_dco = PERIOD "adc0_dco" 2.5 ns HIGH 50%;
NET "adc_dco_p_i[1]" TNM_NET = adc1_dco;
NET "adc_dco_n_i[1]" TNM_NET = adc1_dco;
TIMESPEC TS_adc1_dco = PERIOD "adc1_dco" 2.5 ns HIGH 50%;
#----------------------------------------
# Cross-clock domain sync
#----------------------------------------
NET "gen_fmc_mezzanine[0].*/cmp_fmc_adc_100Ms_core/fs_clk" TNM_NET = fs0_clk;
NET "gen_fmc_mezzanine[1].*/cmp_fmc_adc_100Ms_core/fs_clk" TNM_NET = fs1_clk;
TIMEGRP "adc0_sync_ffs" = "sync_ffs" EXCEPT "fs0_clk";
TIMEGRP "adc1_sync_ffs" = "sync_ffs" EXCEPT "fs1_clk";
#TIMESPEC TS_adc0_sync_ffs = FROM fs0_clk TO "adc0_sync_ffs" TIG;
#TIMESPEC TS_adc1_sync_ffs = FROM fs1_clk TO "adc1_sync_ffs" TIG;
TIMEGRP "adc0_sync_reg" = "sync_reg" EXCEPT "fs0_clk";
TIMEGRP "adc1_sync_reg" = "sync_reg" EXCEPT "fs1_clk";
TIMESPEC TS_adc0_sync_reg = FROM fs0_clk TO "adc0_sync_reg" 8ns DATAPATHONLY;
TIMESPEC TS_adc1_sync_reg = FROM fs1_clk TO "adc1_sync_reg" 8ns DATAPATHONLY;
# No sync words used in FMC-ADC
#TIMESPEC TS_adc0_sync_word = FROM sync_word TO fs0_clk 30ns DATAPATHONLY;
#TIMESPEC TS_adc1_sync_word = FROM sync_word TO fs1_clk 30ns DATAPATHONLY;
*
!.gitignore
!Manifest.py
!*.ucf
!syn_extra_steps.tcl
board = "svec"
target = "xilinx"
action = "synthesis"
syn_device = "xc6slx150t"
syn_grade = "-3"
syn_package = "fgg900"
syn_top = "wrtd_ref_svec_fd_x2"
syn_project = "wrtd_ref_svec_fd_x2.xise"
syn_tool = "ise"
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto = "../../../dependencies"
files = [
"wrtd_ref_svec_fd_x2.ucf",
"buildinfo_pkg.vhd",
fetchto + "/fmc-delay-1ns-8cha/hdl/syn/svec/svec-fd0.ucf",
fetchto + "/fmc-delay-1ns-8cha/hdl/syn/svec/svec-fd1.ucf",
]
modules = {
"local" : [
"../../top/wrtd_ref_svec_fd_x2",
],
}
syn_pre_project_cmd = "make -C ../../../software/firmware"
# Do not fail during hdlmake fetch
try:
exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
except:
pass
syn_post_project_cmd = "$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
svec_base_ucf = ['wr', 'led', 'gpio']
ctrls = ["bank4_64b_32b", "bank5_64b_32b"]
# get project file from 1st command-line argument
set project_file [lindex $argv 0]
if {![file exists $project_file]} {
report ERROR "Missing file $project_file, exiting."
exit -1
}
xilinx::project open $project_file
# Some of these are not respected by ISE when passed through hdlmake,
# so we add them all ourselves after creating the project
#
# Not respected by ISE when passed through hdlmake:
# 1. Pack I/O Registers/Latches into IOBs
# 2. Register Duplication Map
xilinx::project set "Enable Multi-Threading" "2" -process "Map"
xilinx::project set "Enable Multi-Threading" "4" -process "Place & Route"
xilinx::project set "Pack I/O Registers into IOBs" "Yes"
xilinx::project set "Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs"
xilinx::project set "Register Balancing" "Yes"
xilinx::project set "Register Duplication Map" "On"
#xilinx::project set "Placer Extra Effort Map" "Normal"
#xilinx::project set "Extra Effort (Highest PAR level only)" "Normal"
xilinx::project save
xilinx::project close
#===============================================================================
# Timing constraints and exceptions
#===============================================================================
NET "fp_gpio3_b" TNM_NET = fp_gpio3;
TIMESPEC TS_fp_gpio3 = PERIOD "fp_gpio3" 100 ns HIGH 50%;
NET "fmc0_fd_clk_ref_n_i" TNM_NET = fmc0_fd_clk_ref_n_i;
TIMESPEC TS_fmc0_fd_clk_ref_n_i = PERIOD "fmc0_fd_clk_ref_n_i" 8 ns HIGH 50%;
NET "fmc1_fd_clk_ref_n_i" TNM_NET = fmc1_fd_clk_ref_n_i;
TIMESPEC TS_fmc1_fd_clk_ref_n_i = PERIOD "fmc1_fd_clk_ref_n_i" 8 ns HIGH 50%;
#----------------------------------------
# Cross-clock domain sync
#----------------------------------------
# IMPORTANT: timing constraints are also coming from SVEC base UCF files
# Declaration of domains
NET "dcm0_clk_ref_0" TNM_NET = fd0_clk;
NET "dcm1_clk_ref_0" TNM_NET = fd1_clk;
# Exceptions for crossings via gc_sync_ffs
#TIMEGRP "fdl_sync_ffs" = "sync_ffs" EXCEPT "fdl_clk";
#TIMEGRP "tdc_sync_ffs" = "sync_ffs" EXCEPT "tdc_clk";
#TIMESPEC TS_fdl_sync_ffs = FROM fdl_clk TO "fdl_sync_ffs" TIG;
#TIMESPEC TS_tdc_sync_ffs = FROM tdc_clk TO "tdc_sync_ffs" TIG;
# Exceptions for crossings via gc_sync_register
#TIMEGRP "fdl_sync_reg" = "sync_reg" EXCEPT "fdl_clk";
#TIMEGRP "tdc_sync_reg" = "sync_reg" EXCEPT "tdc_clk";
#TIMESPEC TS_fdl_sync_reg = FROM fdl_clk TO "fdl_sync_reg" 8ns DATAPATHONLY;
#TIMESPEC TS_tdc_sync_reg = FROM tdc_clk TO "tdc_sync_reg" 8ns DATAPATHONLY;
*
!.gitignore
!Manifest.py
!*.ucf
!syn_extra_steps.tcl
board = "svec"
target = "xilinx"
action = "synthesis"
syn_device = "xc6slx150t"
syn_grade = "-3"
syn_package = "fgg900"
syn_top = "wrtd_ref_svec_tdc_fd"
syn_project = "wrtd_ref_svec_tdc_fd.xise"
syn_tool = "ise"
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto = "../../../dependencies"
files = [
"wrtd_ref_svec_tdc_fd.ucf",
"buildinfo_pkg.vhd",
]
modules = {
"local" : [
"../../top/wrtd_ref_svec_tdc_fd",
],
}
syn_pre_project_cmd = "make -C ../../../software/firmware"
# Do not fail during hdlmake fetch
try:
exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
except:
pass
syn_post_project_cmd = "$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
svec_base_ucf = ['wr', 'led', 'gpio']
ctrls = ["bank4_64b_32b", "bank5_64b_32b"]
# get project file from 1st command-line argument
set project_file [lindex $argv 0]
if {![file exists $project_file]} {
report ERROR "Missing file $project_file, exiting."
exit -1
}
xilinx::project open $project_file
# Some of these are not respected by ISE when passed through hdlmake,
# so we add them all ourselves after creating the project
#
# Not respected by ISE when passed through hdlmake:
# 1. Pack I/O Registers/Latches into IOBs
# 2. Register Duplication Map
xilinx::project set "Enable Multi-Threading" "2" -process "Map"
xilinx::project set "Enable Multi-Threading" "4" -process "Place & Route"
xilinx::project set "Pack I/O Registers into IOBs" "Yes"
xilinx::project set "Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs"
xilinx::project set "Register Balancing" "Yes"
xilinx::project set "Register Duplication Map" "On"
#xilinx::project set "Placer Extra Effort Map" "Normal"
#xilinx::project set "Extra Effort (Highest PAR level only)" "Normal"
xilinx::project save
xilinx::project close
This diff is collapsed.
*
!.gitignore
!Manifest.py
!*.ucf
!syn_extra_steps.tcl
board = "svec"
target = "xilinx"
action = "synthesis"
syn_device = "xc6slx150t"
syn_grade = "-3"
syn_package = "fgg900"
syn_top = "wrtd_ref_svec_tdc_x2"
syn_project = "wrtd_ref_svec_tdc_x2.xise"
syn_tool = "ise"
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto = "../../../dependencies"
files = [
"buildinfo_pkg.vhd",
fetchto + "/fmc-tdc/hdl/syn/svec/svec-tdc0.ucf",
fetchto + "/fmc-tdc/hdl/syn/svec/svec-tdc1.ucf",
"wrtd_ref_svec_tdc_x2.ucf",
]
modules = {
"local" : [
"../../top/wrtd_ref_svec_tdc_x2",
],
}
syn_pre_project_cmd = "make -C ../../../software/firmware"
# Do not fail during hdlmake fetch
try:
exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
except:
pass
syn_post_project_cmd = "$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
svec_base_ucf = ['wr', 'led', 'gpio']
ctrls = ["bank4_64b_32b", "bank5_64b_32b"]
# get project file from 1st command-line argument
set project_file [lindex $argv 0]
if {![file exists $project_file]} {
report ERROR "Missing file $project_file, exiting."
exit -1
}
xilinx::project open $project_file
# Some of these are not respected by ISE when passed through hdlmake,
# so we add them all ourselves after creating the project
#
# Not respected by ISE when passed through hdlmake:
# 1. Pack I/O Registers/Latches into IOBs
# 2. Register Duplication Map
xilinx::project set "Enable Multi-Threading" "2" -process "Map"
xilinx::project set "Enable Multi-Threading" "4" -process "Place & Route"
xilinx::project set "Pack I/O Registers into IOBs" "Yes"
xilinx::project set "Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs"
xilinx::project set "Register Balancing" "Yes"
xilinx::project set "Register Duplication Map" "On"
#xilinx::project set "Placer Extra Effort Map" "Normal"
#xilinx::project set "Extra Effort (Highest PAR level only)" "Normal"
xilinx::project save
xilinx::project close
#===============================================================================
# Timing constraints and exceptions
#===============================================================================
NET "fp_gpio3_b" TNM_NET = fp_gpio3;
TIMESPEC TS_fp_gpio3 = PERIOD "fp_gpio3" 100 ns HIGH 50%;
NET "fmc0_tdc_clk_125m_n_i" TNM_NET = fmc0_tdc_clk_125m_n_i;
TIMESPEC TS_fmc0_tdc_clk_125m_n_i = PERIOD "fmc0_tdc_clk_125m_n_i" 8 ns HIGH 50%;
NET "fmc1_tdc_clk_125m_n_i" TNM_NET = fmc1_tdc_clk_125m_n_i;
TIMESPEC TS_fmc1_tdc_clk_125m_n_i = PERIOD "fmc1_tdc_clk_125m_n_i" 8 ns HIGH 50%;
#----------------------------------------
# Cross-clock domain sync
#----------------------------------------
# IMPORTANT: timing constraints are also coming from SVEC base UCF files
# Declaration of domains
NET "tdc0_clk_125m" TNM_NET = tdc0_clk;
NET "tdc1_clk_125m" TNM_NET = tdc1_clk;
# Exceptions for crossings via gc_sync_ffs
TIMEGRP "tdc0_sync_ffs" = "sync_ffs" EXCEPT "tdc0_clk";
#TIMESPEC TS_tdc_sync_ffs = FROM tdc_clk TO "tdc_sync_ffs" TIG;
# Exceptions for crossings via gc_sync_register
#TIMEGRP "tdc_sync_reg" = "sync_reg" EXCEPT "tdc_clk";
#TIMESPEC TS_tdc_sync_reg = FROM tdc_clk TO "tdc_sync_reg" 8ns DATAPATHONLY;
# This Makefile can be called by the Continuous Integration (CI) tool to execute all
# testbenches added for CI
#
# Author: Adam Wujek, CERN 2017
TB_DIRS = wrtd_ref_svec_tdc_fd wrtd_ref_spec150t_adc
test_results_xml=test_results.xml
.PHONY: $(TB_DIRS)
all: $(TB_DIRS) summary summary_total summary_xml
FW_BRAM = ../../software/firmware/fd/wrtd-rt-fd.bram \
../../software/firmware/tdc/wrtd-rt-tdc.bram \
../../software/firmware/adc/wrtd-rt-adc.bram
wrtd-system: $(FW_BRAM)
$(FW_BRAM):
$(MAKE) -C $(@D) defconfig
$(MAKE) -C $(@D) $(notdir $@) EXTRA2_CFLAGS=-DSIMULATION
$(TB_DIRS):
@echo $@
@echo "Run HDL-MAKE"
cd "$@"; \
$(HDLMAKE_PATH)/hdl-make 2>&1
@echo "Run make"
$(MAKE) -C $@ $(TARGET) -j 1
@echo "Run vsim"
cd "$@" ;\
vsim -c -do "run_ci.do" -l transcript."$@".txt;\
echo "vsim returned $$?"
summary: $(TB_DIRS)
@echo "-------------------------------------------------------------------"
@echo "Summary:"
@for d in $(TB_DIRS); do \
if [ -f $$d/transcript."$$d".txt ]; then \
echo "Warnings for $$d:"; \
cat $$d/transcript."$$d".txt | grep Warning:; \
if [ $$? -eq 1 ]; then echo "None"; fi ;\
echo "Errors for $$d:"; \
cat $$d/transcript."$$d".txt | grep Error:; \
if [ $$? -eq 1 ]; then echo "None"; fi ;\
echo "Fatals for $$d:"; \
cat $$d/transcript."$$d".txt | grep Fatal:; \
if [ $$? -eq 1 ]; then echo "None"; fi ;\
else \
echo "No transcript file for $$d"; \
fi \
done
# Run tasks all before summary_total, because if there is a failure summary_total breaks the make execution
summary_total: summary summary_xml
@echo "-------------------------------------------------------------------"
@echo ""
@echo "Summary total:"
@echo "+---------------------------------------------------+----------+----------+----------+"
@echo "| Test bench | Warnings | Errors | Fatals |"
@echo "+---------------------------------------------------+----------+----------+----------+"
@is_error=0;\
for d in $(TB_DIRS); do \
if [ -f $$d/transcript."$$d".txt ]; then \
printf "| %-50s" $$d; \
printf "| %8d " `cat $$d/transcript."$$d".txt | grep Warning: | wc -l`; \
error_n=`cat $$d/transcript."$$d".txt | grep Error: | wc -l`; \
printf "| %8d " $$error_n;\
if [ $$error_n -gt 0 ]; then is_error=1; fi ;\
fatal_n=`cat $$d/transcript."$$d".txt | grep Fatal: | wc -l`; \
printf "| %8d |\n" $$fatal_n;\
if [ $$fatal_n -gt 0 ]; then is_error=1; fi ;\
else \
printf "| %-30s" $$d; \
echo "| No transcript file! |"; is_error=1; \
fi \
done ;\
echo "+---------------------------------------------------+----------+----------+----------+";\
if [ $$is_error -gt 0 ]; then exit 1; fi ;
summary_xml: summary
@echo '<?xml version="1.0" encoding="UTF-8"?>' > $(test_results_xml)
@echo '<testsuites tests="0" failures="0" disabled="0" errors="0" time="0" name="AllTests">' >> $(test_results_xml)
@for d in $(TB_DIRS); do \
is_test_error=0;\
error_n=0;\
fatal_n=0;\
echo -n " <testsuite name=\""$$d"\" tests=\"1\" failures=\"" >> $(test_results_xml) ;\
if [ -f $$d/transcript."$$d".txt ]; then \
error_n=`cat $$d/transcript."$$d".txt | grep Error: | wc -l`; \
fatal_n=`cat $$d/transcript."$$d".txt | grep Fatal: | wc -l`; \
if [ $$error_n -gt 0 ] || [ $$fatal_n -gt 0 ]; then is_test_error=1; fi ;\
echo -n $$is_test_error >> $(test_results_xml);\
else \
is_test_error=2; \
echo -n "1" >> $(test_results_xml); \
fi; \
echo "\" disabled=\"0\" errors=\"0\" time=\"0\">" >> $(test_results_xml) ;\
echo " <testcase name=\""$$d"\" status=\"run\" time=\"0\" classname=\""Testbench"\">" >> $(test_results_xml) ;\
if [ $$is_test_error -eq 1 ]; then \
if [ $$error_n -gt 0 ]; then \
echo " <failure message=\"Errors\" type=\"\"><![CDATA[" >> $(test_results_xml) ;\
cat $$d/transcript."$$d".txt | grep Error: >> $(test_results_xml);\
echo " ]]></failure>" >> $(test_results_xml) ;\
fi;\
if [ $$fatal_n -gt 0 ]; then \
echo " <failure message=\"Fatals\" type=\"\"><![CDATA[" >> $(test_results_xml) ;\
cat $$d/transcript."$$d".txt | grep Fatal: >> $(test_results_xml);\
echo " ]]></failure>" >> $(test_results_xml) ;\
fi;\
fi ;\
if [ $$is_test_error -eq 2 ]; then \
echo " <failure message=\"Output file not found\" type=\"\">" >> $(test_results_xml) ;\
echo "<![CDATA[Output file not found. Testbench didnt run.]]>" >> $(test_results_xml) ;\
echo " </failure>" >> $(test_results_xml) ;\
fi ;\
echo " </testcase>" >> $(test_results_xml) ;\
echo " </testsuite>" >> $(test_results_xml) ;\
done ;\
echo "</testsuites>" >> $(test_results_xml)
clean:
@for d in $(TB_DIRS); do \
if [ -f $$d/Makefile ]; then \
$(MAKE) -C $$d $@; \
rm -f $$d/Makefile; \
fi \
done
work/
NullFile
Makefile
modelsim.ini
transcript*
*.wlf
buildinfo_pkg.vhd
board = "spec"
sim_tool = "modelsim"
sim_top = "main"
action = "simulation"
target = "xilinx"
syn_device = "xc6slx150t"
vcom_opt = "-93 -mixedsvvh"
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto = "../../../dependencies"
sim_pre_cmd = "EXTRA2_CFLAGS='-DSIMULATION' make -C ../../../software/firmware"
include_dirs = [
"../include",
fetchto + "/gn4124-core/hdl/sim/gn4124_bfm",
fetchto + "/general-cores/sim",
fetchto + "/mock-turtle/hdl/testbench/include",
fetchto + "/fmc-adc-100m14b4cha/hdl/testbench/include",
]
files = [
"main.sv",
"dut_env.sv",
"buildinfo_pkg.vhd",
]
modules = {
"local" : [
"../../top/wrtd_ref_spec150t_adc",
],
}
ctrls = ["bank3_64b_32b"]
# Do not fail during hdlmake fetch
try:
exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
except:
pass
Introduction
============
This is a testbench for the SPEC150T-based FMC ADC WRTD reference design.
Dependencies
============
To build this, you will need [hdl-make][1], using commit `968fa87` (or newer), as well as GNU Make.
To run it, you will need Modelsim/Questa. It has been tested with Questa 10.5c on Linux.
Build/Run Instrunctions
=======================
1. If not already done, pull all dependencies using `git submodule update --init` from within the
WRTD repository.
2. Run `hdlmake` from this directory.
3. Run `make` on the hdlmake-generated Makefile.
4. Run `vsim -c -do run.do`.
[1]: https://www.ohwr.org/projects/hdl-make/wiki
This diff is collapsed.
//------------------------------------------------------------------------------
// CERN BE-CO-HT
// White Rabbit Trigger Distribution (WRTD)
// https://ohwr.org/projects/wrtd
//------------------------------------------------------------------------------
//
// unit name: main
//
// description: Testbench for the SPEC150T-based FMC ADC WRTD reference design.
//
//------------------------------------------------------------------------------
// Copyright CERN 2019
//------------------------------------------------------------------------------
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 2.0 (the "License"); you may not use this file except
// in compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-2.0.
// Unless required by applicable law or agreed to in writing, software,
// hardware and materials distributed under this License is distributed on an
// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
// or implied. See the License for the specific language governing permissions
// and limitations under the License.
//------------------------------------------------------------------------------
`timescale 1ns/1ps
`include "gn4124_bfm.svh"
`include "wrtd_driver.svh"
`include "fmc_adc_mezzanine_mmap.v"
`include "fmc_adc_100Ms_csr.v"
`include "fmc_adc_100Ms_channel_regs.v"
`include "fmc_adc_eic_regs.v"
`define DMA_BASE 'h00c0
`define VIC_BASE 'h0100
`define ADC_OFFSET 'h4000
`define ADC_CSR_BASE `ADC_OFFSET + `ADDR_FMC_ADC_MEZZANINE_MMAP_FMC_ADC_100M_CSR
`define ADC_EIC_BASE `ADC_OFFSET + `ADDR_FMC_ADC_MEZZANINE_MMAP_FMC_ADC_EIC
`define ADC_CH1_BASE `ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_FMC_ADC_CH1
`define ADC_CH2_BASE `ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_FMC_ADC_CH2
`define ADC_CH3_BASE `ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_FMC_ADC_CH3
`define ADC_CH4_BASE `ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_FMC_ADC_CH4
module main;
IGN4124PCIMaster hostA ();
IGN4124PCIMaster hostB ();
reg duta_ext_trig, dutb_ext_trig;
dut_env DUTA (hostA, a2b_txp, a2b_txn, a2b_rxp, a2b_rxn, duta_ext_trig);
dut_env DUTB (hostB, a2b_rxp, a2b_rxn, a2b_txp, a2b_txn, dutb_ext_trig);
IMockTurtleIRQ MtIrqMonitorA (`MT_ATTACH_IRQ(DUTA.DUT.cmp_mock_turtle));
IMockTurtleIRQ MtIrqMonitorB (`MT_ATTACH_IRQ(DUTB.DUT.cmp_mock_turtle));
CBusAccessor accA, accB;
WrtdDrv devA, devB;
const uint64_t MT_BASE = 'h0002_0000;
int sim_end = 0;
initial begin
uint64_t val, expected;
$timeformat (-6, 3, "us", 10);
duta_ext_trig <= 1'b0;
wait ((hostA.ready == 1'b1) && (hostB.ready == 1'b1));
fork
begin
accA = hostA.get_accessor();
accA.set_default_xfer_size(4);
devA = new (accA, MT_BASE, MtIrqMonitorA, "DUT:A");
devA.init();
devA.add_rule ( "rule0" );
devA.set_rule ( "rule0", "LC-I5", "NET0", 0 );
devA.enable_rule ( "rule0" );
// Configure the EIC for an interrupt on ACQ_END
accA.write(`ADC_EIC_BASE + 'h4, 'h2);
// Configure the VIC
accA.write(`VIC_BASE + 'h8, 'h7f);
accA.write(`VIC_BASE + 'h0, 'h1);
// Config DUTA to trigger on external trigger and get 64 samples
accA.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_PRE_SAMPLES, 'h0000);
accA.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_POST_SAMPLES, 'h0040);
accA.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_SHOTS, 'h0001);
accA.write(`ADC_CH1_BASE + `ADDR_FMC_ADC_100MS_CHANNEL_REGS_CALIB, 'h8000);
accA.write(`ADC_CH2_BASE + `ADDR_FMC_ADC_100MS_CHANNEL_REGS_CALIB, 'h8000);
accA.write(`ADC_CH3_BASE + `ADDR_FMC_ADC_100MS_CHANNEL_REGS_CALIB, 'h8000);
accA.write(`ADC_CH4_BASE + `ADDR_FMC_ADC_100MS_CHANNEL_REGS_CALIB, 'h8000);
accA.write(`ADC_CH1_BASE + `ADDR_FMC_ADC_100MS_CHANNEL_REGS_SAT, 'h7fff);
accA.write(`ADC_CH2_BASE + `ADDR_FMC_ADC_100MS_CHANNEL_REGS_SAT, 'h7fff);
accA.write(`ADC_CH3_BASE + `ADDR_FMC_ADC_100MS_CHANNEL_REGS_SAT, 'h7fff);
accA.write(`ADC_CH4_BASE + `ADDR_FMC_ADC_100MS_CHANNEL_REGS_SAT, 'h7fff);
val = (1'b1 << `FMC_ADC_100MS_CSR_TRIG_EN_EXT_OFFSET);
accA.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_TRIG_EN, val);
expected = 'h39;
accA.read(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_STA, val);
if (val != expected)
$fatal (1, "ADC status error (got 0x%8x, expected 0x%8x).", val, expected);
$display ("[DUT:A] <%t> ADC configured and armed", $realtime);
end
begin
accB = hostB.get_accessor();
accB.set_default_xfer_size(4);
devB = new (accB, MT_BASE, MtIrqMonitorB, "DUT:B");
devB.init();
devB.add_rule ( "rule0" );
devB.set_rule ( "rule0", "NET0", "LC-O1", 50000 );
devB.enable_rule ( "rule0" );
// Configure the EIC for an interrupt on ACQ_END
accB.write(`ADC_EIC_BASE + 'h4, 'h2);
// Configure the VIC
accB.write(`VIC_BASE + 'h8, 'h7f);
accB.write(`VIC_BASE + 'h0, 'h1);
// Config DUTB to trigger on WRTD and get 64 samples
accB.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_PRE_SAMPLES, 'h0000);
accB.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_POST_SAMPLES, 'h0040);
accB.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_SHOTS, 'h0001);
accB.write(`ADC_CH1_BASE + `ADDR_FMC_ADC_100MS_CHANNEL_REGS_CALIB, 'h8000);
accB.write(`ADC_CH2_BASE + `ADDR_FMC_ADC_100MS_CHANNEL_REGS_CALIB, 'h8000);
accB.write(`ADC_CH3_BASE + `ADDR_FMC_ADC_100MS_CHANNEL_REGS_CALIB, 'h8000);
accB.write(`ADC_CH4_BASE + `ADDR_FMC_ADC_100MS_CHANNEL_REGS_CALIB, 'h8000);
accB.write(`ADC_CH1_BASE + `ADDR_FMC_ADC_100MS_CHANNEL_REGS_SAT, 'h7fff);
accB.write(`ADC_CH2_BASE + `ADDR_FMC_ADC_100MS_CHANNEL_REGS_SAT, 'h7fff);
accB.write(`ADC_CH3_BASE + `ADDR_FMC_ADC_100MS_CHANNEL_REGS_SAT, 'h7fff);
accB.write(`ADC_CH4_BASE + `ADDR_FMC_ADC_100MS_CHANNEL_REGS_SAT, 'h7fff);
expected = 'h39;
accB.read(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_STA, val);
if (val != expected)
$fatal (1, "ADC status error (got 0x%8x, expected 0x%8x).", val, expected);
$display ("[DUT:B] <%t> ADC configured and armed", $realtime);
end
join
#50us;
$display("[DUT:B] <%t> START ACQ 1", $realtime);
accB.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CTL, 'h00000001); // FSM start
$display("[DUT:A] <%t> START ACQ 1", $realtime);
accA.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CTL, 'h00000001); // FSM start
#5us;
duta_ext_trig <= 1'b1;
#10ns;
duta_ext_trig <= 1'b0;
fork
begin
wait (DUTA.DUT.cmp0_fmc_adc_mezzanine.acq_end_irq_o == 1);
$display("[DUT:A] <%t> END ACQ 1", $realtime);
accA.write(`ADC_EIC_BASE + 'hc, 'h2);
accA.write(`VIC_BASE + 'h1c, 'h0);
accA.read(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_TRIG_POS, val);
$display("[DUT:A] <%t> TRIG POSITION %.8x", $realtime, val);
// DMA transfer
accA.write(`DMA_BASE + 'h08, val); // dma start addr
accA.write(`DMA_BASE + 'h0C, 'h00001000); // host addr
accA.write(`DMA_BASE + 'h10, 'h00000000);
accA.write(`DMA_BASE + 'h14, 'h00000100); // len << 2
accA.write(`DMA_BASE + 'h18, 'h00000000); // next
accA.write(`DMA_BASE + 'h1C, 'h00000000);
accA.write(`DMA_BASE + 'h20, 'h00000000); // attrib: pcie -> host
accA.write(`DMA_BASE + 'h00, 'h00000001); // xfer start
wait (DUTA.DUT.inst_spec_base.irqs[2] == 1);
$display("[DUT:A] <%t> END DMA 1", $realtime);
accA.write(`DMA_BASE + 'h04, 'h04); // clear DMA IRQ
accA.write(`VIC_BASE + 'h1c, 'h0);
end
begin
wait (DUTB.DUT.cmp0_fmc_adc_mezzanine.acq_end_irq_o == 1);
$display("[DUT:B] <%t> END ACQ 1", $realtime);
accB.write(`ADC_EIC_BASE + 'hc, 'h2);
accB.write(`VIC_BASE + 'h1c, 'h0);
accB.read(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_TRIG_POS, val);
$display("[DUT:B] <%t> TRIG POSITION %.8x", $realtime, val);
// DMA transfer
accB.write(`DMA_BASE + 'h08, val); // dma start addr
accB.write(`DMA_BASE + 'h0C, 'h00001000); // host addr
accB.write(`DMA_BASE + 'h10, 'h00000000);
accB.write(`DMA_BASE + 'h14, 'h00000100); // len << 2
accB.write(`DMA_BASE + 'h18, 'h00000000); // next
accB.write(`DMA_BASE + 'h1C, 'h00000000);
accB.write(`DMA_BASE + 'h20, 'h00000000); // attrib: pcie -> host
accB.write(`DMA_BASE + 'h00, 'h00000001); // xfer start
wait (DUTB.DUT.inst_spec_base.irqs[2] == 1);
$display("[DUT:B] <%t> END DMA 1", $realtime);
accB.write(`DMA_BASE + 'h04, 'h04); // clear DMA IRQ
accB.write(`VIC_BASE + 'h1c, 'h0);
end
join
sim_end = 1;
end
initial begin
$display();
$display("Start of simulation");
$display("-------------------");
$display();
wait (sim_end == 1);
$display();
$display("Simulation PASSED");
$finish;
end
endmodule // main
vsim -quiet -t 10fs -L unisim work.main -suppress 1270,8617,8683,8684
set StdArithNoWarnings 1
set NumericStdNoWarnings 1
radix -hexadecimal
run -all
work/
Makefile
modelsim.ini
transcript*
*.wlf
buildinfo_pkg.vhd
board = "svec"
sim_tool = "modelsim"
sim_top = "main"
action = "simulation"
target = "xilinx"
syn_device = "xc6slx150t"
vcom_opt = "-93 -mixedsvvh"
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto = "../../../dependencies"
sim_pre_cmd = "EXTRA2_CFLAGS='-DSIMULATION' make -C ../../../software/firmware"
include_dirs = [
"../include",
fetchto + "/general-cores/sim/",
fetchto + "/mock-turtle/hdl/testbench/include/",
fetchto + "/vme64x-core/hdl/sim/vme64x_bfm/",
]
files = [
"main.sv",
"dut_env.sv",
"buildinfo_pkg.vhd",
]
modules = {
"local" : [
"../../top/wrtd_ref_svec_tdc_fd",
],
}
ctrls = ["bank4_64b_32b", "bank5_64b_32b"]
# Do not fail during hdlmake fetch
try:
exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
except:
pass
This diff is collapsed.
//------------------------------------------------------------------------------
// CERN BE-CO-HT
// White Rabbit Trigger Distribution (WRTD)
// https://ohwr.org/projects/wrtd
//------------------------------------------------------------------------------
//
// unit name: main
//
// description: Testbench for the SVEC-based FMC TDC+FD WRTD reference design.
//
//------------------------------------------------------------------------------
// Copyright CERN 2018-2019
//------------------------------------------------------------------------------
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 2.0 (the "License"); you may not use this file except
// in compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-2.0.
// Unless required by applicable law or agreed to in writing, software,
// hardware and materials distributed under this License is distributed on an
// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
// or implied. See the License for the specific language governing permissions
// and limitations under the License.
//------------------------------------------------------------------------------
`timescale 1ns/1ps
`include "vme64x_bfm.svh"
`include "wrtd_driver.svh"
`define VME_OFFSET 'h8000_0000
`define TDC_DIRECT_BASE `VME_OFFSET + 'h0001_8000
`define MT_BASE `VME_OFFSET + 'h0002_0000
module main;
wire clk_sys, rst_sys_n;
wire sfp_txp, sfp_txn, sfp_rxp, sfp_rxn;
IVME64X VME(rst_sys_n);
dut_env DUT (VME, clk_sys, rst_sys_n, sfp_txp, sfp_txn, sfp_rxp, sfp_rxn);
IMockTurtleIRQ MtIrqMonitor (`MT_ATTACH_IRQ(DUT.DUT.cmp_mock_turtle));
assign sfp_rxp = sfp_txp;
assign sfp_rxn = sfp_txn;
WrtdDrv dev;
initial begin
CBusAccessor_VME64x acc;
acc = new(VME.tb);
$timeformat (-6, 3, "us", 10);
#5us;
/* map func0 to 0x80000000, A32 */
acc.write('h7ff63, 'h80, A32|CR_CSR|D08Byte3);
acc.write('h7ff67, 0, CR_CSR|A32|D08Byte3);
acc.write('h7ff6b, 0, CR_CSR|A32|D08Byte3);
acc.write('h7ff6f, 36, CR_CSR|A32|D08Byte3);
acc.write('h7ff33, 1, CR_CSR|A32|D08Byte3);
acc.write('h7fffb, 'h10, CR_CSR|A32|D08Byte3); /* enable module (BIT_SET = 0x10) */
acc.set_default_modifiers(A32 | D32 | SINGLE);
/* Hack around CBusAccessor to make it work like CBusAccessor_VME64x. This is needed
because WrtdDev expects a CBusAccesor and will not respect the m_default_modifiers value
of CBusAccessor_VME64x when performing reads/writes. */
acc.set_default_xfer_size(A32 | D32 | SINGLE);
#5us;
dev = new (acc, `MT_BASE, MtIrqMonitor, "DUT");
dev.init();
dev.add_rule ( "rule0" );
dev.set_rule ( "rule0", "NET0", "LC-O1", 400000 );
dev.enable_rule ( "rule0" );
dev.add_rule ( "rule1" );
dev.set_rule ( "rule1", "NET1", "LC-O2", 400000 );
dev.enable_rule ( "rule1" );
dev.add_rule ( "rule2" );
dev.set_rule ( "rule2", "NET2", "LC-O3", 400000 );
dev.enable_rule ( "rule2" );
dev.add_rule ( "rule3" );
dev.set_rule ( "rule3", "LC-I1", "NET0", 0 );
dev.enable_rule ( "rule3" );
dev.add_rule ( "rule4" );
dev.set_rule ( "rule4", "LC-I2", "NET1", 0 );
dev.enable_rule ( "rule4" );
dev.add_rule ( "rule5" );
dev.set_rule ( "rule5", "LC-I3", "NET2", 0 );
dev.enable_rule ( "rule5" );
#5us;
// Force start_fpga from TDC to make sure that the FSM has been started
force DUT.DUT.U_TDC_Core.cmp_tdc_mezz.cmp_tdc_core.start_from_fpga = 'b1;
#100ns;
release DUT.DUT.U_TDC_Core.cmp_tdc_mezz.cmp_tdc_core.start_from_fpga;
dev.mdisplay("Configuration complete, ready to accept pulses...");
end
endmodule // main
vsim -quiet -t 10fs -L unisim work.main -suppress 1270,8617,8683,8684,8822
set StdArithNoWarnings 1
set NumericStdNoWarnings 1
radix -hexadecimal
log -r /*
run -all
# Modelsim run script for continuous integration
# execute: vsim -c -do "run_ci.do"
vsim -quiet -t 10fs -L unisim work.main -suppress 1270,8617,8683,8684,8822
set StdArithNoWarnings 1
set NumericStdNoWarnings 1
run -all
exit
files = [
"wrtd_ref_spec150t_adc.vhd",
]
fetchto = "../../../dependencies"
modules = {
"git" : [
"https://ohwr.org/project/general-cores.git",
"https://ohwr.org/project/wr-cores.git",
"https://ohwr.org/project/urv-core.git",
"https://ohwr.org/project/mock-turtle.git",
"https://ohwr.org/project/ddr3-sp6-core.git",
"https://ohwr.org/project/gn4124-core.git",
"https://ohwr.org/project/spec.git",
"https://ohwr.org/project/fmc-adc-100m14b4cha.git",
],
}
files = [
"wrtd_ref_svec_adc_x2.vhd",
"wrtd_adc_x2_host_map.vhd",
"wrtd_adc_x2_fmc_map.vhd",
]
fetchto = "../../../dependencies"
modules = {
"git" : [
"https://ohwr.org/project/svec.git",
"https://ohwr.org/project/general-cores.git",
"https://ohwr.org/project/wr-cores.git",
"https://ohwr.org/project/vme64x-core.git",
"https://ohwr.org/project/urv-core.git",
"https://ohwr.org/project/mock-turtle.git",
"https://ohwr.org/project/fmc-adc-100m14b4cha.git",
"https://ohwr.org/project/ddr3-sp6-core.git",
],
}
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC-BY-SA-4.0 OR CERN-OHL-W-2.0+ OR GPL-2.0-or-later
memory-map:
name: wrtd_adc_x2_fmc_map
bus: wb-32-be
description: WRTD ADC x2 dedicated peripheral map
size: 0x4000
x-hdl:
busgroup: True
pipeline: wr,rd
children:
- submap:
name: adc0_trigin
address: 0x0000
size: 0x1000
description: FMC ADC0 trigin
interface: wb-32-be
x-hdl:
busgroup: True
- submap:
name: adc0_trigout
address: 0x1000
size: 0x1000
description: FMC ADC0 trigout
interface: wb-32-be
x-hdl:
busgroup: True
- submap:
name: adc1_trigin
address: 0x2000
size: 0x1000
description: FMC ADC1 trigin
interface: wb-32-be
x-hdl:
busgroup: True
- submap:
name: adc1_trigout
address: 0x3000
size: 0x1000
description: FMC ADC1 trigout
interface: wb-32-be
x-hdl:
busgroup: True
This diff is collapsed.
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC-BY-SA-4.0 OR CERN-OHL-W-2.0+ OR GPL-2.0-or-later
memory-map:
name: wrtd_adc_x2_host_map
bus: wb-32-be
description: WRTD FMC-ADC-100M memory map
size: 0x40000
x-hdl:
busgroup: True
pipeline: wr,rd
children:
- submap:
name: metadata
address: 0x4000
size: 0x40
interface: wb-32-be
x-hdl:
busgroup: True
description: a ROM containing the application metadata
- submap:
name: adc0
address: 0x6000
size: 0x2000
description: FMC ADC Mezzanine slot 1
interface: wb-32-be
x-hdl:
busgroup: True
- submap:
name: adc1
address: 0x8000
size: 0x2000
description: FMC ADC Mezzanine slot 2
interface: wb-32-be
x-hdl:
busgroup: True
- submap:
name: mt
address: 0x20000
size: 0x20000
description: Mock-turtle
interface: wb-32-be
x-hdl:
busgroup: True
-- Do not edit. Generated on Thu Feb 25 09:14:33 2021 by tgingold
-- With Cheby 1.4.dev0 and these options:
-- --gen-hdl=wrtd_adc_x2_host_map.vhd -i wrtd_adc_x2_host_map.cheby
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
entity wrtd_adc_x2_host_map is
port (
rst_n_i : in std_logic;
clk_i : in std_logic;
wb_i : in t_wishbone_slave_in;
wb_o : out t_wishbone_slave_out;
-- a ROM containing the application metadata
metadata_i : in t_wishbone_master_in;
metadata_o : out t_wishbone_master_out;
-- FMC ADC Mezzanine slot 1
adc0_i : in t_wishbone_master_in;
adc0_o : out t_wishbone_master_out;
-- FMC ADC Mezzanine slot 2
adc1_i : in t_wishbone_master_in;
adc1_o : out t_wishbone_master_out;
-- Mock-turtle
mt_i : in t_wishbone_master_in;
mt_o : out t_wishbone_master_out
);
end wrtd_adc_x2_host_map;
architecture syn of wrtd_adc_x2_host_map is
signal adr_int : std_logic_vector(17 downto 2);
signal rd_req_int : std_logic;
signal wr_req_int : std_logic;
signal rd_ack_int : std_logic;
signal wr_ack_int : std_logic;
signal wb_en : std_logic;
signal ack_int : std_logic;
signal wb_rip : std_logic;
signal wb_wip : std_logic;
signal metadata_re : std_logic;
signal metadata_we : std_logic;
signal metadata_wt : std_logic;
signal metadata_rt : std_logic;
signal metadata_tr : std_logic;
signal metadata_wack : std_logic;
signal metadata_rack : std_logic;
signal adc0_re : std_logic;
signal adc0_we : std_logic;
signal adc0_wt : std_logic;
signal adc0_rt : std_logic;
signal adc0_tr : std_logic;
signal adc0_wack : std_logic;
signal adc0_rack : std_logic;
signal adc1_re : std_logic;
signal adc1_we : std_logic;
signal adc1_wt : std_logic;
signal adc1_rt : std_logic;
signal adc1_tr : std_logic;
signal adc1_wack : std_logic;
signal adc1_rack : std_logic;
signal mt_re : std_logic;
signal mt_we : std_logic;
signal mt_wt : std_logic;
signal mt_rt : std_logic;
signal mt_tr : std_logic;
signal mt_wack : std_logic;
signal mt_rack : std_logic;
signal rd_req_d0 : std_logic;
signal rd_adr_d0 : std_logic_vector(17 downto 2);
signal rd_ack_d0 : std_logic;
signal rd_dat_d0 : std_logic_vector(31 downto 0);
signal wr_req_d0 : std_logic;
signal wr_dat_d0 : std_logic_vector(31 downto 0);
signal wr_sel_d0 : std_logic_vector(3 downto 0);
signal wr_ack_d0 : std_logic;
begin
-- WB decode signals
adr_int <= wb_i.adr(17 downto 2);
wb_en <= wb_i.cyc and wb_i.stb;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
wb_rip <= '0';
else
wb_rip <= (wb_rip or (wb_en and not wb_i.we)) and not rd_ack_int;
end if;
end if;
end process;
rd_req_int <= (wb_en and not wb_i.we) and not wb_rip;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
wb_wip <= '0';
else
wb_wip <= (wb_wip or (wb_en and wb_i.we)) and not wr_ack_int;
end if;
end if;
end process;
wr_req_int <= (wb_en and wb_i.we) and not wb_wip;
ack_int <= rd_ack_int or wr_ack_int;
wb_o.ack <= ack_int;
wb_o.stall <= not ack_int and wb_en;
wb_o.rty <= '0';
wb_o.err <= '0';
-- pipelining for rd-in+rd-out+wr-in+wr-out
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
rd_req_d0 <= '0';
rd_ack_int <= '0';
wr_req_d0 <= '0';
wr_ack_int <= '0';
else
rd_req_d0 <= rd_req_int;
rd_adr_d0 <= adr_int;
rd_ack_int <= rd_ack_d0;
wb_o.dat <= rd_dat_d0;
wr_req_d0 <= wr_req_int;
wr_dat_d0 <= wb_i.dat;
wr_sel_d0 <= wb_i.sel;
wr_ack_int <= wr_ack_d0;
end if;
end if;
end process;
-- Interface metadata
metadata_tr <= metadata_wt or metadata_rt;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
metadata_rt <= '0';
metadata_wt <= '0';
else
metadata_rt <= (metadata_rt or metadata_re) and not metadata_rack;
metadata_wt <= (metadata_wt or metadata_we) and not metadata_wack;
end if;
end if;
end process;
metadata_o.cyc <= metadata_tr;
metadata_o.stb <= metadata_tr;
metadata_wack <= metadata_i.ack and metadata_wt;
metadata_rack <= metadata_i.ack and metadata_rt;
metadata_o.adr <= ((25 downto 0 => '0') & rd_adr_d0(5 downto 2)) & (1 downto 0 => '0');
metadata_o.sel <= wr_sel_d0;
metadata_o.we <= metadata_wt;
metadata_o.dat <= wr_dat_d0;
-- Interface adc0
adc0_tr <= adc0_wt or adc0_rt;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
adc0_rt <= '0';
adc0_wt <= '0';
else
adc0_rt <= (adc0_rt or adc0_re) and not adc0_rack;
adc0_wt <= (adc0_wt or adc0_we) and not adc0_wack;
end if;
end if;
end process;
adc0_o.cyc <= adc0_tr;
adc0_o.stb <= adc0_tr;
adc0_wack <= adc0_i.ack and adc0_wt;
adc0_rack <= adc0_i.ack and adc0_rt;
adc0_o.adr <= ((18 downto 0 => '0') & rd_adr_d0(12 downto 2)) & (1 downto 0 => '0');
adc0_o.sel <= wr_sel_d0;
adc0_o.we <= adc0_wt;
adc0_o.dat <= wr_dat_d0;
-- Interface adc1
adc1_tr <= adc1_wt or adc1_rt;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
adc1_rt <= '0';
adc1_wt <= '0';
else
adc1_rt <= (adc1_rt or adc1_re) and not adc1_rack;
adc1_wt <= (adc1_wt or adc1_we) and not adc1_wack;
end if;
end if;
end process;
adc1_o.cyc <= adc1_tr;
adc1_o.stb <= adc1_tr;
adc1_wack <= adc1_i.ack and adc1_wt;
adc1_rack <= adc1_i.ack and adc1_rt;
adc1_o.adr <= ((18 downto 0 => '0') & rd_adr_d0(12 downto 2)) & (1 downto 0 => '0');
adc1_o.sel <= wr_sel_d0;
adc1_o.we <= adc1_wt;
adc1_o.dat <= wr_dat_d0;
-- Interface mt
mt_tr <= mt_wt or mt_rt;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
mt_rt <= '0';
mt_wt <= '0';
else
mt_rt <= (mt_rt or mt_re) and not mt_rack;
mt_wt <= (mt_wt or mt_we) and not mt_wack;
end if;
end if;
end process;
mt_o.cyc <= mt_tr;
mt_o.stb <= mt_tr;
mt_wack <= mt_i.ack and mt_wt;
mt_rack <= mt_i.ack and mt_rt;
mt_o.adr <= ((14 downto 0 => '0') & rd_adr_d0(16 downto 2)) & (1 downto 0 => '0');
mt_o.sel <= wr_sel_d0;
mt_o.we <= mt_wt;
mt_o.dat <= wr_dat_d0;
-- Process for write requests.
process (rd_adr_d0, wr_req_d0, metadata_wack, adc0_wack, adc1_wack, mt_wack) begin
metadata_we <= '0';
adc0_we <= '0';
adc1_we <= '0';
mt_we <= '0';
case rd_adr_d0(17 downto 17) is
when "0" =>
case rd_adr_d0(16 downto 13) is
when "0010" =>
-- Submap metadata
metadata_we <= wr_req_d0;
wr_ack_d0 <= metadata_wack;
when "0011" =>
-- Submap adc0
adc0_we <= wr_req_d0;
wr_ack_d0 <= adc0_wack;
when "0100" =>
-- Submap adc1
adc1_we <= wr_req_d0;
wr_ack_d0 <= adc1_wack;
when others =>
wr_ack_d0 <= wr_req_d0;
end case;
when "1" =>
-- Submap mt
mt_we <= wr_req_d0;
wr_ack_d0 <= mt_wack;
when others =>
wr_ack_d0 <= wr_req_d0;
end case;
end process;
-- Process for read requests.
process (rd_adr_d0, rd_req_d0, metadata_i.dat, metadata_rack, adc0_i.dat, adc0_rack, adc1_i.dat, adc1_rack, mt_i.dat, mt_rack) begin
-- By default ack read requests
rd_dat_d0 <= (others => 'X');
metadata_re <= '0';
adc0_re <= '0';
adc1_re <= '0';
mt_re <= '0';
case rd_adr_d0(17 downto 17) is
when "0" =>
case rd_adr_d0(16 downto 13) is
when "0010" =>
-- Submap metadata
metadata_re <= rd_req_d0;
rd_dat_d0 <= metadata_i.dat;
rd_ack_d0 <= metadata_rack;
when "0011" =>
-- Submap adc0
adc0_re <= rd_req_d0;
rd_dat_d0 <= adc0_i.dat;
rd_ack_d0 <= adc0_rack;
when "0100" =>
-- Submap adc1
adc1_re <= rd_req_d0;
rd_dat_d0 <= adc1_i.dat;
rd_ack_d0 <= adc1_rack;
when others =>
rd_ack_d0 <= rd_req_d0;
end case;
when "1" =>
-- Submap mt
mt_re <= rd_req_d0;
rd_dat_d0 <= mt_i.dat;
rd_ack_d0 <= mt_rack;
when others =>
rd_ack_d0 <= rd_req_d0;
end case;
end process;
end syn;
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files = [
"wrtd_ref_svec_fd_x2.vhd",
"wrtd_fd_x2_host_map.vhd",
]
fetchto = "../../../dependencies"
modules = {
"git" : [
"https://ohwr.org/project/svec.git",
"https://ohwr.org/project/general-cores.git",
"https://ohwr.org/project/wr-cores.git",
"https://ohwr.org/project/vme64x-core.git",
"https://ohwr.org/project/urv-core.git",
"https://ohwr.org/project/mock-turtle.git",
"https://ohwr.org/project/fmc-delay-1ns-8cha.git",
"https://ohwr.org/project/ddr3-sp6-core.git",
],
}
memory-map:
name: wrtd_fd_x2_host_map
bus: wb-32-be
size: 0x80000
x-hdl:
busgroup: True
children:
- submap:
name: metadata
description: a ROM containing the carrier metadata
address: 0x4000
size: 0x40
interface: wb-32-be
x-hdl:
busgroup: True
- submap:
name: fd
description: FD
address: 0x10000
size: 0x10000
interface: wb-32-be
x-hdl:
busgroup: True
- submap:
name: mt
description: Mock Turtle
address: 0x20000
size: 0x20000
interface: wb-32-be
x-hdl:
busgroup: True
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files = [
"wrtd_ref_svec_tdc_fd.vhd",
]
fetchto = "../../../dependencies"
modules = {
"git" : [
"https://ohwr.org/project/svec.git",
"https://ohwr.org/project/general-cores.git",
"https://ohwr.org/project/wr-cores.git",
"https://ohwr.org/project/vme64x-core.git",
"https://ohwr.org/project/urv-core.git",
"https://ohwr.org/project/mock-turtle.git",
"https://ohwr.org/project/fmc-tdc.git",
"https://ohwr.org/project/fmc-delay-1ns-8cha.git",
"https://ohwr.org/project/ddr3-sp6-core.git",
],
}
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files = [
"wrtd_ref_svec_tdc_x2.vhd",
"wrtd_tdc_x2_host_map.vhd",
"wrtd_tdc_x2_fmc_map.vhd",
]
fetchto = "../../../dependencies"
modules = {
"git" : [
"https://ohwr.org/project/svec.git",
"https://ohwr.org/project/general-cores.git",
"https://ohwr.org/project/wr-cores.git",
"https://ohwr.org/project/vme64x-core.git",
"https://ohwr.org/project/urv-core.git",
"https://ohwr.org/project/mock-turtle.git",
"https://ohwr.org/project/fmc-tdc.git",
"https://ohwr.org/project/fmc-delay-1ns-8cha.git",
"https://ohwr.org/project/ddr3-sp6-core.git",
],
}
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# SPDX-FileCopyrightText: 2022 CERN (home.cern)
# SPDX-License-Identifier: CC0-1.0
__pycache__/
# SPDX-FileCopyrightText: 2022 CERN (home.cern)
# SPDX-License-Identifier: CC0-1.0
[pytest]
addopts = -v
testpaths =
tests
filterwarnings =
ignore::pytest.PytestCacheWarning
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