Commit 27cd661f authored by Dimitris Lampridis's avatar Dimitris Lampridis

hdl: SVEC TDC+FDEL ref design: adjust and update constraints

parent 4dcd8371
......@@ -710,50 +710,59 @@ TIMESPEC TS_fmc0_tdc_125m_clk_n_i = PERIOD "fmc0_tdc_125m_clk_n_i" 8 ns HIGH 50%
NET "fmc1_fd_clk_ref_n_i" TNM_NET = fmc1_fd_clk_ref_n_i;
TIMESPEC TS_fmc1_fd_clk_ref_n_i = PERIOD "fmc1_fd_clk_ref_n_i" 8 ns HIGH 50%;
# relax all paths through syncrhonisers:
# 1. define groups for each clock domain
# 2. define group for all sync chains
# 3. create sync chain groups that exclude one clock domain each
# 4. relax path from each clock domain to respective sync chain group
NET "clk_ref_125m" TNM_NET = clk_125m_pllref;
NET "clk_sys_62m5" TNM_NET = clk_sys;
NET "dcm1_clk_ref_0" TNM_NET = dcm1_clk_ref_0;
NET "tdc_clk_125m" TNM_NET = tdc_clk_125m;
NET "cmp_xwrc_board_svec/phy8_to_wrc_rx_clk" TNM_NET = phy_rx_rbclk;
NET "*/gc_sync_ffs_in" TNM_NET = "sync_ffs";
NET "*/gc_sync_register_in[*]" TNM_NET = "sync_reg";
TIMEGRP "synchronizers"="sync_ffs" "sync_reg";
#----------------------------------------
# WR DMTD tweaks
#----------------------------------------
TIMEGRP "ref_sync"="synchronizers" EXCEPT "clk_125m_pllref";
TIMEGRP "sys_sync"="synchronizers" EXCEPT "clk_sys";
TIMEGRP "fdl_sync"="synchronizers" EXCEPT "dcm1_clk_ref_0";
TIMEGRP "tdc_sync"="synchronizers" EXCEPT "tdc_clk_125m";
TIMEGRP "phy_sync"="synchronizers" EXCEPT "phy_rx_rbclk";
INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds*/clk_in" TNM = skew_limit;
INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds*/clk_in" TNM = skew_limit;
TIMESPEC TS_ref_sync_ffs = FROM clk_125m_pllref TO "ref_sync" 20ns DATAPATHONLY;
TIMESPEC TS_sys_sync_ffs = FROM clk_sys TO "sys_sync" 20ns DATAPATHONLY;
TIMESPEC TS_fdl_sync_ffs = FROM dcm1_clk_ref_0 TO "fdl_sync" 20ns DATAPATHONLY;
TIMESPEC TS_tdc_sync_ffs = FROM tdc_clk_125m TO "tdc_sync" 20ns DATAPATHONLY;
TIMESPEC TS_phy_sync_ffs = FROM phy_rx_rbclk TO "phy_sync" 20ns DATAPATHONLY;
TIMESPEC TS_dmtd_skew = FROM "skew_limit" TO "FFS" 1 ns DATAPATHONLY;
# Relax the path where TAI time crosses from WR ref to MT sys clock
# This is already synced via a gc_pulse_synchronizer, which makes sure that
# TAI WR ref value is stable when sampled by the MT sys clock
NET "cmp_mock_turtle/gen_cpus[*].U_CPU_Block/tm_p_sys" TNM_NET = "tm_mt_sync";
#----------------------------------------
# Asynchronous resets
#----------------------------------------
TIMESPEC TS_tm_mt_sync = FROM clk_125m_pllref TO "tm_mt_sync" 20ns DATAPATHONLY;
NET "rst_n_i" TIG;
NET "vme_sysreset_n_i" TIG;
# Relax timing from spll_aligner outputs cref and cin (driven by ref clock)
# to the spll registers (driven by sys clock). The two sides are already sychronized
# via a gc_pulse_synchronizer, which makes sure that cref and cin are stable
# when sampled by the sys clock.
NET "*/WRPC/U_SOFTPLL/U_Wrapped_Softpll/aligner_sample_cref(*)" TNM_NET = "wr_spll_sync";
NET "*/WRPC/U_SOFTPLL/U_Wrapped_Softpll/aligner_sample_cin(*)" TNM_NET = "wr_spll_sync";
#----------------------------------------
# Cross-clock domain sync
#----------------------------------------
TIMESPEC TS_wr_spll_sync = FROM clk_125m_pllref TO "wr_spll_sync" 20ns DATAPATHONLY;
# Declaration of domains
NET "clk_ref_125m" TNM_NET = clk_125m_pllref;
NET "clk_sys_62m5" TNM_NET = clk_sys;
NET "dcm1_clk_ref_0" TNM_NET = dcm1_clk_ref_0;
NET "tdc_clk_125m" TNM_NET = tdc_clk_125m;
NET "cmp_xwrc_board_svec/phy8_to_wrc_rx_clk" TNM_NET = phy_rx_rbclk;
# External async resets
NET "rst_n_i" TIG;
NET "vme_sysreset_n_i" TIG;
# Exceptions for crossings via gc_sync_ffs
NET "*/gc_sync_ffs_in" TNM = FFS "sync_ffs";
TIMEGRP "ref_sync_ffs" = "sync_ffs" EXCEPT "clk_125m_pllref";
TIMEGRP "sys_sync_ffs" = "sync_ffs" EXCEPT "clk_sys";
TIMEGRP "fdl_sync_ffs" = "sync_ffs" EXCEPT "dcm1_clk_ref_0";
TIMEGRP "tdc_sync_ffs" = "sync_ffs" EXCEPT "tdc_clk_125m";
TIMEGRP "phy_sync_ffs" = "sync_ffs" EXCEPT "phy_rx_rbclk";
TIMESPEC TS_ref_sync_ffs = FROM clk_125m_pllref TO "ref_sync_ffs" TIG;
TIMESPEC TS_sys_sync_ffs = FROM clk_sys TO "sys_sync_ffs" TIG;
TIMESPEC TS_fdl_sync_ffs = FROM dcm1_clk_ref_0 TO "fdl_sync_ffs" TIG;
TIMESPEC TS_tdc_sync_ffs = FROM tdc_clk_125m TO "tdc_sync_ffs" TIG;
TIMESPEC TS_phy_sync_ffs = FROM phy_rx_rbclk TO "phy_sync_ffs" TIG;
# Exceptions for crossings via gc_sync_register
#NET "*/gc_sync_register_in[*]" TNM = FFS "sync_reg";
#TIMEGRP "ref_sync_reg" = "sync_reg" EXCEPT "clk_125m_pllref";
#TIMEGRP "sys_sync_reg" = "sync_reg" EXCEPT "clk_sys";
#TIMEGRP "fdl_sync_reg" = "sync_reg" EXCEPT "dcm1_clk_ref_0";
#TIMEGRP "tdc_sync_reg" = "sync_reg" EXCEPT "tdc_clk_125m";
#TIMEGRP "phy_sync_reg" = "sync_reg" EXCEPT "phy_rx_rbclk";
#TIMESPEC TS_ref_sync_reg = FROM clk_125m_pllref TO "ref_sync_reg" 8ns DATAPATHONLY;
#TIMESPEC TS_sys_sync_reg = FROM clk_sys TO "sys_sync_reg" 16ns DATAPATHONLY;
#TIMESPEC TS_fdl_sync_reg = FROM dcm1_clk_ref_0 TO "fdl_sync_reg" 8ns DATAPATHONLY;
#TIMESPEC TS_tdc_sync_reg = FROM tdc_clk_125m TO "tdc_sync_reg" 8ns DATAPATHONLY;
#TIMESPEC TS_phy_sync_reg = FROM phy_rx_rbclk TO "phy_sync_reg" 8ns DATAPATHONLY;
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