Commit 0aa922c4 authored by Dimitris Lampridis's avatar Dimitris Lampridis

[hdl] update SPEC ref design testbench to follow convention

parent e61f03ef
Subproject commit c010febba58a1b616c971f6fd8c953df51e411b6
Subproject commit ac43a1dbde29bcbd9126d877477e77b620176bac
Subproject commit 72adf76dab9a6fc33fbff7c86d786c31e175a46a
Subproject commit 2d01bc96a015a14ae90a449a52b86105c5c99b75
Subproject commit ed94f8594009fda6deafde22532fb48c321792b9
Subproject commit 00b12ec7cca6d304b0e2646fa5af66cd896d3aa9
......@@ -23,7 +23,7 @@ include_dirs = [
files = [
"main.sv",
"dut_env.sv",
"synthesis_descriptor.vhd",
"buildinfo_pkg.vhd",
]
modules = {
......
-- Buildinfo for project blah
--
-- This file was automatically generated; do not edit
package buildinfo_pkg is
constant buildinfo : string :=
"buildinfo:1" & LF
& "module:wrtd_ref_spec150t_adc" & LF
& "commit:cb32df93f503c2ec56ef759ec063dd8557848e2b" & LF
& "syntool:modelsim" & LF
& "syndate:Wednesday, July 17 2019" & LF
& "synauth:Dimitris Lampridis" & LF;
end buildinfo_pkg;
......@@ -291,16 +291,16 @@ module dut_env
initial begin
// Skip WR SoftPLL lock
force DUT.cmp_xwrc_board_spec.cmp_board_common.cmp_xwr_core.
WRPC.U_SOFTPLL.U_Wrapped_Softpll.out_locked_o = 3'b111;
force DUT.cmp_spec_template_wr.cmp_xwrc_board_spec.cmp_board_common.cmp_xwr_core.WRPC.
U_SOFTPLL.U_Wrapped_Softpll.out_locked_o = 3'b111;
// Silence Xilinx unisim DSP48A1 warnings about invalid OPMODE
force DUT.cmp_xwrc_board_spec.cmp_board_common.cmp_xwr_core.
force DUT.cmp_spec_template_wr.cmp_xwrc_board_spec.cmp_board_common.cmp_xwr_core.
WRPC.LM32_CORE.gen_profile_medium_icache.U_Wrapped_LM32.cpu.
multiplier.D1.OPMODE_dly = 0;
force DUT.cmp_xwrc_board_spec.cmp_board_common.cmp_xwr_core.
force DUT.cmp_spec_template_wr.cmp_xwrc_board_spec.cmp_board_common.cmp_xwr_core.
WRPC.LM32_CORE.gen_profile_medium_icache.U_Wrapped_LM32.cpu.
multiplier.D2.OPMODE_dly = 0;
force DUT.cmp_xwrc_board_spec.cmp_board_common.cmp_xwr_core.
force DUT.cmp_spec_template_wr.cmp_xwrc_board_spec.cmp_board_common.cmp_xwr_core.
WRPC.LM32_CORE.gen_profile_medium_icache.U_Wrapped_LM32.cpu.
multiplier.D3.OPMODE_dly = 0;
end // initial begin
......
......@@ -168,7 +168,7 @@ module main;
accA.write('h2000, 'h00000001); // xfer start
wait (DUTA.DUT.dma_irq[0] == 1);
wait (DUTA.DUT.cmp_spec_template_wr.irqs[0] == 1);
$display("[DUT:A] <%t> END DMA 1", $realtime);
end
......@@ -194,7 +194,7 @@ module main;
accB.write('h2000, 'h00000001); // xfer start
wait (DUTB.DUT.dma_irq[0] == 1);
wait (DUTB.DUT.cmp_spec_template_wr.irqs[0] == 1);
$display("[DUT:B] <%t> END DMA 1", $realtime);
end
......
--------------------------------------------------------------------------------
-- SDB meta information for wrtd_ref_spec150t_adc.xise.
--
-- This file was automatically generated by ../../../dependencies/general-cores/tools/sdb_desc_gen.tcl on:
-- Wednesday, January 30 2019
--
-- ../../../dependencies/general-cores/tools/sdb_desc_gen.tcl is part of OHWR general-cores:
-- https://www.ohwr.org/projects/general-cores/wiki
--
-- For more information on SDB meta information, see also:
-- https://www.ohwr.org/projects/sdb/wiki
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.wishbone_pkg.all;
package synthesis_descriptor is
constant c_sdb_synthesis_info : t_sdb_synthesis := (
syn_module_name => "wrtd_ref_spec150",
syn_commit_id => "eaa378a35717954407166b2e80e34c2*",
syn_tool_name => "ISE ",
syn_tool_version => x"00000147",
syn_date => x"20190130",
syn_username => "Dimitris Lampri");
constant c_sdb_repo_url : t_sdb_repo_url := (
repo_url => "git@ohwr-gitlab.cern.ch:project/wrtd.git ");
end package synthesis_descriptor;
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