--------------------------------------------------------------------------------
-- CERN BE-CO-HT
-- LHC Instability Trigger Distribution (LIST)
-- https://ohwr.org/projects/list
--------------------------------------------------------------------------------
--
-- unit name:   svec_list_top
--
-- description: Top entity for LHC Instability Trigger Distribution project
--
-- Top level design of the SVEC-based LIST WR trigger distribution node, with
-- an FMC TDC in slot and an FMC Fine Delay in slot 2.
--
--------------------------------------------------------------------------------
-- Copyright CERN 2014-2018
--------------------------------------------------------------------------------
-- Copyright and related rights are licensed under the Solderpad Hardware
-- License, Version 2.0 (the "License"); you may not use this file except
-- in compliance with the License. You may obtain a copy of the License at
-- http://solderpad.org/licenses/SHL-2.0.
-- Unless required by applicable law or agreed to in writing, software,
-- hardware and materials distributed under this License is distributed on an
-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
-- or implied. See the License for the specific language governing permissions
-- and limitations under the License.
--------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library work;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
use work.vme64x_pkg.all;
use work.wr_board_pkg.all;
use work.wr_svec_pkg.all;
use work.wr_fabric_pkg.all;
use work.mt_mqueue_pkg.all;
use work.mock_turtle_pkg.all;
use work.synthesis_descriptor.all;
use work.wr_xilinx_pkg.all;
use work.wr_board_pkg.all;
{use}

entity {name}_top is
  generic (
    g_WRPC_INITF : string  := "{topdir}/wr-cores/bin/wrpc/wrc_phy8.bram";
    g_MT_CPU0_INITF  : string  := "../../../../software/firmware/tdc/wrtd-rt-tdc.bram";
    g_MT_CPU1_INITF  : string  := "../../../../software/firmware/fd/wrtd-rt-fd.bram";
    -- Simulation-mode enable parameter. Set by default (synthesis) to 0, and
    -- changed to non-zero in the instantiation of the top level DUT in the
    -- testbench. Its purpose is to reduce some internal counters/timeouts
    -- to speed up simulations.
    g_SIMULATION     : integer := 0;
    -- Bypass VME core, useful only in simulation
    g_SIM_BYPASS_VME : boolean := FALSE);
  port (
    ---------------------------------------------------------------------------
    -- Clocks/resets
    ---------------------------------------------------------------------------

    -- Reset from system fpga
    rst_n_i : in std_logic;

    -- Local oscillators
    clk_20m_vcxo_i : in std_logic;  -- 20MHz VCXO clock

    clk_125m_pllref_p_i : in std_logic;  -- 125 MHz PLL reference
    clk_125m_pllref_n_i : in std_logic;

    clk_125m_gtp_n_i : in std_logic;  -- 125 MHz GTP reference
    clk_125m_gtp_p_i : in std_logic;

    ---------------------------------------------------------------------------
    -- VME interface
    ---------------------------------------------------------------------------

    -- Bypass VME core, useful only in simulation
    -- synthesis translate_off
    sim_wb_i : in  t_wishbone_slave_in := cc_dummy_slave_in;
    sim_wb_o : out t_wishbone_slave_out;
    -- synthesis translate_on

    vme_write_n_i    : in    std_logic;
    vme_sysreset_n_i : in    std_logic;
    vme_retry_oe_o   : out   std_logic;
    vme_retry_n_o    : out   std_logic;
    vme_lword_n_b    : inout std_logic;
    vme_iackout_n_o  : out   std_logic;
    vme_iackin_n_i   : in    std_logic;
    vme_iack_n_i     : in    std_logic;
    vme_gap_i        : in    std_logic;
    vme_dtack_oe_o   : out   std_logic;
    vme_dtack_n_o    : out   std_logic;
    vme_ds_n_i       : in    std_logic_vector(1 downto 0);
    vme_data_oe_n_o  : out   std_logic;
    vme_data_dir_o   : out   std_logic;
    vme_berr_o       : out   std_logic;
    vme_as_n_i       : in    std_logic;
    vme_addr_oe_n_o  : out   std_logic;
    vme_addr_dir_o   : out   std_logic;
    vme_irq_o        : out   std_logic_vector(7 downto 1);
    vme_ga_i         : in    std_logic_vector(4 downto 0);
    vme_data_b       : inout std_logic_vector(31 downto 0);
    vme_am_i         : in    std_logic_vector(5 downto 0);
    vme_addr_b       : inout std_logic_vector(31 downto 1);

    ---------------------------------------------------------------------------
    -- SPI interfaces to DACs
    ---------------------------------------------------------------------------

    pll20dac_din_o    : out std_logic;
    pll20dac_sclk_o   : out std_logic;
    pll20dac_sync_n_o : out std_logic;
    pll25dac_din_o    : out std_logic;
    pll25dac_sclk_o   : out std_logic;
    pll25dac_sync_n_o : out std_logic;

    ---------------------------------------------------------------------------
    -- SFP I/O for transceiver
    ---------------------------------------------------------------------------

    sfp_txp_o         : out   std_logic;
    sfp_txn_o         : out   std_logic;
    sfp_rxp_i         : in    std_logic;
    sfp_rxn_i         : in    std_logic;
    sfp_mod_def0_i    : in    std_logic;  -- sfp detect
    sfp_mod_def1_b    : inout std_logic;  -- scl
    sfp_mod_def2_b    : inout std_logic;  -- sda
    sfp_rate_select_o : out   std_logic;
    sfp_tx_fault_i    : in    std_logic;
    sfp_tx_disable_o  : out   std_logic;
    sfp_los_i         : in    std_logic;

    ---------------------------------------------------------------------------
    -- Carrier I2C EEPROM
    ---------------------------------------------------------------------------

    carrier_scl_b : inout std_logic;
    carrier_sda_b : inout std_logic;

    ---------------------------------------------------------------------------
    -- Onewire interface
    ---------------------------------------------------------------------------

    onewire_b : inout std_logic;

    ---------------------------------------------------------------------------
    -- UART
    ---------------------------------------------------------------------------

    uart_rxd_i : in  std_logic;
    uart_txd_o : out std_logic;

    ---------------------------------------------------------------------------
    -- SPI (flash is connected to SFPGA and routed to AFPGA
    -- once the boot process is complete)
    ---------------------------------------------------------------------------

    spi_sclk_o : out std_logic;
    spi_ncs_o  : out std_logic;
    spi_mosi_o : out std_logic;
    spi_miso_i : in  std_logic;

    ---------------------------------------------------------------------------
    -- Carrier front panel LEDs and IOs
    ---------------------------------------------------------------------------

    fp_led_line_oen_o : out std_logic_vector(1 downto 0);
    fp_led_line_o     : out std_logic_vector(1 downto 0);
    fp_led_column_o   : out std_logic_vector(3 downto 0);

    fp_gpio1_o      : out std_logic;  -- PPS output
    fp_gpio2_o      : out std_logic;  -- Ref clock div2 output
    fp_gpio3_i      : in  std_logic;  -- ext 10MHz clock input
    fp_gpio4_i      : in  std_logic;  -- ext PPS input
    fp_term_en_o    : out std_logic_vector(4 downto 1);
    fp_gpio1_a2b_o  : out std_logic;
    fp_gpio2_a2b_o  : out std_logic;
    fp_gpio34_a2b_o : out std_logic;

{ports}

    fmc0_prsntm2c_n_i : in std_logic;

    fmc0_scl_b : inout std_logic;
    fmc0_sda_b : inout std_logic;

    fmc1_prsntm2c_n_i : in std_logic;

    fmc1_scl_b : inout std_logic;
    fmc1_sda_b : inout std_logic);

end entity {name}_top;

architecture arch of {name}_top is

  -----------------------------------------------------------------------------
  -- Constants
  -----------------------------------------------------------------------------

  -- WRPC Xilinx platform auxiliary clock configuration, used for DDR clock
  constant c_WRPC_PLL_CONFIG : t_px_pll_cfg := (
    enabled => TRUE, divide => 3, multiply => 8 );


  -- Number of masters attached to the primary wishbone crossbar
  constant c_NUM_WB_MASTERS : integer := 1;

  -- Number of slaves attached to the primary wishbone crossbar
  constant c_NUM_WB_SLAVES : integer := {nbr_slaves} + 3;

  -- Primary Wishbone master(s) offsets
  constant c_WB_MASTER_VME : integer := 0;

  -- Primary Wishbone slave(s) offsets
  constant c_WB_SLAVE_VIC  : integer := 0;
{slaves_decl}
  constant c_WB_SLAVE_MT   : integer := {nbr_slaves} + 1;
  constant c_WB_SLAVE_WRC  : integer := {nbr_slaves} + 2;
  constant c_WB_DESC_SYN   : integer := {nbr_slaves} + 3;
  constant c_WB_DESC_URL   : integer := {nbr_slaves} + 4;

  -- sdb header address on primary crossbar
  constant c_SDB_ADDRESS : t_wishbone_address := x"00000000";

  -- f_xwb_bridge_manual_sdb(size, sdb_addr)
  -- Note: sdb_addr is the sdb records address relative to the bridge base address
  constant c_wrc_bridge_sdb : t_sdb_bridge :=
    f_xwb_bridge_manual_sdb(x"0003ffff", x"00030000");

{sdb-decl}

  -- Primary wishbone crossbar layout
  constant c_WB_LAYOUT : t_sdb_record_array(c_NUM_WB_SLAVES + 1 downto 0) := (
    c_WB_SLAVE_VIC  => f_sdb_embed_device(c_XWB_VIC_SDB, x"00002000"),
{sdb-layout}
    c_WB_SLAVE_MT   => f_sdb_embed_device(c_MOCK_TURTLE_SDB, x"00020000"),
    c_WB_SLAVE_WRC  => f_sdb_embed_bridge(c_wrc_bridge_sdb, x"00040000"),
    c_WB_DESC_SYN   => f_sdb_embed_synthesis(c_SDB_SYNTHESIS_INFO),
    c_WB_DESC_URL   => f_sdb_embed_repo_url(c_SDB_REPO_URL));

  -- not really used, will be reprogrammed by software
  constant c_VIC_VECTOR_TABLE : t_wishbone_address_array(0 to 5) := (
    0 => x"00011500",   -- FMC0  EIC address
    1 => x"00018000",   -- FMC1
    2 => x"00020000",   -- MT Mqueue in interrupt
    3 => x"00020001",   -- MT Mqueue out interrupt
    4 => x"00020002",   -- MT Console interrupt
    5 => x"00020003");  -- MT Notify interrupt

  constant c_FMC_MUX_ADDR : t_wishbone_address_array(0 downto 0) :=
    (0 => x"00000000");
  constant c_FMC_MUX_MASK : t_wishbone_address_array(0 downto 0) :=
    (0 => x"10000000");

 {mt_config}

  -----------------------------------------------------------------------------
  -- Signals
  -----------------------------------------------------------------------------

  -- Wishbone buse(s) from masters attached to crossbar
  signal cnx_master_out : t_wishbone_master_out_array(c_NUM_WB_MASTERS-1 downto 0);
  signal cnx_master_in  : t_wishbone_master_in_array(c_NUM_WB_MASTERS-1 downto 0);

  -- Wishbone buse(s) to slaves attached to crossbar
  signal cnx_slave_out : t_wishbone_slave_out_array(c_NUM_WB_SLAVES-1 downto 0);
  signal cnx_slave_in  : t_wishbone_slave_in_array(c_NUM_WB_SLAVES-1 downto 0);

  -- clock and reset
  signal areset_n         : std_logic;
  signal clk_sys_62m5     : std_logic;
  signal rst_sys_62m5_n   : std_logic;
  signal clk_ref_125m     : std_logic;
  signal rst_ref_125m_n   : std_logic;
  signal clk_ddr_333m     : std_logic;
  signal rst_ddr_333m_n   : std_logic;
  signal clk_ref_div2     : std_logic;
  signal clk_ext_ref      : std_logic;
  signal fmc0_clk_125m    : std_logic;
  signal fmc1_clk_125m    : std_logic;

  attribute keep                   : string;
  attribute keep of clk_sys_62m5   : signal is "TRUE";
  attribute keep of clk_ref_125m   : signal is "TRUE";
  attribute keep of clk_ddr_333m   : signal is "TRUE";
  attribute keep of fmc0_clk_125m  : signal is "TRUE";
  attribute keep of fmc1_clk_125m  : signal is "TRUE";
  attribute keep of rst_ddr_333m_n : signal is "TRUE";

  -- I2C EEPROM
  signal eeprom_sda_in  : std_logic;
  signal eeprom_sda_out : std_logic;
  signal eeprom_scl_in  : std_logic;
  signal eeprom_scl_out : std_logic;

  -- VME
  signal vme_data_b_out    : std_logic_vector(31 downto 0);
  signal vme_addr_b_out    : std_logic_vector(31 downto 1);
  signal vme_lword_n_b_out : std_logic;
  signal Vme_data_dir_int  : std_logic;
  signal vme_addr_dir_int  : std_logic;
  signal vme_ga            : std_logic_vector(5 downto 0);
  signal vme_berr_n        : std_logic;
  signal vme_irq_n         : std_logic_vector(7 downto 1);
  signal vme_access_led    : std_logic;

  -- SFP
  signal sfp_sda_in  : std_logic;
  signal sfp_sda_out : std_logic;
  signal sfp_scl_in  : std_logic;
  signal sfp_scl_out : std_logic;

  -- OneWire
  signal onewire_data : std_logic;
  signal onewire_oe   : std_logic;

  -- LEDs and GPIO
  signal pps         : std_logic;
  signal pps_led     : std_logic;
  signal pps_ext_in  : std_logic;
  signal svec_led    : std_logic_vector(15 downto 0);
  signal wr_led_link : std_logic;
  signal wr_led_act  : std_logic;

  -- VIC
  signal fmc_host_irq   : std_logic_vector(1 downto 0) := "00";
  signal mt_hmq_in_irq  : std_logic;
  signal mt_hmq_out_irq : std_logic;
  signal mt_console_irq : std_logic;
  signal mt_notify_irq  : std_logic;
  signal vic_master_irq : std_logic;

  --  MT endpoints
  signal rmq_endpoint_out : t_mt_rmq_endpoint_iface_out;
  signal rmq_endpoint_in  : t_mt_rmq_endpoint_iface_in;
  signal rmq_src_in       : t_mt_stream_source_in;
  signal rmq_src_out      : t_mt_stream_source_out;
  signal rmq_src_cfg_in   : t_mt_stream_config_in;
  signal rmq_src_cfg_out  : t_mt_stream_config_out;
  signal rmq_snk_in       : t_mt_stream_sink_in;
  signal rmq_snk_out      : t_mt_stream_sink_out;
  signal rmq_snk_cfg_in   : t_mt_stream_config_in;
  signal rmq_snk_cfg_out  : t_mt_stream_config_out;

  --  MT fabric.
  signal eth_tx_out : t_wrf_source_out;
  signal eth_tx_in  : t_wrf_source_in;
  signal eth_rx_out : t_wrf_sink_out;
  signal eth_rx_in  : t_wrf_sink_in;

  -- MT Dedicated WB interfaces to FMCs
  signal fmc_dp_wb_out : t_wishbone_master_out_array(0 to {ncpus} - 1);
  signal fmc_dp_wb_in  : t_wishbone_master_in_array(0 to {ncpus} - 1);

  -- WRPC TM interface and aux clocks
  signal tm_link_up         : std_logic;
  signal tm_tai             : std_logic_vector(39 downto 0);
  signal tm_cycles          : std_logic_vector(27 downto 0);
  signal tm_time_valid      : std_logic;
  signal tm_clk_aux_lock_en : std_logic_vector(1 downto 0);
  signal tm_clk_aux_locked  : std_logic_vector(1 downto 0);
  signal tm_dac_value       : std_logic_vector(23 downto 0);
  signal tm_dac_wr          : std_logic_vector(1 downto 0);
  signal wrabbit_en         : std_logic;

  -- MT TM interface
  signal tm : t_mt_timing_if;

  signal fmc0_scl_out : std_logic := '1';
  signal fmc0_sda_out : std_logic := '1';

  signal fmc1_scl_out : std_logic := '1';
  signal fmc1_sda_out : std_logic := '1';

  attribute iob : string;
  attribute iob of pps : signal is "FORCE";

{decls}

begin  -- architecture arch

  -----------------------------------------------------------------------------
  -- System reset
  -----------------------------------------------------------------------------
  areset_n <= vme_sysreset_n_i and rst_n_i;

  -----------------------------------------------------------------------------
  -- Primary wishbone Crossbar
  -----------------------------------------------------------------------------

  cmp_sdb_crossbar : xwb_sdb_crossbar
    generic map (
      g_num_masters => c_NUM_WB_MASTERS,
      g_num_slaves  => c_NUM_WB_SLAVES,
      g_registered  => TRUE,
      g_wraparound  => TRUE,
      g_layout      => c_WB_LAYOUT,
      g_sdb_addr    => c_SDB_ADDRESS)
    port map (
      clk_sys_i => clk_sys_62m5,
      rst_n_i   => rst_sys_62m5_n,
      slave_i   => cnx_master_out,
      slave_o   => cnx_master_in,
      master_i  => cnx_slave_out,
      master_o  => cnx_slave_in);

  -----------------------------------------------------------------------------
  -- VME64x Core (WB Master)
  -----------------------------------------------------------------------------

  gen_with_vme64_core : if not g_SIM_BYPASS_VME generate
    cmp_vme_core : xvme64x_core
      generic map (
        g_CLOCK_PERIOD    => 16,
        g_DECODE_AM       => TRUE,
        g_USER_CSR_EXT    => FALSE,
        g_WB_GRANULARITY  => BYTE,
        g_MANUFACTURER_ID => c_CERN_ID,
        g_BOARD_ID        => c_SVEC_ID,
        g_REVISION_ID     => c_SVEC_REVISION_ID,
        g_PROGRAM_ID      => c_SVEC_PROGRAM_ID)
      port map (
        clk_i           => clk_sys_62m5,
        rst_n_i         => rst_sys_62m5_n,
        vme_i.as_n      => vme_as_n_i,
        vme_i.rst_n     => vme_sysreset_n_i,
        vme_i.write_n   => vme_write_n_i,
        vme_i.am        => vme_am_i,
        vme_i.ds_n      => vme_ds_n_i,
        vme_i.ga        => vme_ga,
        vme_i.lword_n   => vme_lword_n_b,
        vme_i.addr      => vme_addr_b,
        vme_i.data      => vme_data_b,
        vme_i.iack_n    => vme_iack_n_i,
        vme_i.iackin_n  => vme_iackin_n_i,
        vme_o.berr_n    => vme_berr_n,
        vme_o.dtack_n   => vme_dtack_n_o,
        vme_o.retry_n   => vme_retry_n_o,
        vme_o.retry_oe  => vme_retry_oe_o,
        vme_o.lword_n   => vme_lword_n_b_out,
        vme_o.data      => vme_data_b_out,
        vme_o.addr      => vme_addr_b_out,
        vme_o.irq_n     => vme_irq_n,
        vme_o.iackout_n => vme_iackout_n_o,
        vme_o.dtack_oe  => vme_dtack_oe_o,
        vme_o.data_dir  => vme_data_dir_int,
        vme_o.data_oe_n => vme_data_oe_n_o,
        vme_o.addr_dir  => vme_addr_dir_int,
        vme_o.addr_oe_n => vme_addr_oe_n_o,
        wb_o            => cnx_master_out(c_WB_MASTER_VME),
        wb_i            => cnx_master_in(c_WB_MASTER_VME),
        int_i           => vic_master_irq);

    vme_ga     <= vme_gap_i & vme_ga_i;
    vme_berr_o <= not vme_berr_n;
    vme_irq_o  <= not vme_irq_n;

    -- VME tri-state buffers
    vme_data_b    <= vme_data_b_out    when vme_data_dir_int = '1' else (others => 'Z');
    vme_addr_b    <= vme_addr_b_out    when vme_addr_dir_int = '1' else (others => 'Z');
    vme_lword_n_b <= vme_lword_n_b_out when vme_addr_dir_int = '1' else 'Z';

    vme_addr_dir_o <= vme_addr_dir_int;
    vme_data_dir_o <= vme_data_dir_int;

  end generate gen_with_vme64_core;

  gen_without_vme64_core : if g_SIM_BYPASS_VME generate
    -- synthesis translate_off
    cnx_master_out(c_WB_MASTER_VME) <= sim_wb_i;
    sim_wb_o                        <= cnx_master_in(c_WB_MASTER_VME);
  -- synthesis translate_on
  end generate gen_without_vme64_core;

  cmp_vme_led_extend : gc_extend_pulse
    generic map (
      g_width => 5000000)
    port map (
      clk_i      => clk_sys_62m5,
      rst_n_i    => rst_sys_62m5_n,
      pulse_i    => cnx_slave_in(c_WB_MASTER_VME).cyc,
      extended_o => vme_access_led);

  -----------------------------------------------------------------------------
  -- Vectored Interrupt Controller (WB Slave)
  -----------------------------------------------------------------------------

  cmp_vic : xwb_vic
    generic map (
      g_INTERFACE_MODE      => PIPELINED,
      g_ADDRESS_GRANULARITY => BYTE,
      g_NUM_INTERRUPTS      => 6,
      g_INIT_VECTORS        => c_VIC_VECTOR_TABLE)
    port map (
      clk_sys_i    => clk_sys_62m5,
      rst_n_i      => rst_sys_62m5_n,
      slave_i      => cnx_slave_in(c_WB_SLAVE_VIC),
      slave_o      => cnx_slave_out(c_WB_SLAVE_VIC),
      irqs_i(0)    => fmc_host_irq(0),
      irqs_i(1)    => fmc_host_irq(1),
      irqs_i(2)    => mt_hmq_in_irq,
      irqs_i(3)    => mt_hmq_out_irq,
      irqs_i(4)    => mt_console_irq,
      irqs_i(5)    => mt_notify_irq,
      irq_master_o => vic_master_irq);

  -----------------------------------------------------------------------------
  -- Mock Turtle (WB Slave)
  -----------------------------------------------------------------------------

  cmp_mock_turtle : entity work.mock_turtle_core
    generic map (
      g_CONFIG            => c_MT_CONFIG,
      g_CPU0_IRAM_INITF   => g_MT_CPU0_INITF,
      g_CPU1_IRAM_INITF   => g_MT_CPU1_INITF,
      g_WITH_WHITE_RABBIT => TRUE)
    port map (
      clk_i          => clk_sys_62m5,
      rst_n_i        => rst_sys_62m5_n,
      sp_master_o    => open,
      sp_master_i    => c_DUMMY_WB_MASTER_IN,
      dp_master_o    => fmc_dp_wb_out,
      dp_master_i    => fmc_dp_wb_in,
      rmq_endpoint_o => rmq_endpoint_out,
      rmq_endpoint_i => rmq_endpoint_in,
      host_slave_i   => cnx_slave_in(c_WB_SLAVE_MT),
      host_slave_o   => cnx_slave_out(c_WB_SLAVE_MT),
      clk_ref_i      => clk_ref_125m,
      tm_i           => tm,
      hmq_in_irq_o   => mt_hmq_in_irq,
      hmq_out_irq_o  => mt_hmq_out_irq,
      notify_irq_o   => mt_notify_irq,
      console_irq_o  => mt_console_irq);

  tm.cycles                 <= tm_cycles;
  tm.tai                    <= tm_tai;
  tm.time_valid             <= tm_time_valid;
  tm.link_up                <= tm_link_up;
  tm.aux_locked(1 downto 0) <= tm_clk_aux_locked;
  tm.aux_locked(7 downto 2) <= (others => '0');

  cmp_eth_endpoint : entity work.mt_ep_ethernet_single
    port map (
      clk_i            => clk_sys_62m5,
      rst_n_i          => rst_sys_62m5_n,
      rmq_src_i        => rmq_src_in,
      rmq_src_o        => rmq_src_out,
      rmq_src_config_i => rmq_snk_cfg_out,
      rmq_src_config_o => rmq_snk_cfg_in,
      rmq_snk_i        => rmq_snk_in,
      rmq_snk_o        => rmq_snk_out,
      rmq_snk_config_i => rmq_src_cfg_out,
      rmq_snk_config_o => rmq_src_cfg_in,
      eth_src_o        => eth_tx_out,
      eth_src_i        => eth_tx_in,
      eth_snk_o        => eth_rx_out,
      eth_snk_i        => eth_rx_in);

  p_rmq_assign : process (rmq_endpoint_out, rmq_snk_cfg_in, rmq_snk_out,
                          rmq_src_cfg_in, rmq_src_out) is
  begin

    rmq_endpoint_in <= c_MT_RMQ_ENDPOINT_IFACE_IN_DEFAULT_VALUE;

    -- WR->MT (RX, to MT CPU1)
    rmq_src_in                          <= rmq_endpoint_out.snk_out(1)(0);
    rmq_endpoint_in.snk_in(1)(0)        <= rmq_src_out;
    rmq_snk_cfg_out                     <= rmq_endpoint_out.snk_config_out(1)(0);
    rmq_endpoint_in.snk_config_in(1)(0) <= rmq_snk_cfg_in;

    -- MT->WR (TX, from MT CPU0)
    rmq_snk_in                          <= rmq_endpoint_out.src_out(0)(0);
    rmq_endpoint_in.src_in(0)(0)        <= rmq_snk_out;
    rmq_src_cfg_out                     <= rmq_endpoint_out.src_config_out(0)(0);
    rmq_endpoint_in.src_config_in(0)(0) <= rmq_src_cfg_in;

  end process p_rmq_assign;

  -----------------------------------------------------------------------------
  -- The WR PTP core SVEC board package (WB Slave)
  -----------------------------------------------------------------------------

  cmp_xwrc_board_svec : xwrc_board_svec
    generic map (
      g_simulation     => g_simulation,
      g_WITH_EXTERNAL_CLOCK_INPUT => True,
      g_dpram_initf    => g_WRPC_INITF,
      g_AUX_PLL_CONFIG => c_WRPC_PLL_CONFIG,
      g_fabric_iface   => PLAIN,
      g_aux_clks       => 2)
    port map (
      clk_20m_vcxo_i       => clk_20m_vcxo_i,
      clk_125m_pllref_p_i  => clk_125m_pllref_p_i,
      clk_125m_pllref_n_i  => clk_125m_pllref_n_i,
      clk_125m_gtp_n_i     => clk_125m_gtp_n_i,
      clk_125m_gtp_p_i     => clk_125m_gtp_p_i,

      clk_10m_ext_i        => clk_ext_ref,
      pps_ext_i            => pps_ext_in,
      clk_aux_i(0)         => fmc0_clk_125m,
      clk_aux_i(1)         => fmc1_clk_125m,

      areset_n_i           => areset_n,
      clk_sys_62m5_o       => clk_sys_62m5,
      clk_ref_125m_o       => clk_ref_125m,
      clk_pll_aux_o        => clk_ddr_333m,
      rst_sys_62m5_n_o     => rst_sys_62m5_n,
      rst_ref_125m_n_o     => rst_ref_125m_n,
      rst_pll_aux_n_o      => rst_ddr_333m_n,
      pll20dac_din_o       => pll20dac_din_o,
      pll20dac_sclk_o      => pll20dac_sclk_o,
      pll20dac_sync_n_o    => pll20dac_sync_n_o,
      pll25dac_din_o       => pll25dac_din_o,
      pll25dac_sclk_o      => pll25dac_sclk_o,
      pll25dac_sync_n_o    => pll25dac_sync_n_o,
      sfp_txp_o            => sfp_txp_o,
      sfp_txn_o            => sfp_txn_o,
      sfp_rxp_i            => sfp_rxp_i,
      sfp_rxn_i            => sfp_rxn_i,
      sfp_det_i            => sfp_mod_def0_i,
      sfp_sda_i            => sfp_sda_in,
      sfp_sda_o            => sfp_sda_out,
      sfp_scl_i            => sfp_scl_in,
      sfp_scl_o            => sfp_scl_out,
      sfp_rate_select_o    => sfp_rate_select_o,
      sfp_tx_fault_i       => sfp_tx_fault_i,
      sfp_tx_disable_o     => sfp_tx_disable_o,
      sfp_los_i            => sfp_los_i,
      eeprom_sda_i         => eeprom_sda_in,
      eeprom_sda_o         => eeprom_sda_out,
      eeprom_scl_i         => eeprom_scl_in,
      eeprom_scl_o         => eeprom_scl_out,
      onewire_i            => onewire_data,
      onewire_oen_o        => onewire_oe,
      uart_rxd_i           => uart_rxd_i,
      uart_txd_o           => uart_txd_o,
      spi_sclk_o           => spi_sclk_o,
      spi_ncs_o            => spi_ncs_o,
      spi_mosi_o           => spi_mosi_o,
      spi_miso_i           => spi_miso_i,
      wb_slave_o           => cnx_slave_out(c_WB_SLAVE_WRC),
      wb_slave_i           => cnx_slave_in(c_WB_SLAVE_WRC),

      wrf_src_o            => eth_rx_in,
      wrf_src_i            => eth_rx_out,
      wrf_snk_o            => eth_tx_in,
      wrf_snk_i            => eth_tx_out,

      tm_link_up_o         => tm_link_up,
      tm_time_valid_o      => tm_time_valid,
      tm_tai_o             => tm_tai,
      tm_cycles_o          => tm_cycles,

      tm_dac_value_o       => tm_dac_value,
      tm_dac_wr_o          => tm_dac_wr,
      tm_clk_aux_lock_en_i => tm_clk_aux_lock_en,
      tm_clk_aux_locked_o  => tm_clk_aux_locked,

      pps_p_o              => pps,
      pps_led_o            => pps_led,
      led_link_o           => wr_led_link,
      led_act_o            => wr_led_act,
      link_ok_o            => wrabbit_en);

  -- tri-state Carrier EEPROM
  carrier_sda_b <= '0' when (eeprom_sda_out = '0') else 'Z';
  eeprom_sda_in <= carrier_sda_b;
  carrier_scl_b <= '0' when (eeprom_scl_out = '0') else 'Z';
  eeprom_scl_in <= carrier_scl_b;

  -- Tristates for SFP EEPROM
  sfp_mod_def1_b <= '0' when sfp_scl_out = '0' else 'Z';
  sfp_mod_def2_b <= '0' when sfp_sda_out = '0' else 'Z';
  sfp_scl_in     <= sfp_mod_def1_b;
  sfp_sda_in     <= sfp_mod_def2_b;

  -- tri-state onewire access
  onewire_b    <= '0' when (onewire_oe = '1') else 'Z';
  onewire_data <= onewire_b;

  --  fmc i2c

  fmc0_scl_b     <= '0' when (fmc0_scl_out = '0') else 'Z';
  fmc0_sda_b     <= '0' when (fmc0_sda_out = '0') else 'Z';

  fmc1_scl_b     <= '0' when (fmc1_scl_out = '0') else 'Z';
  fmc1_sda_b     <= '0' when (fmc1_sda_out = '0') else 'Z';

{body}

  -----------------------------------------------------------------------------
  -- Carrier front panel LEDs and LEMOs
  -----------------------------------------------------------------------------

  cmp_led_controller : gc_bicolor_led_ctrl
    generic map(
      g_nb_column    => 4,
      g_nb_line      => 2,
      g_clk_freq     => 62500000,  -- in Hz
      g_refresh_rate => 250        -- in Hz
      )
    port map(
      rst_n_i => rst_sys_62m5_n,
      clk_i   => clk_sys_62m5,

      led_intensity_i => "1100100",  -- in %

      led_state_i => svec_led,

      column_o   => fp_led_column_o,
      line_o     => fp_led_line_o,
      line_oen_o => fp_led_line_oen_o);

  -- LED 1
  svec_led(1 downto 0)   <= c_led_green     when wr_led_link = '1'          else c_led_red;
  -- LED 2
  svec_led(3 downto 2)   <= c_led_green     when tm_clk_aux_locked(0) = '1' else c_led_red;
  -- LED 3
  svec_led(5 downto 4)   <= c_led_green     when tm_time_valid = '1'        else c_led_red;
  -- LED 4
  svec_led(7 downto 6)   <= c_led_red_green when vme_access_led = '1'       else c_led_off;
  -- LED 5
  svec_led(9 downto 8)   <= c_led_red_green when wr_led_act = '1'           else c_led_off;
  -- LED 6
  svec_led(11 downto 10) <= c_led_green     when tm_clk_aux_locked(1) = '1' else c_led_red;
  -- LED 7
  svec_led(13 downto 12) <= c_led_off;
  -- LED 8
  svec_led(15 downto 14) <= c_led_green     when pps_led = '1'              else c_led_off;

  -- Div by 2 reference clock to LEMO connector
  process(clk_ref_125m)
  begin
    if rising_edge(clk_ref_125m) then
      clk_ref_div2 <= not clk_ref_div2;
    end if;
  end process;

  -- Front panel IO configuration
  fp_gpio1_o      <= pps;
  fp_gpio2_o      <= clk_ref_div2;
  clk_ext_ref     <= fp_gpio3_i;
  pps_ext_in      <= fp_gpio4_i;
  fp_term_en_o    <= (others => '0');
  fp_gpio1_a2b_o  <= '1';
  fp_gpio2_a2b_o  <= '1';
  fp_gpio34_a2b_o <= '0';

end architecture arch;
