/*
  Register definitions for slave core: TDC Direct Readout WB Slave

  * File           : fmctdc-direct.h
  * Author         : auto-generated by wbgen2 from fmc_tdc_direct_readout_slave.wb
  * Created        : Thu May 15 14:23:14 2014
  * Standard       : ANSI C

    THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_tdc_direct_readout_slave.wb
    DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!

*/

#ifndef __WBGEN2_REGDEFS_FMC_TDC_DIRECT_READOUT_SLAVE_WB
#define __WBGEN2_REGDEFS_FMC_TDC_DIRECT_READOUT_SLAVE_WB

#include <inttypes.h>

#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif

#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif


/* definitions for register: Channel Enable Register */

/* definitions for register: Dead Time Register */

/* definitions for register: FIFO 'Readout FIFO' data output register 0 */

/* definitions for field: Seconds in reg: FIFO 'Readout FIFO' data output register 0 */
#define DR_FIFO_R0_SECONDS_MASK               WBGEN2_GEN_MASK(0, 32)
#define DR_FIFO_R0_SECONDS_SHIFT              0
#define DR_FIFO_R0_SECONDS_W(value)           WBGEN2_GEN_WRITE(value, 0, 32)
#define DR_FIFO_R0_SECONDS_R(reg)             WBGEN2_GEN_READ(reg, 0, 32)

/* definitions for register: FIFO 'Readout FIFO' data output register 1 */

/* definitions for field: Cycles in reg: FIFO 'Readout FIFO' data output register 1 */
#define DR_FIFO_R1_CYCLES_MASK                WBGEN2_GEN_MASK(0, 32)
#define DR_FIFO_R1_CYCLES_SHIFT               0
#define DR_FIFO_R1_CYCLES_W(value)            WBGEN2_GEN_WRITE(value, 0, 32)
#define DR_FIFO_R1_CYCLES_R(reg)              WBGEN2_GEN_READ(reg, 0, 32)

/* definitions for register: FIFO 'Readout FIFO' data output register 2 */

/* definitions for field: Bins in reg: FIFO 'Readout FIFO' data output register 2 */
#define DR_FIFO_R2_BINS_MASK                  WBGEN2_GEN_MASK(0, 18)
#define DR_FIFO_R2_BINS_SHIFT                 0
#define DR_FIFO_R2_BINS_W(value)              WBGEN2_GEN_WRITE(value, 0, 18)
#define DR_FIFO_R2_BINS_R(reg)                WBGEN2_GEN_READ(reg, 0, 18)

/* definitions for field: Edge in reg: FIFO 'Readout FIFO' data output register 2 */
#define DR_FIFO_R2_EDGE                       WBGEN2_GEN_MASK(18, 1)

/* definitions for field: Channel in reg: FIFO 'Readout FIFO' data output register 2 */
#define DR_FIFO_R2_CHANNEL_MASK               WBGEN2_GEN_MASK(19, 4)
#define DR_FIFO_R2_CHANNEL_SHIFT              19
#define DR_FIFO_R2_CHANNEL_W(value)           WBGEN2_GEN_WRITE(value, 19, 4)
#define DR_FIFO_R2_CHANNEL_R(reg)             WBGEN2_GEN_READ(reg, 19, 4)

/* definitions for register: FIFO 'Readout FIFO' control/status register */

/* definitions for field: FIFO full flag in reg: FIFO 'Readout FIFO' control/status register */
#define DR_FIFO_CSR_FULL                      WBGEN2_GEN_MASK(16, 1)

/* definitions for field: FIFO empty flag in reg: FIFO 'Readout FIFO' control/status register */
#define DR_FIFO_CSR_EMPTY                     WBGEN2_GEN_MASK(17, 1)

/* definitions for field: FIFO counter in reg: FIFO 'Readout FIFO' control/status register */
#define DR_FIFO_CSR_USEDW_MASK                WBGEN2_GEN_MASK(0, 8)
#define DR_FIFO_CSR_USEDW_SHIFT               0
#define DR_FIFO_CSR_USEDW_W(value)            WBGEN2_GEN_WRITE(value, 0, 8)
#define DR_FIFO_CSR_USEDW_R(reg)              WBGEN2_GEN_READ(reg, 0, 8)
/* [0x0]: REG Channel Enable Register */
#define DR_REG_CHAN_ENABLE 0x00000000
/* [0x4]: REG Dead Time Register */
#define DR_REG_DEAD_TIME 0x00000004
/* [0x8]: REG FIFO 'Readout FIFO' data output register 0 */
#define DR_REG_FIFO_R0 0x00000008
/* [0xc]: REG FIFO 'Readout FIFO' data output register 1 */
#define DR_REG_FIFO_R1 0x0000000c
/* [0x10]: REG FIFO 'Readout FIFO' data output register 2 */
#define DR_REG_FIFO_R2 0x00000010
/* [0x14]: REG FIFO 'Readout FIFO' control/status register */
#define DR_REG_FIFO_CSR 0x00000014
#endif
