[use]
use work.fine_delay_pkg.all;
[ports]
    ---------------------------------------------------------------------------
    -- FMC slot {n} pins (FDELAY mezzanine)
    ---------------------------------------------------------------------------

    fmc{n}_fd_tdc_start_p_i : in std_logic;
    fmc{n}_fd_tdc_start_n_i : in std_logic;

    fmc{n}_fd_clk_ref_p_i : in std_logic;
    fmc{n}_fd_clk_ref_n_i : in std_logic;

    fmc{n}_fd_trig_a_i         : in    std_logic;
    fmc{n}_fd_tdc_cal_pulse_o  : out   std_logic;
    fmc{n}_fd_tdc_d_b          : inout std_logic_vector(27 downto 0);
    fmc{n}_fd_tdc_emptyf_i     : in    std_logic;
    fmc{n}_fd_tdc_alutrigger_o : out   std_logic;
    fmc{n}_fd_tdc_wr_n_o       : out   std_logic;
    fmc{n}_fd_tdc_rd_n_o       : out   std_logic;
    fmc{n}_fd_tdc_oe_n_o       : out   std_logic;
    fmc{n}_fd_led_trig_o       : out   std_logic;
    fmc{n}_fd_tdc_start_dis_o  : out   std_logic;
    fmc{n}_fd_tdc_stop_dis_o   : out   std_logic;
    fmc{n}_fd_spi_cs_dac_n_o   : out   std_logic;
    fmc{n}_fd_spi_cs_pll_n_o   : out   std_logic;
    fmc{n}_fd_spi_cs_gpio_n_o  : out   std_logic;
    fmc{n}_fd_spi_sclk_o       : out   std_logic;
    fmc{n}_fd_spi_mosi_o       : out   std_logic;
    fmc{n}_fd_spi_miso_i       : in    std_logic;
    fmc{n}_fd_delay_len_o      : out   std_logic_vector(3 downto 0);
    fmc{n}_fd_delay_val_o      : out   std_logic_vector(9 downto 0);
    fmc{n}_fd_delay_pulse_o    : out   std_logic_vector(3 downto 0);

    fmc{n}_fd_dmtd_clk_o    : out std_logic;
    fmc{n}_fd_dmtd_fb_in_i  : in  std_logic;
    fmc{n}_fd_dmtd_fb_out_i : in  std_logic;

    fmc{n}_fd_pll_status_i : in  std_logic;
    fmc{n}_fd_ext_rst_n_o  : out std_logic;

    fmc{n}_fd_onewire_b : inout std_logic;

[sdb-decl]
[sdb-layout]
    c_WB_SLAVE_FMC{n} => f_sdb_embed_device(c_FD_SDB_DEVICE, x"{addr}"),
[decls]
    -- Muxed Host and MT WB interface to FMC{n}
  signal fmc{n}_mux_wb_out : t_wishbone_master_out;
  signal fmc{n}_mux_wb_in  : t_wishbone_master_in;

  -- Misc FMC signals
  signal fmc{n}_fd_tdc_start  : std_logic;
  signal ddr{n}_pll_reset     : std_logic;
  signal ddr{n}_pll_locked    : std_logic;
  signal fmc{n}_fd_pll_status : std_logic;

  signal fmc{n}_fd_tdc_data_out : std_logic_vector(27 downto 0);
  signal fmc{n}_fd_tdc_data_in  : std_logic_vector(27 downto 0);
  signal fmc{n}_fd_tdc_data_oe  : std_logic;

  signal fmc{n}_fd_owr_en, fmc{n}_fd_owr_in  : std_logic;
  signal fmc{n}_fd_scl_in : std_logic;
  signal fmc{n}_fd_sda_in : std_logic;

  signal fmc{n}_clk_125m_180 : std_logic;

[body]
  -----------------------------------------------------------------------------
  -- FMC FDELAY (SVEC slot #{n})
  -----------------------------------------------------------------------------


  cmp_fd_tdc_start{n} : IBUFDS
    generic map (
      DIFF_TERM    => TRUE,
      IBUF_LOW_PWR => FALSE)
    port map (
      O  => fmc{n}_fd_tdc_start,
      I  => fmc{n}_fd_tdc_start_p_i,
      IB => fmc{n}_fd_tdc_start_n_i);

  U_DDR_PLL1 : entity work.fd_ddr_pll
    port map (
      RST       => ddr{n}_pll_reset,
      LOCKED    => ddr{n}_pll_locked,
      CLK_IN1_P => fmc{n}_fd_clk_ref_p_i,
      CLK_IN1_N => fmc{n}_fd_clk_ref_n_i,
      CLK_OUT1  => fmc{n}_clk_125m,
      CLK_OUT2  => fmc{n}_clk_125m_180);

  ddr{n}_pll_reset     <= not fmc{n}_fd_pll_status_i;
  fmc{n}_fd_pll_status <= fmc{n}_fd_pll_status_i and ddr{n}_pll_locked;

  U_FineDelay_Core{n} : fine_delay_core
    generic map (
      g_with_wr_core        => TRUE,
      g_simulation          => f_int2bool(g_simulation),
      g_interface_mode      => PIPELINED,
      g_address_granularity => BYTE)
    port map (
      clk_ref_0_i          => fmc{n}_clk_125m,
      clk_ref_180_i        => fmc{n}_clk_125m_180,
      clk_sys_i            => clk_sys_62m5,
      clk_dmtd_i           => '0',
      rst_n_i              => rst_sys_62m5_n,
      dcm_reset_o          => open,
      dcm_locked_i         => ddr{n}_pll_locked,
      trig_a_i             => fmc{n}_fd_trig_a_i,
      tdc_cal_pulse_o      => fmc{n}_fd_tdc_cal_pulse_o,
      tdc_start_i          => fmc{n}_fd_tdc_start,
      dmtd_fb_in_i         => fmc{n}_fd_dmtd_fb_in_i,
      dmtd_fb_out_i        => fmc{n}_fd_dmtd_fb_out_i,
      dmtd_samp_o          => fmc{n}_fd_dmtd_clk_o,
      led_trig_o           => fmc{n}_fd_led_trig_o,
      ext_rst_n_o          => fmc{n}_fd_ext_rst_n_o,
      pll_status_i         => fmc{n}_fd_pll_status,
      acam_d_o             => fmc{n}_fd_tdc_data_out,
      acam_d_i             => fmc{n}_fd_tdc_data_in,
      acam_d_oen_o         => fmc{n}_fd_tdc_data_oe,
      acam_emptyf_i        => fmc{n}_fd_tdc_emptyf_i,
      acam_alutrigger_o    => fmc{n}_fd_tdc_alutrigger_o,
      acam_wr_n_o          => fmc{n}_fd_tdc_wr_n_o,
      acam_rd_n_o          => fmc{n}_fd_tdc_rd_n_o,
      acam_start_dis_o     => fmc{n}_fd_tdc_start_dis_o,
      acam_stop_dis_o      => fmc{n}_fd_tdc_stop_dis_o,
      spi_cs_dac_n_o       => fmc{n}_fd_spi_cs_dac_n_o,
      spi_cs_pll_n_o       => fmc{n}_fd_spi_cs_pll_n_o,
      spi_cs_gpio_n_o      => fmc{n}_fd_spi_cs_gpio_n_o,
      spi_sclk_o           => fmc{n}_fd_spi_sclk_o,
      spi_mosi_o           => fmc{n}_fd_spi_mosi_o,
      spi_miso_i           => fmc{n}_fd_spi_miso_i,
      delay_len_o          => fmc{n}_fd_delay_len_o,
      delay_val_o          => fmc{n}_fd_delay_val_o,
      delay_pulse_o        => fmc{n}_fd_delay_pulse_o,
      tm_link_up_i         => tm_link_up,
      tm_time_valid_i      => tm_time_valid,
      tm_cycles_i          => tm_cycles,
      tm_utc_i             => tm_tai,
      tm_clk_aux_lock_en_o => tm_clk_aux_lock_en({n}),
      tm_clk_aux_locked_i  => tm_clk_aux_locked({n}),
      tm_clk_dmtd_locked_i => '1',
      tm_dac_value_i       => tm_dac_value,
      tm_dac_wr_i          => tm_dac_wr({n}),
      owr_en_o             => fmc{n}_fd_owr_en,
      owr_i                => fmc{n}_fd_owr_in,
      i2c_scl_oen_o        => fmc{n}_scl_out,
      i2c_scl_i            => fmc{n}_fd_scl_in,
      i2c_sda_oen_o        => fmc{n}_sda_out,
      i2c_sda_i            => fmc{n}_fd_sda_in,
      fmc_present_n_i      => fmc{n}_prsntm2c_n_i,
      wb_adr_i             => fmc{n}_mux_wb_out.adr,
      wb_dat_i             => fmc{n}_mux_wb_out.dat,
      wb_dat_o             => fmc{n}_mux_wb_in.dat,
      wb_sel_i             => fmc{n}_mux_wb_out.sel,
      wb_cyc_i             => fmc{n}_mux_wb_out.cyc,
      wb_stb_i             => fmc{n}_mux_wb_out.stb,
      wb_we_i              => fmc{n}_mux_wb_out.we,
      wb_ack_o             => fmc{n}_mux_wb_in.ack,
      wb_stall_o           => fmc{n}_mux_wb_in.stall,
      wb_irq_o             => fmc_host_irq({n}));

  cmp_fmc{n}_wb_mux : xwb_crossbar
    generic map (
      g_num_masters => 2,
      g_num_slaves  => 1,
      g_registered  => TRUE,
      g_address     => c_FMC_MUX_ADDR,
      g_mask        => c_FMC_MUX_MASK)
    port map (
      clk_sys_i   => clk_sys_62m5,
      rst_n_i     => rst_sys_62m5_n,
      slave_i(0)  => fmc_dp_wb_out({n}),
      slave_i(1)  => cnx_slave_in(c_WB_SLAVE_FMC{n}),
      slave_o(0)  => fmc_dp_wb_in({n}),
      slave_o(1)  => cnx_slave_out(c_WB_SLAVE_FMC{n}),
      master_i(0) => fmc{n}_mux_wb_in,
      master_o(0) => fmc{n}_mux_wb_out);

  fmc{n}_mux_wb_in.err <= '0';
  fmc{n}_mux_wb_in.rty <= '0';

  -- tristate buffer for the TDC data bus:
  fmc{n}_fd_tdc_d_b     <= fmc{n}_fd_tdc_data_out when fmc{n}_fd_tdc_data_oe = '1' else (others => 'Z');
  fmc{n}_fd_tdc_oe_n_o  <= '1';
  fmc{n}_fd_tdc_data_in <= fmc{n}_fd_tdc_d_b;

  fmc{n}_fd_onewire_b <= '0' when fmc{n}_fd_owr_en = '1' else 'Z';
  fmc{n}_fd_owr_in    <= fmc{n}_fd_onewire_b;

  fmc{n}_fd_scl_in <= fmc{n}_scl_b;
  fmc{n}_fd_sda_in <= fmc{n}_sda_b;
