# DDR1 (bank 5)
NET "ddr_rzq_b[1]"     LOC = G25;
NET "ddr_we_n_o[1]"    LOC = E26;
NET "ddr_udqs_p_b[1]"  LOC = K28;
NET "ddr_udqs_n_b[1]"  LOC = K30;
NET "ddr_udm_o[1]"     LOC = J27;
NET "ddr_reset_n_o[1]" LOC = C26;
NET "ddr_ras_n_o[1]"   LOC = K26;
NET "ddr_odt_o[1]"     LOC = E30;
NET "ddr_ldqs_p_b[1]"  LOC = J29;
NET "ddr_ldqs_n_b[1]"  LOC = J30;
NET "ddr_ldm_o[1]"     LOC = J28;
NET "ddr_cke_o[1]"     LOC = B29;
NET "ddr_ck_p_o[1]"    LOC = E27;
NET "ddr_ck_n_o[1]"    LOC = E28;
NET "ddr_cas_n_o[1]"   LOC = K27;
NET "ddr_dq_b[31]"     LOC = M30;
NET "ddr_dq_b[30]"     LOC = M28;
NET "ddr_dq_b[29]"     LOC = M27;
NET "ddr_dq_b[28]"     LOC = M26;
NET "ddr_dq_b[27]"     LOC = L30;
NET "ddr_dq_b[26]"     LOC = L29;
NET "ddr_dq_b[25]"     LOC = L28;
NET "ddr_dq_b[24]"     LOC = L27;
NET "ddr_dq_b[23]"     LOC = F30;
NET "ddr_dq_b[22]"     LOC = F28;
NET "ddr_dq_b[21]"     LOC = G28;
NET "ddr_dq_b[20]"     LOC = G27;
NET "ddr_dq_b[19]"     LOC = G30;
NET "ddr_dq_b[18]"     LOC = G29;
NET "ddr_dq_b[17]"     LOC = H30;
NET "ddr_dq_b[16]"     LOC = H28;
NET "ddr_ba_o[5]"      LOC = D26;
NET "ddr_ba_o[4]"      LOC = C27;
NET "ddr_ba_o[3]"      LOC = D27;
NET "ddr_a_o[27]"      LOC = A28;
NET "ddr_a_o[26]"      LOC = B30;
NET "ddr_a_o[25]"      LOC = A26;
NET "ddr_a_o[24]"      LOC = F26;
NET "ddr_a_o[23]"      LOC = A27;
NET "ddr_a_o[22]"      LOC = B27;
NET "ddr_a_o[21]"      LOC = C29;
NET "ddr_a_o[20]"      LOC = H27;
NET "ddr_a_o[19]"      LOC = H26;
NET "ddr_a_o[18]"      LOC = F27;
NET "ddr_a_o[17]"      LOC = E29;
NET "ddr_a_o[16]"      LOC = C30;
NET "ddr_a_o[15]"      LOC = D30;
NET "ddr_a_o[14]"      LOC = D28;
