#===============================================================================
# IO Location Constraints
#===============================================================================

#----------------------------------------
# GN4124 interface
#----------------------------------------
NET "gn_rst_n_i"         LOC = N20;
NET "gn_p2l_clk_n_i"     LOC = M19;
NET "gn_p2l_clk_p_i"     LOC = M20;
NET "gn_p2l_rdy_o"       LOC = J16;
NET "gn_p2l_dframe_i"    LOC = J22;
NET "gn_p2l_valid_i"     LOC = L19;
NET "gn_p2l_data_i[15]"  LOC = H19;
NET "gn_p2l_data_i[14]"  LOC = F21;
NET "gn_p2l_data_i[13]"  LOC = F22;
NET "gn_p2l_data_i[12]"  LOC = E20;
NET "gn_p2l_data_i[11]"  LOC = E22;
NET "gn_p2l_data_i[10]"  LOC = J19;
NET "gn_p2l_data_i[9]"   LOC = H20;
NET "gn_p2l_data_i[8]"   LOC = K19;
NET "gn_p2l_data_i[7]"   LOC = K18;
NET "gn_p2l_data_i[6]"   LOC = G20;
NET "gn_p2l_data_i[5]"   LOC = G22;
NET "gn_p2l_data_i[4]"   LOC = K17;
NET "gn_p2l_data_i[3]"   LOC = L17;
NET "gn_p2l_data_i[2]"   LOC = H21;
NET "gn_p2l_data_i[1]"   LOC = H22;
NET "gn_p2l_data_i[0]"   LOC = K20;
NET "gn_p_wr_req_i[1]"   LOC = M21;
NET "gn_p_wr_req_i[0]"   LOC = M22;
NET "gn_p_wr_rdy_o[1]"   LOC = K16;
NET "gn_p_wr_rdy_o[0]"   LOC = L15;
NET "gn_rx_error_o"      LOC = J17;
NET "gn_l2p_clk_n_o"     LOC = K22;
NET "gn_l2p_clk_p_o"     LOC = K21;
NET "gn_l2p_dframe_o"    LOC = U22;
NET "gn_l2p_valid_o"     LOC = T18;
NET "gn_l2p_edb_o"       LOC = U20;
NET "gn_l2p_data_o[15]"  LOC = Y21;
NET "gn_l2p_data_o[14]"  LOC = W20;
NET "gn_l2p_data_o[13]"  LOC = V20;
NET "gn_l2p_data_o[12]"  LOC = V22;
NET "gn_l2p_data_o[11]"  LOC = T19;
NET "gn_l2p_data_o[10]"  LOC = T21;
NET "gn_l2p_data_o[9]"   LOC = R22;
NET "gn_l2p_data_o[8]"   LOC = P22;
NET "gn_l2p_data_o[7]"   LOC = Y22;
NET "gn_l2p_data_o[6]"   LOC = W22;
NET "gn_l2p_data_o[5]"   LOC = V19;
NET "gn_l2p_data_o[4]"   LOC = V21;
NET "gn_l2p_data_o[3]"   LOC = T20;
NET "gn_l2p_data_o[2]"   LOC = P18;
NET "gn_l2p_data_o[1]"   LOC = P21;
NET "gn_l2p_data_o[0]"   LOC = P16;
NET "gn_l2p_rdy_i"       LOC = U19;
NET "gn_l_wr_rdy_i[1]"   LOC = T22;
NET "gn_l_wr_rdy_i[0]"   LOC = R20;
NET "gn_p_rd_d_rdy_i[1]" LOC = P19;
NET "gn_p_rd_d_rdy_i[0]" LOC = N16;
NET "gn_tx_error_i"      LOC = M17;
NET "gn_vc_rdy_i[1]"     LOC = B22;
NET "gn_vc_rdy_i[0]"     LOC = B21;
NET "gn_gpio_b[1]"       LOC = U16;
NET "gn_gpio_b[0]"       LOC = AB19;

NET "gn_rst_n_i"         IOSTANDARD = "LVCMOS18";
NET "gn_p2l_clk_?_i"     IOSTANDARD = "DIFF_SSTL18_I";
NET "gn_p2l_rdy_o"       IOSTANDARD = "SSTL18_I";
NET "gn_p2l_dframe_i"    IOSTANDARD = "SSTL18_I";
NET "gn_p2l_valid_i"     IOSTANDARD = "SSTL18_I";
NET "gn_p2l_data_i[*]"   IOSTANDARD = "SSTL18_I";
NET "gn_p_wr_req_i[*]"   IOSTANDARD = "SSTL18_I";
NET "gn_p_wr_rdy_o[*]"   IOSTANDARD = "SSTL18_I";
NET "gn_rx_error_o"      IOSTANDARD = "SSTL18_I";
NET "gn_l2p_clk_?_o"     IOSTANDARD = "DIFF_SSTL18_I";
NET "gn_l2p_dframe_o"    IOSTANDARD = "SSTL18_I";
NET "gn_l2p_valid_o"     IOSTANDARD = "SSTL18_I";
NET "gn_l2p_edb_o"       IOSTANDARD = "SSTL18_I";
NET "gn_l2p_data_o[*]"   IOSTANDARD = "SSTL18_I";
NET "gn_l2p_rdy_i"       IOSTANDARD = "SSTL18_I";
NET "gn_l_wr_rdy_i[*]"   IOSTANDARD = "SSTL18_I";
NET "gn_p_rd_d_rdy_i[*]" IOSTANDARD = "SSTL18_I";
NET "gn_tx_error_i"      IOSTANDARD = "SSTL18_I";
NET "gn_vc_rdy_i[*]"     IOSTANDARD = "SSTL18_I";
NET "gn_gpio_b[*]"       IOSTANDARD = "LVCMOS25";

#----------------------------------------
# Clock and reset inputs
#----------------------------------------
NET "clk_20m_vcxo_i"      LOC = H12;
NET "clk_125m_pllref_n_i" LOC = F10;
NET "clk_125m_pllref_p_i" LOC = G9;
NET "clk_125m_gtp_n_i"    LOC = D11;
NET "clk_125m_gtp_p_i"    LOC = C11;

NET "clk_20m_vcxo_i"      IOSTANDARD = "LVCMOS25";
NET "clk_125m_pllref_n_i" IOSTANDARD = "LVDS_25";
NET "clk_125m_pllref_p_i" IOSTANDARD = "LVDS_25";
NET "clk_125m_gtp_n_i"    IOSTANDARD = "LVDS_25";
NET "clk_125m_gtp_p_i"    IOSTANDARD = "LVDS_25";

#----------------------------------------
# SFP slot
#----------------------------------------
NET "sfp_rxn_i"         LOC = C15;
NET "sfp_rxp_i"         LOC = D15;
NET "sfp_txn_o"         LOC = A16;
NET "sfp_txp_o"         LOC = B16;
NET "sfp_los_i"         LOC = D18;
NET "sfp_mod_def0_i"    LOC = G15;
NET "sfp_mod_def1_b"    LOC = C17;
NET "sfp_mod_def2_b"    LOC = G16;
NET "sfp_rate_select_o" LOC = H14;
NET "sfp_tx_disable_o"  LOC = F17;
NET "sfp_tx_fault_i"    LOC = B18;

NET "sfp_los_i"         IOSTANDARD = "LVCMOS25";
NET "sfp_mod_def0_i"    IOSTANDARD = "LVCMOS25";
NET "sfp_mod_def1_b"    IOSTANDARD = "LVCMOS25";
NET "sfp_mod_def2_b"    IOSTANDARD = "LVCMOS25";
NET "sfp_rate_select_o" IOSTANDARD = "LVCMOS25";
NET "sfp_tx_disable_o"  IOSTANDARD = "LVCMOS25";
NET "sfp_tx_fault_i"    IOSTANDARD = "LVCMOS25";

#----------------------------------------
# DAC interfaces (for VCXO)
#----------------------------------------
NET "pll25dac_sync_n_o" LOC = A3;
NET "pll20dac_sync_n_o" LOC = B3;
NET "plldac_din_o"      LOC = C4;
NET "plldac_sclk_o"     LOC = A4;

NET "pll25dac_sync_n_o" IOSTANDARD = "LVCMOS25";
NET "pll20dac_sync_n_o" IOSTANDARD = "LVCMOS25";
NET "plldac_din_o"      IOSTANDARD = "LVCMOS25";
NET "plldac_sclk_o"     IOSTANDARD = "LVCMOS25";

#----------------------------------------
# SPI FLASH
#----------------------------------------
NET "spi_ncs_o"  LOC = AA3;
NET "spi_sclk_o" LOC = Y20;
NET "spi_mosi_o" LOC = AB20;
NET "spi_miso_i" LOC = AA20;

NET "spi_ncs_o"  IOSTANDARD = "LVCMOS25";
NET "spi_sclk_o" IOSTANDARD = "LVCMOS25";
NET "spi_mosi_o" IOSTANDARD = "LVCMOS25";
NET "spi_miso_i" IOSTANDARD = "LVCMOS25";

#----------------------------------------
# UART
#----------------------------------------
NET "uart_txd_o" LOC = B2;
NET "uart_rxd_i" LOC = A2;

NET "uart_txd_o" IOSTANDARD = "LVCMOS25";
NET "uart_rxd_i" IOSTANDARD = "LVCMOS25";

#----------------------------------------
# 1-wire thermometer + unique ID
#----------------------------------------
NET "carrier_onewire_b" LOC = D4;

NET "carrier_onewire_b" IOSTANDARD = "LVCMOS25";

#----------------------------------------
# Carrier front panel LEDs
#----------------------------------------
NET "led_sfp_red_o"   LOC = D5;
NET "led_sfp_green_o" LOC = E5;

NET "led_sfp_red_o"   IOSTANDARD = "LVCMOS25";
NET "led_sfp_green_o" IOSTANDARD = "LVCMOS25";

#----------------------------------------
# PCB revision
#----------------------------------------
NET "pcbrev_i[0]" LOC = P5;
NET "pcbrev_i[1]" LOC = P4;
NET "pcbrev_i[2]" LOC = AA2;
NET "pcbrev_i[3]" LOC = AA1;

NET "pcbrev_i[*]" IOSTANDARD = "LVCMOS15";

#----------------------------------------
# PCB Buttons and LEDs
#----------------------------------------
NET "button1_n_i"   LOC = C22;
NET "aux_leds_o[0]" LOC = G19;
NET "aux_leds_o[1]" LOC = F20;
NET "aux_leds_o[2]" LOC = F18;
NET "aux_leds_o[3]" LOC = C20;

NET "button1_n_i"   IOSTANDARD = "LVCMOS18";
NET "aux_leds_o[*]" IOSTANDARD = "LVCMOS18";

#----------------------------------------
# FMC slot management
#----------------------------------------
NET "fmc0_prsnt_m2c_n_i" LOC = AB14;
NET "fmc0_scl_b"         LOC = F7;
NET "fmc0_sda_b"         LOC = F8;

NET "fmc0_prsnt_m2c_n_i" IOSTANDARD = "LVCMOS25";
NET "fmc0_scl_b"         IOSTANDARD = "LVCMOS25";
NET "fmc0_sda_b"         IOSTANDARD = "LVCMOS25";

#----------------------------------------
# IOBs
#----------------------------------------

INST "cmp_gn4124_core/cmp_wrapped_gn4124/l2p_rdy_t"   IOB = FALSE;
INST "cmp_gn4124_core/cmp_wrapped_gn4124/l_wr_rdy_t*" IOB = FALSE;

#===============================================================================
# Timing constraints and exceptions
#===============================================================================

# All input clocks

NET "clk_125m_pllref_n_i" TNM_NET = clk_125m_pllref_n_i;
TIMESPEC TS_clk_125m_pllref_n_i = PERIOD "clk_125m_pllref_n_i" 8 ns HIGH 50%;

NET "clk_125m_gtp_n_i" TNM_NET = clk_125m_gtp_n_i;
TIMESPEC TS_clk_125m_gtp_n_i = PERIOD "clk_125m_gtp_n_i" 8 ns HIGH 50%;

NET "clk_20m_vcxo_i" TNM_NET = "clk_20m_vcxo_i";
TIMESPEC TS_clk_20m_vcxo_i = PERIOD "clk_20m_vcxo_i" 50 ns HIGH 50%;

NET "cmp_xwrc_board_spec/*/gen_phy_spartan6.cmp_gtp/ch1_gtp_clkout_int<1>" TNM_NET = wrc_gtp_clk;
TIMESPEC TS_wrc_gtp_clk = PERIOD "wrc_gtp_clk" 8 ns HIGH 50%;

NET "gn_p2l_clk_n_i" TNM_NET = "p2l_clk";
TIMESPEC TS_p2l_clk = PERIOD "p2l_clk" 5 ns HIGH 50%;

#----------------------------------------
# WR DMTD tweaks
#----------------------------------------

INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds*/clk_in" TNM = skew_limit;
INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds*/clk_in"      TNM = skew_limit;

TIMESPEC TS_dmtd_skew = FROM "skew_limit" TO "FFS" 1 ns DATAPATHONLY;

#----------------------------------------
# Asynchronous resets
#----------------------------------------

# GN4124
NET "gn_rst_n_i" TIG;
NET "cmp_gn4124_core/cmp_wrapped_gn4124/rst_*" TIG;

# Ignore async reset inputs to reset synchronisers
NET "*/gc_reset_async_in" TIG;

#----------------------------------------
# Cross-clock domain sync
#----------------------------------------

# Declaration of domains
NET "clk_sys_62m5"                             TNM_NET = sys_clk_62_5;
NET "clk_ref_125m"                             TNM_NET = clk_125m_pllref;
NET "clk_ddr_333m"                             TNM_NET = ddr_clk_333m;
NET "cmp_xwrc_board_spec/clk_pll_dmtd"         TNM_NET = clk_dmtd;
NET "cmp_xwrc_board_spec/phy8_to_wrc_rx_clk"   TNM_NET = phy_clk;
NET "cmp_gn4124_core/cmp_wrapped_gn4124/sys_clk" TNM_NET = pci_sys_clk;
NET "cmp_gn4124_core/cmp_wrapped_gn4124/io_clk"  TNM_NET = pci_io_clk;

TIMEGRP "sys_clk" = "sys_clk_62_5" "clk_125m_pllref";
TIMEGRP "pci_clk" = "pci_sys_clk"  "pci_io_clk";

# Exceptions for crossings via gc_sync_ffs
NET "*/gc_sync_ffs_in" TNM_NET = "sync_ffs";

TIMEGRP "pci_sync_ffs"  = "sync_ffs" EXCEPT "pci_clk";
TIMEGRP "sys_sync_ffs"  = "sync_ffs" EXCEPT "sys_clk";
TIMEGRP "dmtd_sync_ffs" = "sync_ffs" EXCEPT "clk_dmtd";
TIMEGRP "phy_sync_ffs"  = "sync_ffs" EXCEPT "phy_clk";

TIMESPEC TS_pci_sync_ffs  = FROM pci_clk  TO "pci_sync_ffs"  TIG;
TIMESPEC TS_sys_sync_ffs  = FROM sys_clk   TO "sys_sync_ffs"  TIG;
TIMESPEC TS_dmtd_sync_ffs = FROM clk_dmtd  TO "dmtd_sync_ffs" TIG;
TIMESPEC TS_phy_sync_ffs  = FROM phy_clk   TO "phy_sync_ffs"  TIG;

# Exceptions for crossings via gc_sync_register
NET "*/gc_sync_register_in[*]" TNM_NET = "sync_reg";

TIMEGRP "pci_sync_reg"  = "sync_reg" EXCEPT "pci_clk";
TIMEGRP "sys_sync_reg"  = "sync_reg" EXCEPT "sys_clk";
TIMEGRP "dmtd_sync_reg" = "sync_reg" EXCEPT "clk_dmtd";
TIMEGRP "phy_sync_reg"  = "sync_reg" EXCEPT "phy_clk";

TIMESPEC TS_pci_sync_reg      = FROM pci_clk         TO "pci_sync_reg"  5ns  DATAPATHONLY;
TIMESPEC TS_sys_62m5_sync_reg = FROM sys_clk_62_5    TO "sys_sync_reg"  16ns DATAPATHONLY;
TIMESPEC TS_sys_125m_sync_reg = FROM clk_125m_pllref TO "sys_sync_reg"  8ns  DATAPATHONLY;
TIMESPEC TS_dmtd_sync_reg     = FROM clk_dmtd        TO "dmtd_sync_reg" 16ns DATAPATHONLY;
TIMESPEC TS_phy_sync_reg      = FROM phy_clk         TO "phy_sync_reg"  8ns  DATAPATHONLY;
