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WRS Low Jitter Daughterboard
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Layout review

Last edited by Mattia Rizzi Nov 21, 2016
Page history

Layout review 21/11/2016

Files for the review: https://edms.cern.ch/edmsui/nav/EDA-03530-V1-0

Presents

Van der Bij Erik (BE/CO), Wlostowski Tomasz (BE/CO), Calvo Giraldo Eva (BE/CO), Daniluk Grzegorz (BE/CO), Van der Bij Erik (BE/CO), Lampridis Dimitrios (BE/CO), Gousiou Evangelia (BE/CO), Lipinski Maciej (BE/CO)

Comments on the layout

  • Errata Project silkscreen name (Motherboard instead of Daughterboard)
  • Same order of the IDx lines on both table and jumpers
  • Connect mounting holes to ground
  • Remove polygon copper pour on top (antenna problems)
  • R11 too close to the mounting holes
  • Thermal dissipation of the LDO and DC/DC: add vias on the thermal pad

21 November 2016

Files

  • EDA-03530-V1-0_pcb_1_.pdf
  • EDA-03530-V1-0_project_1_.zip
  • EDA-03530-V1-0_sch_1_.pdf
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