Project description
The aim of the board is to improve the jitter performance of the 10 MHz and PPS outputs of WR Switch using an external PLL and a new VCTCXO. This project is a spin-off of the general WR low jitter project: https://www.ohwr.org/project/wr-low-jitter/wiki
The board needs to be mounted inside an existing WR-S3/18 switch, on top of the Switch Control Board (SCB) and will use the installed 12V power supply of the WRS. It needs a new external 10 MHz input, to be used instead of the current 10 MHz input when configured as Grand Master. The improvements are also effective when configured as boundary switch, thanks to the new VCTCXO.
The proposed board can be installed in any PCB v3.3 and v3.4 versions of the switch.
Image of the board:
Main Features
- 10 MHz input clock for GrandMaster operation
- wide input power range, from -10 dBm to 20 dBm, sinewave or square
- AD9516-4 low noise PLL for clock synthetization
- Low jitter VCTCXO, option to install another oscillator (14x9mm
footprint)
- Connor-Winfield DOT050 VCTCXO (default mounted)
- Abracom ABLNO VCTCXO
- Crystek CCHD-950 VCTCXO
- IQOV-162-3 OCXO (CMOS output)
- 16-bit DAC AD5662 to control the oscillator (used by White Rabbit PTP core)
Project Information
- Hardware: see EDMS (CERN Electronic Document Management System) document EDA-03530-V1-0
- Performance of the new board
- Frequently Asked Questions
- Gateware and software (download and building)
- Mounting instructions
- Reviews
- Schematics-review 26/10/2016
- Layout-review 21/11/2016
Contacts
Commercial producers
General question about project
- Mattia Rizzi - CERN
- Erik van der Bij - CERN
Status
Date | Event |
23-10-2016 | Preliminary version of the Schematics ready for review |
26-10-2016 | Schematics-review |
21-11-2016 | Layout-Review |
09-12-2016 | Got the boards |
11-12-2016 | Board fully tested |
16-12-2016 | Software & Gateware ready |
26-12-2016 | Experimental results, mounting and building instructions |
Mattia Rizzi - 26 December 2016