dev/endpoint: hold the PHY in LONG reset during startup to ensure the WRS calclates the PHY bitstlide correctly.

Temporary workaround for the bug in the WR Switch (wr-switch-sw#243).

- detailed Aux clock status
- RX error count

dev: factor out WDIAGS code from SYSCON into a separate file. Implement accessor function for new diagnostic fields

softpll: rename the 'source tracking' mode to 'phase monitor', as it simply monitors the phases of the external (aux clocks) to the local WR clock

This patchset removes the cli dependency on copy/pasted magic numbers
coming from different .h files.

We need the solibs ready before the ErtmTest class declaration
(actually, before most struct declarations) to make available
the magic constants from the libs without duplicated assignments

In particular: aiming at using acc-py is not worth the ticket.
The self-contained venv, based on system Python and a local copy of
pyserial, builds less dependencies and nicely handles the dependency on
pyserial. No need to add headaches to a simple test program.

This disposes of the re-reading of cached values of latency, which is
just another configuration paramenter

This reverts commit b8694a13.

This reverts commit 1fcefe06.

This implements the setting of streamers latencies. The API and
semantics need to be clarified and the "experiment" of doing the read
back of latencies directly from diag regs assessed or supressed.