Commits · proposed_master · Projects / Software for White Rabbit PTP Core · Open Hardware Repository

22 Aug, 2018 1 commit
- sim: enable time_valid_o only when the link is up · 8ff9e3ea
  Grzegorz Daniluk authored Aug 22, 2018
  
  8ff9e3ea
26 Jun, 2017 1 commit
- wrc_main_sim: remove warnings · 7f02a3e0
  Adam Wujek authored Jun 26, 2017
```
Signed-off-by: Adam Wujek <adam.wujek@cern.ch>
```
  7f02a3e0
21 Jun, 2017 1 commit
- sim main: disable discovery of peripherals via SDB to speed-up the simulation. · 7d366a33
  Dimitris Lampridis authored Jun 19, 2017
  
  7d366a33
27 Feb, 2017 3 commits
- [tb/wrpc] updated test_1() to return OK/ERROR to the testbench · 02d430f1
  Maciej Lipinski authored Feb 24, 2017
  
  02d430f1
- [tb/wrpc] added "null" test when test_num=0 (no test specified) · 25a0100b
  Maciej Lipinski authored Feb 24, 2017
```
for some simulations, we just need link-up, so wrpc to initialize
and then loop endlessly, this should be the default behaviour
```
  25a0100b
- [tb/wrpc] enable PPS on initialization - useful for testbenches (e.g. Btrain) · b73b27f8
  Maciej Lipinski authored Feb 24, 2017
  
  b73b27f8
24 Feb, 2017 1 commit
- arch/lm32: add a pointer to hdl_testbench structure in crt0.S · 5fc4dfc3
  Adam Wujek authored Feb 23, 2017
```
Signed-off-by: Adam Wujek <adam.wujek@cern.ch>
```
  5fc4dfc3
23 Feb, 2017 5 commits
- wrpc sim: missing pl_cnt assignment · 3ea94d74
  Grzegorz Daniluk authored Feb 14, 2017
  
  3ea94d74
- wrc simulation: fix indentation to make checkpatch happy · bf1916f1
  Grzegorz Daniluk authored Feb 14, 2017
  
  bf1916f1
- [tb/wrpc] added comments to the new wrc_main_sim file · bd16ce1e
  Maciej Lipinski authored Feb 13, 2017
  
  bd16ce1e
- [tb/wrpc] add test_1 (for wrpc) to the wrc_main_sim code for simulation · 19789c08
  Maciej Lipinski authored Feb 03, 2017
  
  19789c08
- [tb/wrpc] for modelsim simulation · e31f3745
  Maciej Lipinski authored Feb 03, 2017
  
  e31f3745