Commit e38409da authored by Grzegorz Daniluk's avatar Grzegorz Daniluk Committed by Alessandro Rubini

spll: reset ppsgen only once, not every time the spll mode is changed

Otherwise we have a race condition with wr_date setting initial time on the
switch.
parent d769d02c
......@@ -272,6 +272,12 @@ void _irq_entry()
clear_irq();
}
void spll_very_init()
{
PPSG = (volatile struct PPSG_WB *)BASE_PPS_GEN;
PPSG->CR = PPSG_CR_CNT_EN | PPSG_CR_CNT_RST | PPSG_CR_PWIDTH_W(PPS_WIDTH);
}
void spll_init(int mode, int slave_ref_channel, int align_pps)
{
static const char *modes[] = { "", "grandmaster", "freemaster", "slave", "disabled" };
......@@ -304,7 +310,7 @@ void spll_init(int mode, int slave_ref_channel, int align_pps)
SPLL->DEGLITCH_THR = 1000;
PPSG->ESCR = 0;
PPSG->CR = PPSG_CR_CNT_EN | PPSG_CR_CNT_RST | PPSG_CR_PWIDTH_W(PPS_WIDTH);
PPSG->CR = PPSG_CR_CNT_EN | PPSG_CR_PWIDTH_W(PPS_WIDTH);
if(mode == SPLL_MODE_DISABLED)
s->seq_state = SEQ_DISABLED;
......
......@@ -60,6 +60,7 @@ Initializes the SoftPLL to work in mode (mode). Extra parameters depend on choic
- for SPLL_MODE_SLAVE: (ref_channel) indicates the reference channel to which we are locking our PLL.
*/
void spll_init(int mode, int ref_channel, int align_pps);
void spll_very_init();
/* Disables the SoftPLL and cleans up stuff */
void spll_shutdown();
......
......@@ -92,6 +92,7 @@ static void wrc_initialize()
wrc_ptp_init();
//try reading t24 phase transition from EEPROM
calib_t24p(WRC_MODE_MASTER, &cal_phase_transition);
spll_very_init();
#ifdef CONFIG_ETHERBONE
ipv4_init("wru1");
......
......@@ -41,6 +41,7 @@ int main(void)
ad9516_init(scb_ver);
rts_init();
rtipc_init();
spll_very_init();
for(;;)
{
......
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