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Software for White Rabbit PTP Core
Commit c9f262fd authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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device drivers: added extra comments

parent f592ebfd
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dev/endpoint.c
View file @ c9f262fd
/*
WR Endpoint (WR-compatible Ethernet MAC driver
Tomasz Wlostowski/CERN 2011
LGPL 2.1
*/
#include <stdio.h> #include <stdio.h>
#include "board.h" #include "board.h"
...@@ -6,150 +16,165 @@ ...@@ -6,150 +16,165 @@
#include <hw/endpoint_regs.h> #include <hw/endpoint_regs.h>
#include <hw/endpoint_mdio.h> #include <hw/endpoint_mdio.h>
#define UIS_PER_SERIAL_BIT 800
/* Length of a single bit on the gigabit serial link in picoseconds. Used for calculating deltaRx/deltaTx
from the serdes bitslip value */
#define PICOS_PER_SERIAL_BIT 800
/* Number of raw phase samples averaged by the DMTD detector in the Endpoint during single phase measurement.
The bigger, the better precision, but slower rate */
#define DMTD_AVG_SAMPLES 256 #define DMTD_AVG_SAMPLES 256
static int autoneg_enabled; static int autoneg_enabled;
static volatile struct EP_WB *EP = (volatile struct EP_WB *) BASE_EP; static volatile struct EP_WB *EP = (volatile struct EP_WB *) BASE_EP;
/* functions for accessing PCS registers */ /* functions for accessing PCS (MDIO) registers */
static uint16_t pcs_read(int location) static uint16_t pcs_read(int location)
{ {
EP->MDIO_CR = EP_MDIO_CR_ADDR_W(location >> 2); EP->MDIO_CR = EP_MDIO_CR_ADDR_W(location >> 2);
while ((EP->MDIO_ASR & EP_MDIO_ASR_READY) == 0); while ((EP->MDIO_ASR & EP_MDIO_ASR_READY) == 0);
return EP_MDIO_ASR_RDATA_R(EP->MDIO_ASR) & 0xffff; return EP_MDIO_ASR_RDATA_R(EP->MDIO_ASR) & 0xffff;
} }
static void pcs_write(int location, static void pcs_write(int location, int value)
int value)
{ {
EP->MDIO_CR = EP_MDIO_CR_ADDR_W(location >> 2) EP->MDIO_CR = EP_MDIO_CR_ADDR_W(location >> 2)
| EP_MDIO_CR_DATA_W(value) | EP_MDIO_CR_DATA_W(value)
| EP_MDIO_CR_RW; | EP_MDIO_CR_RW;
while ((EP->MDIO_ASR & EP_MDIO_ASR_READY) == 0); while ((EP->MDIO_ASR & EP_MDIO_ASR_READY) == 0);
} }
/* MAC address setting */
static void set_mac_addr(uint8_t dev_addr[]) static void set_mac_addr(uint8_t dev_addr[])
{ {
EP->MACL = ((uint32_t)dev_addr[2] << 24) EP->MACL = ((uint32_t)dev_addr[2] << 24)
| ((uint32_t)dev_addr[3] << 16) | ((uint32_t)dev_addr[3] << 16)
| ((uint32_t)dev_addr[4] << 8) | ((uint32_t)dev_addr[4] << 8)
| ((uint32_t)dev_addr[5]); | ((uint32_t)dev_addr[5]);
EP->MACH = ((uint32_t)dev_addr[0] << 8) EP->MACH = ((uint32_t)dev_addr[0] << 8)
| ((uint32_t)dev_addr[1]); | ((uint32_t)dev_addr[1]);
} }
void get_mac_addr(uint8_t dev_addr[]) void get_mac_addr(uint8_t dev_addr[])
{ {
dev_addr[5] = (EP->MACL & 0x000000ff); dev_addr[5] = (EP->MACL & 0x000000ff);
dev_addr[4] = (EP->MACL & 0x0000ff00) >> 8; dev_addr[4] = (EP->MACL & 0x0000ff00) >> 8;
dev_addr[3] = (EP->MACL & 0x00ff0000) >> 16; dev_addr[3] = (EP->MACL & 0x00ff0000) >> 16;
dev_addr[2] = (EP->MACL & 0xff000000) >> 24; dev_addr[2] = (EP->MACL & 0xff000000) >> 24;
dev_addr[1] = (EP->MACH & 0x000000ff); dev_addr[1] = (EP->MACH & 0x000000ff);
dev_addr[0] = (EP->MACH & 0x0000ff00) >> 8; dev_addr[0] = (EP->MACH & 0x0000ff00) >> 8;
} }
/* Initializes the endpoint and sets its local MAC address */
void ep_init(uint8_t mac_addr[]) void ep_init(uint8_t mac_addr[])
{ {
int i; set_mac_addr(mac_addr);
set_mac_addr(mac_addr);
*(unsigned int *)(0x62000) = 0x2; // reset network stuff (cleanup required!)
*(unsigned int *)(0x62000) = 0x2; // reset network stuff (cleanup!) *(unsigned int *)(0x62000) = 0;
*(unsigned int *)(0x62000) = 0;
EP->ECR = 0; /* disable Endpoint */
EP->VCR0 = EP_VCR0_QMODE_W(3); /* disable VLAN unit - not used by WRPC */
EP->ECR = 0; EP->RFCR = EP_RFCR_MRU_W(1518); /* Set the max RX packet size */
EP->VCR0 = EP_VCR0_QMODE_W(3); // disable VLAN unit EP->TSCR = EP_TSCR_EN_TXTS | EP_TSCR_EN_RXTS; /* Enable timestamping */
EP->RFCR = EP_RFCR_MRU_W(1518);
EP->TSCR = EP_TSCR_EN_TXTS | EP_TSCR_EN_RXTS; /* Configure DMTD phase tracking */
EP->DMCR = EP_DMCR_EN | EP_DMCR_N_AVG_W(DMTD_AVG_SAMPLES); EP->DMCR = EP_DMCR_EN | EP_DMCR_N_AVG_W(DMTD_AVG_SAMPLES);
} }
/* Enables/disables transmission and reception. When autoneg is set to 1,
starts up 802.3 autonegotiation process */
int ep_enable(int enabled, int autoneg) int ep_enable(int enabled, int autoneg)
{ {
uint16_t mcr; uint16_t mcr;
if(!enabled) if(!enabled)
{ {
EP->ECR = 0; EP->ECR = 0;
return; return;
} }
EP->ECR = 0; /* Disable the endpoint */
pfilter_init_default(); EP->ECR = 0;
EP->ECR = EP_ECR_TX_EN | EP_ECR_RX_EN | EP_ECR_RST_CNT;
/* Load default packet classifier rules - see ep_pfilter.c for details */
autoneg_enabled = autoneg; pfilter_init_default();
#if 1
pcs_write(MDIO_REG_MCR, MDIO_MCR_PDOWN); /* reset the PHY */ /* Enable TX/RX paths, reset RMON counters */
timer_delay(2000); EP->ECR = EP_ECR_TX_EN | EP_ECR_RX_EN | EP_ECR_RST_CNT;
pcs_write(MDIO_REG_MCR, MDIO_MCR_RESET); /* reset the PHY */
pcs_write(MDIO_REG_MCR, 0); /* reset the PHY */ autoneg_enabled = autoneg;
#endif
/* Reset the GTP Transceiver - it's important to do the GTP phase alignment every time
pcs_write(MDIO_REG_ADVERTISE, 0); we start up the software, otherwise the calibration RX/TX deltas may not be correct */
pcs_write(MDIO_REG_MCR, MDIO_MCR_PDOWN); /* reset the PHY */
mcr = MDIO_MCR_SPEED1000_MASK | MDIO_MCR_FULLDPLX_MASK; timer_delay(200);
if(autoneg) pcs_write(MDIO_REG_MCR, MDIO_MCR_RESET); /* reset the PHY */
mcr |= MDIO_MCR_ANENABLE | MDIO_MCR_ANRESTART; pcs_write(MDIO_REG_MCR, 0); /* reset the PHY */
/* Don't advertise anything - we don't want flow control */
pcs_write(MDIO_REG_MCR, mcr); pcs_write(MDIO_REG_ADVERTISE, 0);
mcr = MDIO_MCR_SPEED1000_MASK | MDIO_MCR_FULLDPLX_MASK;
if(autoneg)
mcr |= MDIO_MCR_ANENABLE | MDIO_MCR_ANRESTART;
pcs_write(MDIO_REG_MCR, mcr);
return 0;
} }
/* Checks the link status. If the link is up, returns non-zero
and stores the Link Partner Ability (LPA) autonegotiation register at *lpa */
int ep_link_up(uint16_t *lpa) int ep_link_up(uint16_t *lpa)
{ {
uint16_t flags = MDIO_MSR_LSTATUS; uint16_t flags = MDIO_MSR_LSTATUS;
volatile uint16_t msr; volatile uint16_t msr;
if(autoneg_enabled)
flags |= MDIO_MSR_ANEGCOMPLETE;
if(autoneg_enabled)
flags |= MDIO_MSR_ANEGCOMPLETE;
msr = pcs_read(MDIO_REG_MSR); msr = pcs_read(MDIO_REG_MSR);
msr = pcs_read(MDIO_REG_MSR); msr = pcs_read(MDIO_REG_MSR); /* Read this flag twice to make sure the status is updated */
if(lpa) *lpa = pcs_read(MDIO_REG_LPA); if(lpa) *lpa = pcs_read(MDIO_REG_LPA);
return (msr & flags) == flags ? 1 : 0; return (msr & flags) == flags ? 1 : 0;
} }
/* Returns the TX/RX latencies. They are valid only when the link is up. */
int ep_get_deltas(uint32_t *delta_tx, uint32_t *delta_rx) int ep_get_deltas(uint32_t *delta_tx, uint32_t *delta_rx)
{ {
// mprintf("called ep_get_deltas()\n"); /* fixme: these values should be stored in calibration block in the EEPROM on the FMC. Also, the TX/RX delays of a particular SFP
should be added here */
*delta_tx = 0; *delta_tx = 0;
*delta_rx = 15000 - 7000 + 195000 + 32000 + UIS_PER_SERIAL_BIT * MDIO_WR_SPEC_BSLIDE_R(pcs_read(MDIO_REG_WR_SPEC)) + 2800 - 9000; *delta_rx = 15000 - 7000 + 195000 + 32000 + PICOS_PER_SERIAL_BIT * MDIO_WR_SPEC_BSLIDE_R(pcs_read(MDIO_REG_WR_SPEC)) + 2800 - 9000 - 40000 + 2700;
return 0;
} }
/* Prints out the RMON statistic counters */
void ep_show_counters() void ep_show_counters()
{ {
int i; int i;
for(i=0;i<16;i++) for(i=0;i<16;i++)
TRACE_DEV("cntr%d = %d\n", i, EP->RMON_RAM[i]); TRACE_DEV("cntr%d = %d\n", i, EP->RMON_RAM[i]);
} }
int ep_get_psval(int32_t *psval) int ep_get_psval(int32_t *psval)
{ {
uint32_t val; uint32_t val;
val = EP->DMSR;
if(val & EP_DMSR_PS_RDY)
*psval = EP_DMSR_PS_VAL_R(val);
else
*psval = 0;
val = EP->DMSR; return val & EP_DMSR_PS_RDY ? 1 : 0;
if(val & EP_DMSR_PS_RDY)
*psval = EP_DMSR_PS_VAL_R(val);
else
*psval = 0;
// mprintf("**** PhaseVal: %d\n", *psval);
return val & EP_DMSR_PS_RDY ? 1 : 0;
} }
int ep_cal_pattern_enable() int ep_cal_pattern_enable()
......
dev/ep_pfilter.c
View file @ c9f262fd
...@@ -30,12 +30,12 @@ ...@@ -30,12 +30,12 @@
will compare the 3rd word of the packet (bytes 6, 7) against 0xcafe and if the words are equal, will compare the 3rd word of the packet (bytes 6, 7) against 0xcafe and if the words are equal,
1 will be written to Rd register. 1 will be written to Rd register.
* CMP 4, 0xbabe, 0xffff, MOV, Rd * CMP 4, 0xbabe, 0xffff, AND, Rd
will do the same with the 4th word and write to Rd its previous value ANDed with the result will do the same with the 4th word and write to Rd its previous value ANDed with the result
of the comparison. Effectively, Rd now will be 1 only if bytes [6..9] of the payload contain word of the comparison. Effectively, Rd now will be 1 only if bytes [6..9] of the payload contain word
0xcafebabe. 0xcafebabe.
Note that the mask value is nibble-granular. Thet means you can choose a particular Note that the mask value is nibble-granular. That means you can choose a particular
set of nibbles within a word to be compared, but not an arbitrary set of bits (e.g. 0xf00f, 0xff00 set of nibbles within a word to be compared, but not an arbitrary set of bits (e.g. 0xf00f, 0xff00
and 0xf0f0 masks are ok, but 0x8001 is wrong. and 0xf0f0 masks are ok, but 0x8001 is wrong.
...@@ -63,8 +63,8 @@ ...@@ -63,8 +63,8 @@
IMPORTANT: IMPORTANT:
- the program counter is advanved each time a 16-bit words of the packet arrives. - the program counter is advanved each time a 16-bit words of the packet arrives.
- the CPU doesn't have any interlocks to simplify the HW. That means that you can't compare a - the CPU doesn't have any interlocks to simplify the HW, so you can't compare the
10rd word when PC = 2. Max comparison offset is always equal to the address of the instruction. 10th word when PC = 2. Max comparison offset is always equal to the address of the instruction.
- Code may contain up to 64 operations, but it must classify shorter packets faster than in - Code may contain up to 64 operations, but it must classify shorter packets faster than in
32 instructions (there's no flow throttling) 32 instructions (there's no flow throttling)
*/ */
......
dev/softpll.c
View file @ c9f262fd
...@@ -218,8 +218,8 @@ void main_init(struct spll_dmpll_state *s) ...@@ -218,8 +218,8 @@ void main_init(struct spll_dmpll_state *s)
/* Phase branch PI controller */ /* Phase branch PI controller */
s->pi_phase.y_min = 5; s->pi_phase.y_min = 5;
s->pi_phase.y_max = 65530; s->pi_phase.y_max = 65530;
s->pi_phase.kp = 1304; s->pi_phase.kp = 1304 / 2;
s->pi_phase.ki = 10; s->pi_phase.ki = 10 * 3;
s->pi_phase.anti_windup = 0; s->pi_phase.anti_windup = 0;
s->pi_phase.bias = 32000; s->pi_phase.bias = 32000;
...@@ -443,7 +443,7 @@ void softpll_enable() ...@@ -443,7 +443,7 @@ void softpll_enable()
main_init(&auxpll); main_init(&auxpll);
SPLL->DAC_HPLL = 0; SPLL->DAC_HPLL = 0;
SPLL->DEGLITCH_THR = 2000; SPLL->DEGLITCH_THR = 3000;
SPLL->CSR = SPLL_CSR_TAG_EN_W(CHAN_PERIOD); SPLL->CSR = SPLL_CSR_TAG_EN_W(CHAN_PERIOD);
SPLL->EIC_IER = 1; SPLL->EIC_IER = 1;
...@@ -455,17 +455,6 @@ void softpll_enable() ...@@ -455,17 +455,6 @@ void softpll_enable()
} }
void test_aux()
{
for(;;)
{ SPLL->DAC_AUX = 0;
timer_delay(100);
SPLL->DAC_AUX = 65500;
timer_delay(100);
mprintf(".");
}
}
int softpll_check_lock() int softpll_check_lock()
{ {
...@@ -473,7 +462,8 @@ int softpll_check_lock() ...@@ -473,7 +462,8 @@ int softpll_check_lock()
int lck = !helper.freq_mode && helper.ld_phase.locked && !main.freq_mode && main.ld_phase.locked; int lck = !helper.freq_mode && helper.ld_phase.locked && !main.freq_mode && main.ld_phase.locked;
// if(!lck) // if(!lck)
TRACE_DEV("%d %d%d%d%d%d%d\n", irq_cnt, helper.freq_mode, helper.ld_phase.locked, main.freq_mode, main.ld_phase.locked, auxpll.freq_mode, auxpll.ld_phase.locked) ; TRACE_DEV("%d %d%d%d%d%d%d %d %d %d\n", irq_cnt, helper.freq_mode, helper.ld_phase.locked, main.freq_mode, main.ld_phase.locked, auxpll.freq_mode, auxpll.ld_phase.locked, main.pi_freq.y, main.pi_phase.y, main.pi_phase.x);
irq_cnt = 0;
if(lck && !prev_lck) { if(lck && !prev_lck) {
TRACE_DEV("[softpll]: got lock\n"); TRACE_DEV("[softpll]: got lock\n");
......
monitor/wr_mon.c deleted 100644 → 0
View file @ f592ebfd
#include <stdio.h>
#include <stdlib.h>
#include <wr_ipc.h>
#include "term.h"
#include "ptpd_exports.h"
#include "hal_client.h"
hexp_port_list_t port_list;
wripc_handle_t h_ptp;
void init()
{
halexp_client_init();
if( (h_ptp = wripc_connect("ptpd")) < 0)
{
fprintf(stderr,"Can't establish WRIPC connection to the PTP daemon!\n");
exit(-1);
}
term_init();
halexp_query_ports(&port_list);
}
void show_ports()
{
int i;
term_pcprintf(3, 1, C_BLUE, "Switch ports:");
for(i=0; i<port_list.num_ports;i++)
{
hexp_port_state_t state;
halexp_get_port_state(&state, port_list.port_names[i]);
term_pcprintf(5+i, 1, C_WHITE, "%s: ", port_list.port_names[i]);
if(state.up) term_cprintf(C_GREEN, "Link up "); else term_cprintf(C_RED, "Link down ");
term_cprintf(C_GREY, "mode: ");
switch(state.mode)
{
case HEXP_PORT_MODE_WR_MASTER:term_cprintf(C_WHITE, "WR Master ");break;
case HEXP_PORT_MODE_WR_SLAVE:term_cprintf(C_WHITE, "WR Slave ");break;
}
if(state.is_locked) term_cprintf(C_GREEN, "Locked "); else term_cprintf(C_RED, "NoLock ");
if(state.rx_calibrated && state.tx_calibrated) term_cprintf(C_GREEN, "Calibrated "); else term_cprintf(C_RED, "Uncalibrated ");
}
}
int ph_adjust = 0;
void show_servo()
{
ptpdexp_sync_state_t ss;
wripc_call(h_ptp, "ptpdexp_get_sync_state", &ss, 0);
term_cprintf(C_BLUE, "\n\nSynchronization status:\n\n");
if(!ss.valid)
{
term_cprintf(C_RED, "Master mode or sync info not valid\n\n");
return;
}
term_cprintf(C_GREY, "Servo state: "); term_cprintf(C_WHITE, "%s\n", ss.slave_servo_state);
term_cprintf(C_GREY, "Phase tracking: "); if(ss.tracking_enabled) term_cprintf(C_GREEN, "ON\n"); else term_cprintf(C_RED,"OFF\n");
term_cprintf(C_GREY, "Synchronization source: "); term_cprintf(C_WHITE, "%s\n", ss.sync_source);
term_cprintf(C_BLUE, "\nTiming parameters:\n\n");
term_cprintf(C_GREY, "Round-trip time (mu): "); term_cprintf(C_WHITE, "%.2f nsec\n", ss.mu/1000.0);
term_cprintf(C_GREY, "Master-slave delay: "); term_cprintf(C_WHITE, "%.2f nsec\n", ss.delay_ms/1000.0);
term_cprintf(C_GREY, "Link length: "); term_cprintf(C_WHITE, "%.0f meters \n", ss.delay_ms/1e12 * 300e6 / 1.55);
term_cprintf(C_GREY, "Master PHY delays: "); term_cprintf(C_WHITE, "TX: %.2f nsec, RX: %.2f nsec\n", ss.delta_tx_m/1000.0, ss.delta_rx_m/1000.0);
term_cprintf(C_GREY, "Slave PHY delays: "); term_cprintf(C_WHITE, "TX: %.2f nsec, RX: %.2f nsec\n", ss.delta_tx_s/1000.0, ss.delta_rx_s/1000.0);
term_cprintf(C_GREY, "Total link asymmetry: "); term_cprintf(C_WHITE, "%.2f nsec\n", ss.total_asymmetry/1000.0);
// term_cprintf(C_GREY, "Fiber asymmetry: "); term_cprintf(C_WHITE, "%.2f nsec\n", ss.fiber_asymmetry/1000.0);
term_cprintf(C_GREY, "Clock offset: "); term_cprintf(C_WHITE, "%.2f nsec\n", ss.cur_offset/1000.0);
term_cprintf(C_GREY, "Phase setpoint: "); term_cprintf(C_WHITE, "%.2f nsec\n", ss.cur_setpoint/1000.0);
term_cprintf(C_GREY, "Skew: "); term_cprintf(C_WHITE, "%.2f nsec\n", ss.cur_skew/1000.0);
term_cprintf(C_GREY, "Phase extra adjust: "); term_cprintf(C_WHITE, "%.2f nsec\n", (double) ph_adjust/1000.0);
}
int ki=20, kp=1000;
void show_pll()
{
term_cprintf(C_BLUE, "\n\nDMPLL:\n\n");
term_cprintf(C_GREY, "KI: %d KP: %d", ki, kp);
}
void show_menu()
{
term_pcprintf(30, 1, C_BLUE, "q = quit, t = toggle tracking");
}
int track_onoff = 1;
void show_screen()
{
term_clear();
term_pcprintf(1, 1, C_BLUE, "WR Switch Sync Monitor v 0.1");
show_ports();
show_servo();
show_menu();
// handle_toggle();
}
void pll_set_gain(int kp, int ki)
{
hexp_pll_cmd_t cmd;
cmd.pll = HEXP_DMPLL;
cmd.branch = HEXP_PHASE;
cmd.ki = ki;
cmd.kp = kp;
// halexp_pll_cmd(0, &cmd);
}
main()
{
int rval;
init();
for(;;)
{
if(term_poll())
{
int c = term_get();
if(c=='q') break;
else if(c=='t') {
track_onoff = 1-track_onoff;
wripc_call(h_ptp, "ptpdexp_cmd", &rval, 2, A_INT32(PTPDEXP_COMMAND_TRACKING), A_INT32(track_onoff));
} else if (c=='a')
{
ph_adjust += 500;
wripc_call(h_ptp, "ptpdexp_cmd", &rval, 2, A_INT32(PTPDEXP_COMMAND_MAN_ADJUST_PHASE), A_INT32(ph_adjust));
} else if (c=='z')
{
ph_adjust -= 500;
wripc_call(h_ptp, "ptpdexp_cmd", &rval, 2, A_INT32(PTPDEXP_COMMAND_MAN_ADJUST_PHASE), A_INT32(ph_adjust));
}
else if (c=='s')
{
ki += 10;
pll_set_gain(kp, ki);
} else if (c=='x')
{
ki -= 10;
pll_set_gain(kp, ki);
}
else if (c=='d')
{
kp += 10;
pll_set_gain(kp, ki);
} else if (c=='c')
{
kp -= 10;
pll_set_gain(kp, ki);
}
}
show_screen();
usleep(500000);
}
term_cprintf(C_GREY,"bye...\n\n");
term_clear();
term_restore();
}
\ No newline at end of file
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