Commit b6ec82e8 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski

added programmable deglitcher threshold to softpll

parent a91309a3
......@@ -3,7 +3,7 @@
* File : softpll_regs.h
* Author : auto-generated by wbgen2 from wr_softpll.wb
* Created : Fri Apr 8 20:09:44 2011
* Created : Sat Apr 9 13:29:44 2011
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wr_softpll.wb
......@@ -45,9 +45,7 @@
#define SPLL_CSR_TAG_RDY_W(value) WBGEN2_GEN_WRITE(value, 4, 4)
#define SPLL_CSR_TAG_RDY_R(reg) WBGEN2_GEN_READ(reg, 4, 4)
/* definitions for register: HPLL Tag */
/* definitions for register: HPLL Period */
/* definitions for register: HPLL Frequency Error */
/* definitions for register: DMPLL Tag ref */
......@@ -57,6 +55,8 @@
/* definitions for register: DMPLL DAC Output */
/* definitions for register: Deglitcher threshold */
/* definitions for register: Interrupt disable register */
/* definitions for field: Got a tag in reg: Interrupt disable register */
......@@ -80,18 +80,18 @@
PACKED struct SPLL_WB {
/* [0x0]: REG SPLL Control/Status Register */
uint32_t CSR;
/* [0x4]: REG HPLL Tag */
uint32_t TAG_HPLL;
/* [0x8]: REG HPLL Period */
/* [0x4]: REG HPLL Frequency Error */
uint32_t PER_HPLL;
/* [0xc]: REG DMPLL Tag ref */
/* [0x8]: REG DMPLL Tag ref */
uint32_t TAG_REF;
/* [0x10]: REG DMPLL Tag fb */
/* [0xc]: REG DMPLL Tag fb */
uint32_t TAG_FB;
/* [0x14]: REG HPLL DAC Output */
/* [0x10]: REG HPLL DAC Output */
uint32_t DAC_HPLL;
/* [0x18]: REG DMPLL DAC Output */
/* [0x14]: REG DMPLL DAC Output */
uint32_t DAC_DMPLL;
/* [0x18]: REG Deglitcher threshold */
uint32_t DEGLITCH_THR;
/* padding to: 8 words */
uint32_t __padding_0[1];
/* [0x20]: REG Interrupt disable register */
......
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