Commit b192720c authored by Grzegorz Daniluk's avatar Grzegorz Daniluk

ad9516: keep output 9 at 62.5MHz

parent 2650958e
......@@ -270,7 +270,6 @@ int ad9516_init(int scb_version)
ad9516_set_output_divider(spi_base, 3, 4, 0); // OUT3. 187.5 MHz. - not anymore
ad9516_set_output_divider(spi_base, 4, 1, 0); // OUT4. 500 MHz.
ad9516_set_output_divider(spi_base, 9, 20,0);
/*The following PLL outputs have been configured through the ad9516_base_config_34 register,
* so it doesn't need to replicate the configuration:
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment