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Software for White Rabbit PTP Core
Commit 838f428a authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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regenerated endpoint_mdio.h, it had 4 instead of 5 bit mask for reading bitslide value 

It becomes a problem when WRPC works in 16-bit PCS mode. In such case bitslide
value is 5bit and masking it with 0xF could cause wrong bts once in a while.
parent 4ded48b2
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Showing with 6 additions and 5 deletions
include/hw/endpoint_mdio.h
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/*
Register definitions for slave core: WR Endpoint 1000base-X TBI PCS register block
* File : ../../../software/include/hw/endpoint_mdio.h
* File : endpoint_mdio.h
* Author : auto-generated by wbgen2 from pcs_regs.wb
* Created : Tue Dec 7 17:14:23 2010
* Created : Tue Jan 14 10:24:03 2014
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE pcs_regs.wb
......@@ -30,6 +30,7 @@
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: MDIO Control Register */
/* definitions for field: Reserved in reg: MDIO Control Register */
......@@ -361,10 +362,10 @@
#define MDIO_WR_SPEC_CAL_CRST WBGEN2_GEN_MASK(2, 1)
/* definitions for field: GTP RX Bitslide in reg: WhiteRabbit-specific Configuration Register */
#define MDIO_WR_SPEC_BSLIDE_MASK WBGEN2_GEN_MASK(4, 4)
#define MDIO_WR_SPEC_BSLIDE_MASK WBGEN2_GEN_MASK(4, 5)
#define MDIO_WR_SPEC_BSLIDE_SHIFT 4
#define MDIO_WR_SPEC_BSLIDE_W(value) WBGEN2_GEN_WRITE(value, 4, 4)
#define MDIO_WR_SPEC_BSLIDE_R(reg) WBGEN2_GEN_READ(reg, 4, 4)
#define MDIO_WR_SPEC_BSLIDE_W(value) WBGEN2_GEN_WRITE(value, 4, 5)
#define MDIO_WR_SPEC_BSLIDE_R(reg) WBGEN2_GEN_READ(reg, 4, 5)
/* [0x0]: REG MDIO Control Register */
#define MDIO_REG_MCR 0x00000000
/* [0x4]: REG MDIO Status Register */
......
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