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Software for White Rabbit PTP Core
Commit 7e3805a6 authored by Alessandro Rubini's avatar Alessandro Rubini
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softpll: return 0 or 1 in the non-criticall poll function 

Signed-off-by: Alessandro Rubini's avatarAlessandro Rubini <rubini@gnudd.com>
parent ab59735a
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Showing with 33 additions and 14 deletions
softpll/softpll_ng.c
View file @ 7e3805a6
......@@ -534,6 +534,7 @@ static inline void aux_set_channel_status(int channel, int locked)
static int spll_update_aux_clocks(void)
{
int ch;
int done_sth = 0;
for (ch = 1; ch < spll_n_chan_out; ch++)
{
......@@ -545,6 +546,7 @@ static int spll_update_aux_clocks(void)
spll_stop_channel(ch);
aux_set_channel_status(ch, 0);
s->seq_state = AUX_DISABLED;
done_sth++;
}
switch (s->seq_state) {
......@@ -553,6 +555,7 @@ static int spll_update_aux_clocks(void)
pll_verbose("softpll: enabled aux channel %d\n", ch);
spll_start_channel(ch);
s->seq_state = AUX_LOCK_PLL;
done_sth++;
}
break;
......@@ -561,8 +564,8 @@ static int spll_update_aux_clocks(void)
pll_verbose ("softpll: channel %d locked [aligning @ %d ps]\n", ch, softpll.mpll_shift_ps);
set_phase_shift(ch, softpll.mpll_shift_ps);
s->seq_state = AUX_ALIGN_PHASE;
done_sth++;
}
break;
case AUX_ALIGN_PHASE:
......@@ -570,6 +573,7 @@ static int spll_update_aux_clocks(void)
pll_verbose("softpll: channel %d phase aligned\n", ch);
aux_set_channel_status(ch, 1);
s->seq_state = AUX_READY;
done_sth++;
}
break;
......@@ -578,11 +582,12 @@ static int spll_update_aux_clocks(void)
pll_verbose("softpll: aux channel %d or mpll lost lock\n", ch);
aux_set_channel_status(ch, 0);
s->seq_state = AUX_DISABLED;
done_sth++;
}
break;
}
}
return 0;
return done_sth != 0;
}
int spll_get_aux_status(int channel)
......@@ -625,14 +630,16 @@ void spll_set_dac(int index, int value)
}
}
void spll_update()
int spll_update()
{
int ret = 0;
switch(softpll.mode) {
case SPLL_MODE_GRAND_MASTER:
external_align_fsm(&softpll.ext);
ret = external_align_fsm(&softpll.ext);
break;
}
spll_update_aux_clocks();
ret += spll_update_aux_clocks();
/* currently we have statistics only in the switch */
if (is_wr_switch) {
......@@ -648,6 +655,7 @@ void spll_update()
stats.del_cnt = softpll.delock_count;
stats.sequence++;
}
return ret != 0;
}
static int spll_measure_frequency(int osc)
......
softpll/softpll_ng.h
View file @ 7e3805a6
......@@ -105,7 +105,7 @@ int spll_read_ptracker(int ref_channel, int32_t *phase_ps, int *enabled);
/* Calls non-realtime update state machine. Must be called regularly (although
* it is not time-critical) in the main loop of the program if aux clocks or
* external reference are used in the design. */
void spll_update(void);
int spll_update(void);
/* Returns the status of given aux clock output (SPLL_AUX_) */
int spll_get_aux_status(int out_channel);
......
softpll/spll_external.c
View file @ 7e3805a6
......@@ -94,11 +94,11 @@ static int align_sample(int channel, int *v)
return 0; // sample not valid
}
void external_align_fsm(volatile struct spll_external_state *s)
int external_align_fsm(volatile struct spll_external_state *s)
{
int v;
switch(s->align_state) {
int v, done_sth = 0;
switch(s->align_state) {
case ALIGN_STATE_EXT_OFF:
break;
......@@ -106,6 +106,7 @@ void external_align_fsm(volatile struct spll_external_state *s)
if( !(SPLL->ECCR & SPLL_ECCR_EXT_REF_STOPPED) ) {
SPLL->ECCR |= SPLL_ECCR_EXT_REF_PLLRST;
s->align_state = ALIGN_STATE_WAIT_PLOCK;
done_sth++;
}
break;
......@@ -115,6 +116,7 @@ void external_align_fsm(volatile struct spll_external_state *s)
s->align_state = ALIGN_STATE_WAIT_CLKIN;
else if( SPLL->ECCR & SPLL_ECCR_EXT_REF_LOCKED )
s->align_state = ALIGN_STATE_START;
done_sth++;
break;
case ALIGN_STATE_START:
......@@ -123,6 +125,7 @@ void external_align_fsm(volatile struct spll_external_state *s)
mpll_start(s->main);
enable_irq();
s->align_state = ALIGN_STATE_START_MAIN;
done_sth++;
}
break;
......@@ -130,10 +133,11 @@ void external_align_fsm(volatile struct spll_external_state *s)
SPLL->AL_CR = 2;
if(s->helper->ld.locked && s->main->ld.locked) {
PPSG->CR = PPSG_CR_CNT_EN | PPSG_CR_PWIDTH_W(10);
PPSG->ADJ_NSEC = 3;
PPSG->ESCR = PPSG_ESCR_SYNC;
s->align_state = ALIGN_STATE_INIT_CSYNC;
pll_verbose("EXT: DMTD locked.\n");
PPSG->ADJ_NSEC = 3;
PPSG->ESCR = PPSG_ESCR_SYNC;
s->align_state = ALIGN_STATE_INIT_CSYNC;
pll_verbose("EXT: DMTD locked.\n");
done_sth++;
}
break;
......@@ -142,6 +146,7 @@ void external_align_fsm(volatile struct spll_external_state *s)
PPSG->ESCR = PPSG_ESCR_PPS_VALID; // enable PPS output (even though it's not aligned yet)
s->align_timer = timer_get_tics() + 2 * TICS_PER_SECOND;
s->align_state = ALIGN_STATE_WAIT_CSYNC;
done_sth++;
}
break;
......@@ -150,6 +155,7 @@ void external_align_fsm(volatile struct spll_external_state *s)
s->align_state = ALIGN_STATE_START_ALIGNMENT;
s->align_shift = 0;
pll_verbose("EXT: CSync complete.\n");
done_sth++;
}
break;
......@@ -166,6 +172,7 @@ void external_align_fsm(volatile struct spll_external_state *s)
pll_verbose("EXT: Align target %d, step %d.\n", s->align_target, s->align_step);
s->align_state = ALIGN_STATE_WAIT_SAMPLE;
done_sth++;
}
break;
......@@ -180,6 +187,7 @@ void external_align_fsm(volatile struct spll_external_state *s)
mpll_set_phase_shift(s->main, s->align_shift);
s->align_state = ALIGN_STATE_COMPENSATE_DELAY;
}
done_sth++;
}
break;
......@@ -187,16 +195,19 @@ void external_align_fsm(volatile struct spll_external_state *s)
if(!mpll_shifter_busy(s->main)) {
pll_verbose("EXT: Align done.\n");
s->align_state = ALIGN_STATE_LOCKED;
done_sth++;
}
break;
case ALIGN_STATE_LOCKED:
if(!external_locked(s)) {
s->align_state = ALIGN_STATE_WAIT_CLKIN;
done_sth++;
}
break;
default:
break;
}
return done_sth != 0;
}
softpll/spll_external.h
View file @ 7e3805a6
......@@ -35,6 +35,6 @@ void external_start(struct spll_external_state *s);
int external_locked(volatile struct spll_external_state *s);
void external_align_fsm(volatile struct spll_external_state *s);
int external_align_fsm(volatile struct spll_external_state *s);
#endif // __SPLL_EXTERNAL_H
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