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Software for White Rabbit PTP Core
Commit 75b22ecf authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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new regs in softpll (with external clk input)

parent 709e66d1
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Showing with 31 additions and 15 deletions
include/hw/softpll_regs.h
View file @ 75b22ecf
......@@ -3,7 +3,7 @@
* File : softpll_regs.h
* Author : auto-generated by wbgen2 from spll_wb_slave.wb
* Created : Mon Mar 12 16:02:27 2012
* Created : Fri Apr 13 09:37:36 2012
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE spll_wb_slave.wb
......@@ -54,17 +54,31 @@
/* definitions for field: Enable Period Measurement in reg: SPLL Control/Status Register */
#define SPLL_CSR_PER_EN WBGEN2_GEN_MASK(19, 1)
/* definitions for register: External Clock Control Register */
/* definitions for field: Enable External Clock BB Detector in reg: External Clock Control Register */
#define SPLL_ECCR_EXT_EN WBGEN2_GEN_MASK(0, 1)
/* definitions for field: External Clock Input Available in reg: External Clock Control Register */
#define SPLL_ECCR_EXT_SUPPORTED WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Enable PPS/phase alignment in reg: External Clock Control Register */
#define SPLL_ECCR_ALIGN_EN WBGEN2_GEN_MASK(2, 1)
/* definitions for field: PPS/phase alignment done in reg: External Clock Control Register */
#define SPLL_ECCR_ALIGN_DONE WBGEN2_GEN_MASK(3, 1)
/* definitions for register: DMTD Clock Control Register */
/* definitions for field: DMTD Clock Gate Divider in reg: DMTD Clock Control Register */
/* definitions for field: DMTD Clock Undersampling Divider in reg: DMTD Clock Control Register */
#define SPLL_DCCR_GATE_DIV_MASK WBGEN2_GEN_MASK(0, 6)
#define SPLL_DCCR_GATE_DIV_SHIFT 0
#define SPLL_DCCR_GATE_DIV_W(value) WBGEN2_GEN_WRITE(value, 0, 6)
#define SPLL_DCCR_GATE_DIV_R(reg) WBGEN2_GEN_READ(reg, 0, 6)
/* definitions for register: Reference Channel Gating Enable Register */
/* definitions for register: Reference Channel Undersampling Enable Register */
/* definitions for field: Reference Channel Gating Enable in reg: Reference Channel Gating Enable Register */
/* definitions for field: Reference Channel Undersampling Enable in reg: Reference Channel Undersampling Enable Register */
#define SPLL_RCGER_GATE_SEL_MASK WBGEN2_GEN_MASK(0, 32)
#define SPLL_RCGER_GATE_SEL_SHIFT 0
#define SPLL_RCGER_GATE_SEL_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
......@@ -206,28 +220,30 @@
PACKED struct SPLL_WB {
/* [0x0]: REG SPLL Control/Status Register */
uint32_t CSR;
/* [0x4]: REG DMTD Clock Control Register */
/* [0x4]: REG External Clock Control Register */
uint32_t ECCR;
/* [0x8]: REG DMTD Clock Control Register */
uint32_t DCCR;
/* [0x8]: REG Reference Channel Gating Enable Register */
/* [0xc]: REG Reference Channel Undersampling Enable Register */
uint32_t RCGER;
/* [0xc]: REG Output Channel Control Register */
/* [0x10]: REG Output Channel Control Register */
uint32_t OCCR;
/* [0x10]: REG Reference Channel Enable Register */
/* [0x14]: REG Reference Channel Enable Register */
uint32_t RCER;
/* [0x14]: REG Output Channel Enable Register */
/* [0x18]: REG Output Channel Enable Register */
uint32_t OCER;
/* [0x18]: REG HPLL Period Error */
/* [0x1c]: REG HPLL Period Error */
uint32_t PER_HPLL;
/* [0x1c]: REG Helper DAC Output */
/* [0x20]: REG Helper DAC Output */
uint32_t DAC_HPLL;
/* [0x20]: REG Main DAC Output */
/* [0x24]: REG Main DAC Output */
uint32_t DAC_MAIN;
/* [0x24]: REG Deglitcher threshold */
/* [0x28]: REG Deglitcher threshold */
uint32_t DEGLITCH_THR;
/* [0x28]: REG Debug FIFO Register - SPLL side */
/* [0x2c]: REG Debug FIFO Register - SPLL side */
uint32_t DFR_SPLL;
/* padding to: 16 words */
uint32_t __padding_0[5];
uint32_t __padding_0[4];
/* [0x40]: REG Interrupt disable register */
uint32_t EIC_IDR;
/* [0x44]: REG Interrupt enable register */
......
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