Commit 72c8d2a8 authored by Dimitris Lampridis's avatar Dimitris Lampridis Committed by Adam Wujek

dev: introduce PPS mask/unmask bit in pps_gen.

By default, the bit is zero (masked), which means that PPS signal output is masked
when the link status is not ok. This is useful to pervent spurious PPS when in
SLAVE mode and the link goes down.

When the bit is set, then a PPS is always generated (as long as the PPS valid bit
in the ESCR register is set). This is useful in master mode.
parent 89ece536
......@@ -134,3 +134,15 @@ int shw_pps_gen_enable_output(int enable)
return 0;
}
/* Masks/unmasks PPS output when link is down (useful in master mode) */
int shw_pps_gen_unmask_output(int unmask)
{
uint32_t escr = ppsg_read(ESCR);
if (unmask)
ppsg_write(ESCR, escr | PPSG_ESCR_PPS_UNMASK);
else
ppsg_write(ESCR, escr & ~PPSG_ESCR_PPS_UNMASK);
return 0;
}
......@@ -3,7 +3,7 @@
* File : pps_gen_regs.h
* Author : auto-generated by wbgen2 from pps_gen_wb.wb
* Created : Fri Jul 26 15:09:09 2013
* Created : Fri Feb 10 10:53:05 2017
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE pps_gen_wb.wb
......@@ -14,7 +14,11 @@
#ifndef __WBGEN2_REGDEFS_PPS_GEN_WB_WB
#define __WBGEN2_REGDEFS_PPS_GEN_WB_WB
#ifdef __KERNEL__
#include <linux/types.h>
#else
#include <inttypes.h>
#endif
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
......@@ -68,17 +72,20 @@
/* definitions for field: Sync to external PPS input in reg: External sync control register */
#define PPSG_ESCR_SYNC WBGEN2_GEN_MASK(0, 1)
/* definitions for field: PPS unmask output in reg: External sync control register */
#define PPSG_ESCR_PPS_UNMASK WBGEN2_GEN_MASK(1, 1)
/* definitions for field: PPS output valid in reg: External sync control register */
#define PPSG_ESCR_PPS_VALID WBGEN2_GEN_MASK(1, 1)
#define PPSG_ESCR_PPS_VALID WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Timecode output(UTC+cycles) valid in reg: External sync control register */
#define PPSG_ESCR_TM_VALID WBGEN2_GEN_MASK(2, 1)
#define PPSG_ESCR_TM_VALID WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Set seconds counter in reg: External sync control register */
#define PPSG_ESCR_SEC_SET WBGEN2_GEN_MASK(3, 1)
#define PPSG_ESCR_SEC_SET WBGEN2_GEN_MASK(4, 1)
/* definitions for field: Set nanoseconds counter in reg: External sync control register */
#define PPSG_ESCR_NSEC_SET WBGEN2_GEN_MASK(4, 1)
#define PPSG_ESCR_NSEC_SET WBGEN2_GEN_MASK(5, 1)
PACKED struct PPSG_WB {
/* [0x0]: REG Control Register */
......
......@@ -26,6 +26,9 @@ int shw_pps_gen_busy(void);
/* Enables/disables PPS Generator PPS output */
int shw_pps_gen_enable_output(int enable);
/* Masks/unmasks PPS output when link is down (useful in master mode) */
int shw_pps_gen_unmask_output(int unmask);
/* Reads the current time and stores at <seconds,nanoseconds>. */
void shw_pps_gen_get_time(uint64_t * seconds, uint32_t * nanoseconds);
......
ppsi @ d6aefd73
Subproject commit f8cf1be371150883d1d3c9ba1a87b35b4e2b9f69
Subproject commit d6aefd732b984cc4237277938ea183a038b53603
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