Commit 68f17463 authored by Peter Jansweijer's avatar Peter Jansweijer

clbv2, clbv4 use low phase drift phy

parent 4467bedb
Pipeline #3718 failed with stage
in 1 minute and 23 seconds
......@@ -72,6 +72,21 @@ config TARGET_HPSEC
help
SPEC7 (Zynq-7000) with High Precision Secondairy External Clock
config TARGET_CLB_V2
bool "CLB_V2"
help
KM3NeT Central Logic Board (Version 2 based on Kintex-7)
config TARGET_CLB_V3
bool "CLB_V3"
help
KM3NeT Central Logic Board (Version 3 based on Artix-7)
config TARGET_CLB_V4
bool "CLB_V4"
help
KM3NeT Central Logic Board (Version 4 based on Kintex-7)
config TARGET_PXIE_FMC
bool "ZU7 PXIe FMC Carrier"
help
......
......@@ -7,6 +7,9 @@ obj-$(CONFIG_TARGET_SIS8300KU) += boards/sis8300ku/board.o
obj-$(CONFIG_TARGET_ERTM14) += boards/ertm14/board.o boards/ertm14/ertm15_rf_distr.o boards/ertm14/phy_calibration.o boards/ertm14/rf_frame_transceiver.o boards/ertm14/cmd_ertm14.o boards/ertm14/sdbfs-custom-image.o
obj-$(CONFIG_TARGET_ERTM14) += boards/ertm14/common-uart-link.o boards/ertm14/wrpc-uart-link.o
obj-$(CONFIG_TARGET_SPEC7) += boards/spec7/board.o boards/spec7/phy_calibration.o
obj-$(CONFIG_TARGET_CLB_V2) += boards/clbv2/board.o boards/clbv2/phy_calibration.o
obj-$(CONFIG_TARGET_CLB_V3) += boards/clbv3/board.o
obj-$(CONFIG_TARGET_CLB_V4) += boards/clbv4/board.o boards/clbv4/phy_calibration.o
obj-$(CONFIG_TARGET_PXIE_FMC) += boards/pxie-fmc/board.o
obj-$(CONFIG_TARGET_WR2RF_VME) += boards/wr2rf-vme/board.o boards/wr2rf-vme/sdbfs-custom-image.o boards/ertm14/phy_calibration.o
......
/*
* This work is part of the White Rabbit project
*
* Copyright (C) 2022 Nikhef (www.Nikhef.nl)
* Author: Peter Jansweijer <peterj@nikhef.nl> based on work
* from Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
*
* This program is free software: you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation, either version 3 of the License, or (at your
* option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include "board.h"
#include "wrc.h"
#include "wrc-debug.h"
#include "dev/bb_spi.h"
#include "dev/bb_i2c.h"
#include "dev/w1.h"
#include "dev/spi_flash.h"
#include "dev/i2c_eeprom.h"
#include "dev/syscon.h"
#include "dev/endpoint.h"
#include "storage.h"
int wrc_board_early_init()
{
int memtype;
uint32_t sdbfs_entry;
uint32_t sector_size;
if (EEPROM_STORAGE) {
/* EEPROM support */
bb_i2c_create( &i2c_wrc_eeprom,
&pin_sysc_fmc_scl,
&pin_sysc_fmc_sda );
bb_i2c_init( &i2c_wrc_eeprom );
i2c_eeprom_create( &wrc_eeprom_dev, &i2c_wrc_eeprom, FMC_EEPROM_ADR, 2);
storage_i2ceeprom_create( &wrc_storage_dev, &wrc_eeprom_dev );
} else {
/* Flash support */
/*
* declare GPIO pins and configure their directions for bit-banging SPI
* limit SPI speed to 10MHz by setting bit_delay = CPU_CLOCK / 10^6
*/
bb_spi_create( &spi_wrc_flash,
&pin_sysc_spi_ncs,
&pin_sysc_spi_mosi,
&pin_sysc_spi_miso,
&pin_sysc_spi_sclk, CPU_CLOCK / 10000000 );
spi_wrc_flash.rd_falling_edge = 1;
/*
* Read from gateware info about used memory. Currently only base
* address and sector size for memtype flash is supported.
*/
get_storage_info(&memtype, &sdbfs_entry, &sector_size);
/*
* Initialize SPI flash and read its ID
*/
spi_flash_create( &wrc_flash_dev, &spi_wrc_flash, sector_size, sdbfs_entry);
/*
* Initialize storage subsystem with newly created SPI Flash
*/
storage_spiflash_create( &wrc_storage_dev, &wrc_flash_dev );
}
/*
* Mount SDBFS filesystem from storage.
*/
// #### TEMP_FIX ####
// #### Fixes RISC Crash due to SDBFS not present when EEPROM is clean ####
uint32_t base = 0;
storage_sdbfs_format( &wrc_storage_dev, base, 0 );
//storage_sdbfs_erase( &wrc_storage_dev, base, 0 );
// #### END_TEMP_FIX ####
storage_mount( &wrc_storage_dev );
return 0;
}
static int board_get_persistent_mac(uint8_t *mac)
{
int i;
struct w1_dev *d;
/* Try from SDB */
if (storage_get_persistent_mac(0, mac) == 0)
return 0;
/* Get from one-wire (derived from unique id) */
w1_scan_bus(&wrpc_w1_bus);
for (i = 0; i < W1_MAX_DEVICES; i++) {
d = wrpc_w1_bus.devs + i;
if (d->rom) {
mac[0] = 0x22;
mac[1] = 0x33;
mac[2] = 0xff & (d->rom >> 32);
mac[3] = 0xff & (d->rom >> 24);
mac[4] = 0xff & (d->rom >> 16);
mac[5] = 0xff & (d->rom >> 8);
return 0;
}
}
/* Not found */
return -1;
}
int wrc_board_init()
{
uint8_t mac_addr[6];
/*
* Try reading MAC addr stored in flash
*/
if (board_get_persistent_mac(mac_addr) < 0) {
board_dbg("Failed to get MAC address from the flash. Using fallback address.\n");
mac_addr[0] = 0x22;
mac_addr[1] = 0x33;
mac_addr[2] = 0x44;
mac_addr[3] = 0x55;
mac_addr[4] = 0x66;
mac_addr[5] = 0x77;
}
ep_set_mac_addr(&wrc_endpoint_dev, mac_addr);
ep_pfilter_init_default(&wrc_endpoint_dev);
return 0;
}
int wrc_board_create_tasks()
{
wrc_task_create( "phy-cal", phy_calibration_init, phy_calibration_poll );
return 0;
}
/*
* This work is part of the White Rabbit project
*
* Released according to the GNU GPL, version 2 or any later version.
*/
#include <netconsole.h>
#ifndef __BOARD_WRC_H
#define __BOARD_WRC_H
/*
* This is meant to be automatically included by the Makefile,
* when wrpc-sw is build for wrc (node) -- as opposed to wrs (switch)
*/
#ifdef CONFIG_ARCH_RISCV
#define DEV_BASE 0x100000
#elif defined CONFIG_ARCH_LM32
#define DEV_BASE 0x40000
#else
#error (Wrong Arch!)
#endif
/* Fixed base addresses */
#define BASE_MINIC (DEV_BASE + 0x000)
#define BASE_EP (DEV_BASE + 0x100)
#define BASE_SOFTPLL (DEV_BASE + 0x200)
#define BASE_PPS_GEN (DEV_BASE + 0x300)
#define BASE_SYSCON (DEV_BASE + 0x400)
#define BASE_UART (DEV_BASE + 0x500)
#define BASE_ONEWIRE (DEV_BASE + 0x600)
#define BASE_WDIAGS_PRIV (DEV_BASE + 0x900)
#define BASE_ETHERBONE_CFG (DEV_BASE + 0x8000)
/* Board-specific parameters */
#define TICS_PER_SECOND 1000
/* WR Core system/CPU clock frequency in Hz */
#define CPU_CLOCK 62500000ULL
/* WR Reference clock period (picoseconds) and frequency (Hz) */
/* CLB_V2 has GENERIC_PHY_16BIT */
#define NS_PER_CLOCK 16
#define REF_CLOCK_PERIOD_PS 16000
#define REF_CLOCK_FREQ_HZ 62500000
/* Maximum number of simultaneously created sockets */
#define NET_MAX_SOCKETS 12
/* Socket buffer size, determines the max. RX packet size */
#define NET_MAX_SKBUF_SIZE 512
/* Number of auxillary clock channels - usually equal to the number of FMCs */
#define NUM_AUX_CLOCKS 1
/* spll parameter that are board-specific */
/* CLB_V2 has GENERIC_PHY_16BIT */
#define BOARD_DIVIDE_DMTD_CLOCKS 0
#define BOARD_MAX_CHAN_REF 1
#define BOARD_MAX_CHAN_AUX 2
#define BOARD_MAX_PTRACKERS 1
#undef CONFIG_DISALLOW_LONG_DIVISION
#define BOARD_USE_EVENTS 0
#define BOARD_MAX_CONSOLE_DEVICES (1 + HAS_NETCONSOLE + HAS_PUTS_SYSLOG)
#define CONSOLE_UART_BAUDRATE 115200
#define FMC_EEPROM_ADR 0x50
#define SDBFS_REC 5
#define EEPROM_STORAGE 1
void sdb_find_devices(void);
void sdb_print_devices(void);
extern int phy_calibration_poll(void);
extern void phy_calibration_init(void);
extern int phy_calibration_done(void);
extern void phy_calibration_disable(void);
#endif /* __BOARD_WRC_H */
This diff is collapsed.
/*
* This work is part of the White Rabbit project
*
* Copyright (C) 2022 Nikhef (www.Nikhef.nl)
* Author: Peter Jansweijer <peterj@nikhef.nl> based on work
* from Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
*
* This program is free software: you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation, either version 3 of the License, or (at your
* option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include "board.h"
#include "wrc.h"
#include "wrc-debug.h"
#include "dev/bb_spi.h"
#include "dev/bb_i2c.h"
#include "dev/w1.h"
#include "dev/spi_flash.h"
#include "dev/i2c_eeprom.h"
#include "dev/syscon.h"
#include "dev/endpoint.h"
#include "storage.h"
int wrc_board_early_init()
{
int memtype;
uint32_t sdbfs_entry;
uint32_t sector_size;
if (EEPROM_STORAGE) {
/* EEPROM support */
bb_i2c_create( &i2c_wrc_eeprom,
&pin_sysc_fmc_scl,
&pin_sysc_fmc_sda );
bb_i2c_init( &i2c_wrc_eeprom );
i2c_eeprom_create( &wrc_eeprom_dev, &i2c_wrc_eeprom, FMC_EEPROM_ADR, 2);
storage_i2ceeprom_create( &wrc_storage_dev, &wrc_eeprom_dev );
} else {
/* Flash support */
/*
* declare GPIO pins and configure their directions for bit-banging SPI
* limit SPI speed to 10MHz by setting bit_delay = CPU_CLOCK / 10^6
*/
bb_spi_create( &spi_wrc_flash,
&pin_sysc_spi_ncs,
&pin_sysc_spi_mosi,
&pin_sysc_spi_miso,
&pin_sysc_spi_sclk, CPU_CLOCK / 10000000 );
spi_wrc_flash.rd_falling_edge = 1;
/*
* Read from gateware info about used memory. Currently only base
* address and sector size for memtype flash is supported.
*/
get_storage_info(&memtype, &sdbfs_entry, &sector_size);
/*
* Initialize SPI flash and read its ID
*/
spi_flash_create( &wrc_flash_dev, &spi_wrc_flash, sector_size, sdbfs_entry);
/*
* Initialize storage subsystem with newly created SPI Flash
*/
storage_spiflash_create( &wrc_storage_dev, &wrc_flash_dev );
}
/*
* Mount SDBFS filesystem from storage.
*/
// #### TEMP_FIX ####
// #### Fixes RISC Crash due to SDBFS not present when EEPROM is clean ####
uint32_t base = 0;
storage_sdbfs_format( &wrc_storage_dev, base, 0 );
//storage_sdbfs_erase( &wrc_storage_dev, base, 0 );
// #### END_TEMP_FIX ####
storage_mount( &wrc_storage_dev );
return 0;
}
static int board_get_persistent_mac(uint8_t *mac)
{
int i;
struct w1_dev *d;
/* Try from SDB */
if (storage_get_persistent_mac(0, mac) == 0)
return 0;
/* Get from one-wire (derived from unique id) */
w1_scan_bus(&wrpc_w1_bus);
for (i = 0; i < W1_MAX_DEVICES; i++) {
d = wrpc_w1_bus.devs + i;
if (d->rom) {
mac[0] = 0x22;
mac[1] = 0x33;
mac[2] = 0xff & (d->rom >> 32);
mac[3] = 0xff & (d->rom >> 24);
mac[4] = 0xff & (d->rom >> 16);
mac[5] = 0xff & (d->rom >> 8);
return 0;
}
}
/* Not found */
return -1;
}
int wrc_board_init()
{
uint8_t mac_addr[6];
/*
* Try reading MAC addr stored in flash
*/
if (board_get_persistent_mac(mac_addr) < 0) {
board_dbg("Failed to get MAC address from the flash. Using fallback address.\n");
mac_addr[0] = 0x22;
mac_addr[1] = 0x33;
mac_addr[2] = 0x44;
mac_addr[3] = 0x55;
mac_addr[4] = 0x66;
mac_addr[5] = 0x77;
}
ep_set_mac_addr(&wrc_endpoint_dev, mac_addr);
ep_pfilter_init_default(&wrc_endpoint_dev);
return 0;
}
int wrc_board_create_tasks()
{
return 0;
}
/*
* This work is part of the White Rabbit project
*
* Released according to the GNU GPL, version 2 or any later version.
*/
#include <netconsole.h>
#ifndef __BOARD_WRC_H
#define __BOARD_WRC_H
/*
* This is meant to be automatically included by the Makefile,
* when wrpc-sw is build for wrc (node) -- as opposed to wrs (switch)
*/
#ifdef CONFIG_ARCH_RISCV
#define DEV_BASE 0x100000
#elif defined CONFIG_ARCH_LM32
#define DEV_BASE 0x40000
#else
#error (Wrong Arch!)
#endif
/* Fixed base addresses */
#define BASE_MINIC (DEV_BASE + 0x000)
#define BASE_EP (DEV_BASE + 0x100)
#define BASE_SOFTPLL (DEV_BASE + 0x200)
#define BASE_PPS_GEN (DEV_BASE + 0x300)
#define BASE_SYSCON (DEV_BASE + 0x400)
#define BASE_UART (DEV_BASE + 0x500)
#define BASE_ONEWIRE (DEV_BASE + 0x600)
#define BASE_WDIAGS_PRIV (DEV_BASE + 0x900)
#define BASE_ETHERBONE_CFG (DEV_BASE + 0x8000)
/* Board-specific parameters */
#define TICS_PER_SECOND 1000
/* WR Core system/CPU clock frequency in Hz */
#define CPU_CLOCK 62500000ULL
/* WR Reference clock period (picoseconds) and frequency (Hz) */
/* CLB_V3 has GENERIC_PHY_16BIT */
#define NS_PER_CLOCK 16
#define REF_CLOCK_PERIOD_PS 16000
#define REF_CLOCK_FREQ_HZ 62500000
/* Maximum number of simultaneously created sockets */
#define NET_MAX_SOCKETS 12
/* Socket buffer size, determines the max. RX packet size */
#define NET_MAX_SKBUF_SIZE 512
/* Number of auxillary clock channels - usually equal to the number of FMCs */
#define NUM_AUX_CLOCKS 1
/* spll parameter that are board-specific */
/* CLB_V3 has GENERIC_PHY_16BIT */
#define BOARD_DIVIDE_DMTD_CLOCKS 0
/* CLB_V3 uses CRYSTEC_CVPD992 for Helper and Main VCXO */
#define MAIN_CRYSTEK_CVPD922 1
#define HELPER_CRYSTEK_CVPD922 1
#define BOARD_MAX_CHAN_REF 1
#define BOARD_MAX_CHAN_AUX 2
#define BOARD_MAX_PTRACKERS 1
#undef CONFIG_DISALLOW_LONG_DIVISION
#define BOARD_USE_EVENTS 0
#define BOARD_MAX_CONSOLE_DEVICES (1 + HAS_NETCONSOLE + HAS_PUTS_SYSLOG)
#define CONSOLE_UART_BAUDRATE 115200
#define FMC_EEPROM_ADR 0x50
#define SDBFS_REC 5
#define EEPROM_STORAGE 1
void sdb_find_devices(void);
void sdb_print_devices(void);
#endif /* __BOARD_WRC_H */
/*
* This work is part of the White Rabbit project
*
* Copyright (C) 2022 Nikhef (www.Nikhef.nl)
* Author: Peter Jansweijer <peterj@nikhef.nl> based on work
* from Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
*
* This program is free software: you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation, either version 3 of the License, or (at your
* option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include "board.h"
#include "wrc.h"
#include "wrc-debug.h"
#include "dev/bb_spi.h"
#include "dev/bb_i2c.h"
#include "dev/w1.h"
#include "dev/spi_flash.h"
#include "dev/i2c_eeprom.h"
#include "dev/syscon.h"
#include "dev/endpoint.h"
#include "storage.h"
int wrc_board_early_init()
{
int memtype;
uint32_t sdbfs_entry;
uint32_t sector_size;
if (EEPROM_STORAGE) {
/* EEPROM support */
bb_i2c_create( &i2c_wrc_eeprom,
&pin_sysc_fmc_scl,
&pin_sysc_fmc_sda );
bb_i2c_init( &i2c_wrc_eeprom );
i2c_eeprom_create( &wrc_eeprom_dev, &i2c_wrc_eeprom, FMC_EEPROM_ADR, 2);
storage_i2ceeprom_create( &wrc_storage_dev, &wrc_eeprom_dev );
} else {
/* Flash support */
/*
* declare GPIO pins and configure their directions for bit-banging SPI
* limit SPI speed to 10MHz by setting bit_delay = CPU_CLOCK / 10^6
*/
bb_spi_create( &spi_wrc_flash,
&pin_sysc_spi_ncs,
&pin_sysc_spi_mosi,
&pin_sysc_spi_miso,
&pin_sysc_spi_sclk, CPU_CLOCK / 10000000 );
spi_wrc_flash.rd_falling_edge = 1;
/*
* Read from gateware info about used memory. Currently only base
* address and sector size for memtype flash is supported.
*/
get_storage_info(&memtype, &sdbfs_entry, &sector_size);
/*
* Initialize SPI flash and read its ID
*/
spi_flash_create( &wrc_flash_dev, &spi_wrc_flash, sector_size, sdbfs_entry);
/*
* Initialize storage subsystem with newly created SPI Flash
*/
storage_spiflash_create( &wrc_storage_dev, &wrc_flash_dev );
}
/*
* Mount SDBFS filesystem from storage.
*/
// #### TEMP_FIX ####
// #### Fixes RISC Crash due to SDBFS not present when EEPROM is clean ####
uint32_t base = 0;
storage_sdbfs_format( &wrc_storage_dev, base, 0 );
//storage_sdbfs_erase( &wrc_storage_dev, base, 0 );
// #### END_TEMP_FIX ####
storage_mount( &wrc_storage_dev );
return 0;
}
static int board_get_persistent_mac(uint8_t *mac)
{
int i;
struct w1_dev *d;
/* Try from SDB */
if (storage_get_persistent_mac(0, mac) == 0)
return 0;
/* Get from one-wire (derived from unique id) */
w1_scan_bus(&wrpc_w1_bus);
for (i = 0; i < W1_MAX_DEVICES; i++) {
d = wrpc_w1_bus.devs + i;
if (d->rom) {
mac[0] = 0x22;
mac[1] = 0x33;
mac[2] = 0xff & (d->rom >> 32);
mac[3] = 0xff & (d->rom >> 24);
mac[4] = 0xff & (d->rom >> 16);
mac[5] = 0xff & (d->rom >> 8);
return 0;
}
}
/* Not found */
return -1;
}
int wrc_board_init()
{
uint8_t mac_addr[6];
/*
* Try reading MAC addr stored in flash
*/
if (board_get_persistent_mac(mac_addr) < 0) {
board_dbg("Failed to get MAC address from the flash. Using fallback address.\n");
mac_addr[0] = 0x22;
mac_addr[1] = 0x33;
mac_addr[2] = 0x44;
mac_addr[3] = 0x55;
mac_addr[4] = 0x66;
mac_addr[5] = 0x77;
}
ep_set_mac_addr(&wrc_endpoint_dev, mac_addr);
ep_pfilter_init_default(&wrc_endpoint_dev);
return 0;
}
int wrc_board_create_tasks()
{
wrc_task_create( "phy-cal", phy_calibration_init, phy_calibration_poll );
return 0;
}
/*
* This work is part of the White Rabbit project
*
* Released according to the GNU GPL, version 2 or any later version.
*/
#include <netconsole.h>
#ifndef __BOARD_WRC_H
#define __BOARD_WRC_H
/*
* This is meant to be automatically included by the Makefile,
* when wrpc-sw is build for wrc (node) -- as opposed to wrs (switch)
*/
#ifdef CONFIG_ARCH_RISCV
#define DEV_BASE 0x100000
#elif defined CONFIG_ARCH_LM32
#define DEV_BASE 0x40000
#else
#error (Wrong Arch!)
#endif
/* Fixed base addresses */
#define BASE_MINIC (DEV_BASE + 0x000)
#define BASE_EP (DEV_BASE + 0x100)
#define BASE_SOFTPLL (DEV_BASE + 0x200)
#define BASE_PPS_GEN (DEV_BASE + 0x300)
#define BASE_SYSCON (DEV_BASE + 0x400)
#define BASE_UART (DEV_BASE + 0x500)
#define BASE_ONEWIRE (DEV_BASE + 0x600)
#define BASE_WDIAGS_PRIV (DEV_BASE + 0x900)
#define BASE_ETHERBONE_CFG (DEV_BASE + 0x8000)
/* Board-specific parameters */
#define TICS_PER_SECOND 1000
/* WR Core system/CPU clock frequency in Hz */
#define CPU_CLOCK 62500000ULL
/* WR Reference clock period (picoseconds) and frequency (Hz) */
/* CLB_V4 has GENERIC_PHY_16BIT */
#define NS_PER_CLOCK 16
#define REF_CLOCK_PERIOD_PS 16000
#define REF_CLOCK_FREQ_HZ 62500000
/* Maximum number of simultaneously created sockets */
#define NET_MAX_SOCKETS 12
/* Socket buffer size, determines the max. RX packet size */
#define NET_MAX_SKBUF_SIZE 512
/* Number of auxillary clock channels - usually equal to the number of FMCs */
#define NUM_AUX_CLOCKS 1
/* spll parameter that are board-specific */
/* CLB_V4 has GENERIC_PHY_16BIT */
#define BOARD_DIVIDE_DMTD_CLOCKS 0
/* CLB_V4 uses CRYSTEC_CVPD992 for Helper and Main VCXO */
#define MAIN_CRYSTEK_CVPD922 1
#define HELPER_CRYSTEK_CVPD922 1
#define BOARD_MAX_CHAN_REF 1
#define BOARD_MAX_CHAN_AUX 2
#define BOARD_MAX_PTRACKERS 1
#undef CONFIG_DISALLOW_LONG_DIVISION
#define BOARD_USE_EVENTS 0
#define BOARD_MAX_CONSOLE_DEVICES (1 + HAS_NETCONSOLE + HAS_PUTS_SYSLOG)
#define CONSOLE_UART_BAUDRATE 115200
#define FMC_EEPROM_ADR 0x50
#define SDBFS_REC 5
#define EEPROM_STORAGE 1
void sdb_find_devices(void);
void sdb_print_devices(void);
extern int phy_calibration_poll(void);
extern void phy_calibration_init(void);
extern int phy_calibration_done(void);
extern void phy_calibration_disable(void);
#endif /* __BOARD_WRC_H */
This diff is collapsed.
#
# Automatically generated file; DO NOT EDIT.
# WR PTP Core software configuration
#
# CONFIG_ARCH_LM32 is not set
CONFIG_ARCH_RISCV=y
# CONFIG_RISCV_COMP_INSTR is not set
# CONFIG_TARGET_GENERIC_PHY_8BIT is not set
# CONFIG_TARGET_GENERIC_PHY_16BIT is not set
# CONFIG_TARGET_WR_SWITCH is not set
# CONFIG_TARGET_AFCZ_V2 is not set
# CONFIG_TARGET_ERTM14 is not set
# CONFIG_TARGET_SIS8300KU is not set
# CONFIG_TARGET_SPEC7 is not set
CONFIG_TARGET_CLB_V2=y
# CONFIG_TARGET_CLB_V3 is not set
# CONFIG_TARGET_CLB_V4 is not set
# CONFIG_TARGET_PXIE_FMC is not set
# CONFIG_TARGET_WR2RF_VME is not set
CONFIG_WR_NODE=y
CONFIG_STACKSIZE=2048
CONFIG_PRINT_BUFSIZE=256
CONFIG_RAMSIZE=131072
CONFIG_TEMP_POLL_INTERVAL=15
CONFIG_TEMP_HIGH_THRESHOLD=70
CONFIG_TEMP_HIGH_RAPPEL=60
# CONFIG_VLAN is not set
CONFIG_VLAN_NR=0
CONFIG_VLAN_1_FOR_CLASS7=0
CONFIG_VLAN_2_FOR_CLASS7=0
CONFIG_VLAN_FOR_CLASS6=0
# CONFIG_HOST_PROCESS is not set
CONFIG_EMBEDDED_NODE=y
CONFIG_WRPC_PPSI=y
CONFIG_LATENCY_ETHTYPE=291
# CONFIG_IP is not set
# CONFIG_CMD_CONFIG is not set
CONFIG_BUILD_INIT=y
CONFIG_INIT_COMMAND="vlan off;ptp stop;sfp match;mode slave;ptp start"
CONFIG_HAS_BUILD_INIT=1
CONFIG_HAS_FLASH_INIT=1
CONFIG_FLASH_INIT=y
# CONFIG_AUX_DIAG is not set
# CONFIG_CMD_CALIBRATION_SHOW is not set
# CONFIG_WR_DIAG is not set
# CONFIG_WR_NODE_SIM is not set
CONFIG_ABSCAL=y
# CONFIG_LLDP is not set
# CONFIG_CMD_REFRESH is not set
# CONFIG_CMD_PPS is not set
# CONFIG_CMD_SFP_INFO is not set
# CONFIG_SFP_DOM is not set
# CONFIG_CMD_LEAPSEC is not set
# CONFIG_CMD_PTP_ADV is not set
CONFIG_TEMP_SENSORS=y
# CONFIG_GENERIC_SENSORS is not set
CONFIG_W1=y
CONFIG_W1_TEMP=y
# CONFIG_W1_EEPROM is not set
# CONFIG_TRACE_MSGS is not set
CONFIG_TRACE_ALL=0
CONFIG_TRACE_MAIN=0
CONFIG_TRACE_STORAGE=0
CONFIG_TRACE_DEVICES=0
CONFIG_TRACE_BOARD=0
CONFIG_TRACE_MAC=0
CONFIG_TRACE_PHY=0
#
# wrpc-sw is tainted if you change the following options
#
# CONFIG_DEVELOPER is not set
CONFIG_LTO=y
# CONFIG_PRINTF_XINT is not set
CONFIG_PRINTF_FULL=y
# CONFIG_PRINTF_MINI is not set
# CONFIG_PRINTF_NONE is not set
#
# PPSI config
#
CONFIG_ARCH="wrpc"
CONFIG_ARCH_CFLAGS=""
CONFIG_ARCH_LDFLAGS=""
#
# Options
#
#
# PTP Protocol Options
#
CONFIG_E2E=y
# CONFIG_P2P is not set
CONFIG_E2E_ONLY=y
CONFIG_HAS_P2P=0
# CONFIG_PTP_OVERWRITE_BASIC_ATTRIBUTES is not set
# CONFIG_PTP_OPT_OVERWRITE_ATTRIBUTES is not set
CONFIG_LEAP_SECONDS_VAL=37
#
# Enabled profiles
#
CONFIG_PROFILE_WR=y
# CONFIG_PROFILE_HA is not set
# CONFIG_PROFILE_CUSTOM is not set
CONFIG_PROFILE_PTP=y
CONFIG_HAS_EXT_WR=1
CONFIG_HAS_EXT_L1SYNC=0
CONFIG_HAS_EXT_NONE=0
CONFIG_HAS_PROFILE_PTP=1
CONFIG_HAS_PROFILE_HA=0
CONFIG_HAS_PROFILE_WR=1
CONFIG_HAS_PROFILE_CUSTOM=0
CONFIG_VLAN_ARRAY_SIZE=0
# CONFIG_PPSI_ASSERT is not set
CONFIG_NR_FOREIGN_RECORDS=1
CONFIG_SINGLE_FMASTER=y
CONFIG_NR_PORTS=1
CONFIG_NR_INSTANCES_PER_PORT=1
#
# Code optimization
#
CONFIG_CODEOPT_ENABLED=y
CONFIG_SINGLE_INSTANCE_PER_PORT=y
CONFIG_SINGLE_INSTANCE=y
CONFIG_SINGLE_PORT=y
# CONFIG_CODEOPT_SINGLE_PORT is not set
# CONFIG_CODEOPT_SINGLE_FMASTER is not set
# CONFIG_CODEOPT_SINGLE_INSTANCE_PER_PORT is not set
CONFIG_CODEOPT_WRPC_SIZE=y
CONFIG_CODEOPT_EXT_PORT_CONF_FORCE_DISABLED=y
CONFIG_CODEOPT_SO_FORCE_DISABLED=y
CONFIG_CODEOPT_MO_FORCE_DISABLED=y
CONFIG_CODEOPT_EPC_SO_DISABLED=y
CONFIG_OPTIMIZATION="-Os -ggdb"
# CONFIG_FAULT_INJECTION_MECHANISM is not set
# CONFIG_NO_PTPDUMP is not set
CONFIG_HAS_FAULT_INJECTION_MECHANISM=0
CONFIG_HAS_WRPC_FAULTS=0
CONFIG_HAS_CODEOPT_SINGLE_FMASTER=0
CONFIG_HAS_CODEOPT_SINGLE_PORT=0
CONFIG_HAS_CODEOPT_SINGLE_INSTANCE_PER_PORT=0
CONFIG_HAS_CODEOPT_CODEOPT_WRPC_SIZE=1
CONFIG_HAS_CODEOPT_EXT_PORT_CONF_FORCE_DISABLED=1
CONFIG_HAS_CODEOPT_SO_FORCE_DISABLED=1
CONFIG_HAS_CODEOPT_MO_FORCE_DISABLED=1
CONFIG_HAS_CODEOPT_EPC_ENABLED=0
CONFIG_HAS_CODEOPT_SO_ENABLED=0
CONFIG_ARCH_IS_WRS=0
CONFIG_ARCH_IS_WRPC=1
CONFIG_HAS_PPSI_ASSERT=0
#
# Automatically generated file; DO NOT EDIT.
# WR PTP Core software configuration
#
# CONFIG_ARCH_LM32 is not set
CONFIG_ARCH_RISCV=y
# CONFIG_RISCV_COMP_INSTR is not set
# CONFIG_TARGET_GENERIC_PHY_8BIT is not set
# CONFIG_TARGET_GENERIC_PHY_16BIT is not set
# CONFIG_TARGET_WR_SWITCH is not set
# CONFIG_TARGET_AFCZ_V2 is not set
# CONFIG_TARGET_ERTM14 is not set
# CONFIG_TARGET_SIS8300KU is not set
# CONFIG_TARGET_SPEC7 is not set
# CONFIG_TARGET_CLB_V2 is not set
CONFIG_TARGET_CLB_V3=y
# CONFIG_TARGET_CLB_V4 is not set
# CONFIG_TARGET_PXIE_FMC is not set
# CONFIG_TARGET_WR2RF_VME is not set
CONFIG_WR_NODE=y
CONFIG_STACKSIZE=2048
CONFIG_PRINT_BUFSIZE=256
CONFIG_RAMSIZE=131072
CONFIG_TEMP_POLL_INTERVAL=15
CONFIG_TEMP_HIGH_THRESHOLD=70
CONFIG_TEMP_HIGH_RAPPEL=60
# CONFIG_VLAN is not set
CONFIG_VLAN_NR=0
CONFIG_VLAN_1_FOR_CLASS7=0
CONFIG_VLAN_2_FOR_CLASS7=0
CONFIG_VLAN_FOR_CLASS6=0
# CONFIG_HOST_PROCESS is not set
CONFIG_EMBEDDED_NODE=y
CONFIG_WRPC_PPSI=y
CONFIG_LATENCY_ETHTYPE=291
# CONFIG_IP is not set
# CONFIG_CMD_CONFIG is not set
CONFIG_BUILD_INIT=y
CONFIG_INIT_COMMAND="vlan off;ptp stop;sfp match;mode slave;ptp start"
CONFIG_HAS_BUILD_INIT=1
CONFIG_HAS_FLASH_INIT=1
CONFIG_FLASH_INIT=y
# CONFIG_AUX_DIAG is not set
# CONFIG_CMD_CALIBRATION_SHOW is not set
# CONFIG_WR_DIAG is not set
# CONFIG_WR_NODE_SIM is not set
CONFIG_ABSCAL=y
# CONFIG_LLDP is not set
# CONFIG_CMD_REFRESH is not set
# CONFIG_CMD_PPS is not set
# CONFIG_CMD_SFP_INFO is not set
# CONFIG_SFP_DOM is not set
# CONFIG_CMD_LEAPSEC is not set
# CONFIG_CMD_PTP_ADV is not set
CONFIG_TEMP_SENSORS=y
# CONFIG_GENERIC_SENSORS is not set
CONFIG_W1=y
CONFIG_W1_TEMP=y
# CONFIG_W1_EEPROM is not set
# CONFIG_TRACE_MSGS is not set
CONFIG_TRACE_ALL=0
CONFIG_TRACE_MAIN=0
CONFIG_TRACE_STORAGE=0
CONFIG_TRACE_DEVICES=0
CONFIG_TRACE_BOARD=0
CONFIG_TRACE_MAC=0
CONFIG_TRACE_PHY=0
#
# wrpc-sw is tainted if you change the following options
#
# CONFIG_DEVELOPER is not set
CONFIG_LTO=y
# CONFIG_PRINTF_XINT is not set
CONFIG_PRINTF_FULL=y
# CONFIG_PRINTF_MINI is not set
# CONFIG_PRINTF_NONE is not set
#
# PPSI config
#
CONFIG_ARCH="wrpc"
CONFIG_ARCH_CFLAGS=""
CONFIG_ARCH_LDFLAGS=""
#
# Options
#
#
# PTP Protocol Options
#
CONFIG_E2E=y
# CONFIG_P2P is not set
CONFIG_E2E_ONLY=y
CONFIG_HAS_P2P=0
# CONFIG_PTP_OVERWRITE_BASIC_ATTRIBUTES is not set
# CONFIG_PTP_OPT_OVERWRITE_ATTRIBUTES is not set
CONFIG_LEAP_SECONDS_VAL=37
#
# Enabled profiles
#
CONFIG_PROFILE_WR=y
# CONFIG_PROFILE_HA is not set
# CONFIG_PROFILE_CUSTOM is not set
CONFIG_PROFILE_PTP=y
CONFIG_HAS_EXT_WR=1
CONFIG_HAS_EXT_L1SYNC=0
CONFIG_HAS_EXT_NONE=0
CONFIG_HAS_PROFILE_PTP=1
CONFIG_HAS_PROFILE_HA=0
CONFIG_HAS_PROFILE_WR=1
CONFIG_HAS_PROFILE_CUSTOM=0
CONFIG_VLAN_ARRAY_SIZE=0
# CONFIG_PPSI_ASSERT is not set
CONFIG_NR_FOREIGN_RECORDS=1
CONFIG_SINGLE_FMASTER=y
CONFIG_NR_PORTS=1
CONFIG_NR_INSTANCES_PER_PORT=1
#
# Code optimization
#
CONFIG_CODEOPT_ENABLED=y
CONFIG_SINGLE_INSTANCE_PER_PORT=y
CONFIG_SINGLE_INSTANCE=y
CONFIG_SINGLE_PORT=y
# CONFIG_CODEOPT_SINGLE_PORT is not set
# CONFIG_CODEOPT_SINGLE_FMASTER is not set
# CONFIG_CODEOPT_SINGLE_INSTANCE_PER_PORT is not set
CONFIG_CODEOPT_WRPC_SIZE=y
CONFIG_CODEOPT_EXT_PORT_CONF_FORCE_DISABLED=y
CONFIG_CODEOPT_SO_FORCE_DISABLED=y
CONFIG_CODEOPT_MO_FORCE_DISABLED=y
CONFIG_CODEOPT_EPC_SO_DISABLED=y
CONFIG_OPTIMIZATION="-Os -ggdb"
# CONFIG_FAULT_INJECTION_MECHANISM is not set
# CONFIG_NO_PTPDUMP is not set
CONFIG_HAS_FAULT_INJECTION_MECHANISM=0
CONFIG_HAS_WRPC_FAULTS=0
CONFIG_HAS_CODEOPT_SINGLE_FMASTER=0
CONFIG_HAS_CODEOPT_SINGLE_PORT=0
CONFIG_HAS_CODEOPT_SINGLE_INSTANCE_PER_PORT=0
CONFIG_HAS_CODEOPT_CODEOPT_WRPC_SIZE=1
CONFIG_HAS_CODEOPT_EXT_PORT_CONF_FORCE_DISABLED=1
CONFIG_HAS_CODEOPT_SO_FORCE_DISABLED=1
CONFIG_HAS_CODEOPT_MO_FORCE_DISABLED=1
CONFIG_HAS_CODEOPT_EPC_ENABLED=0
CONFIG_HAS_CODEOPT_SO_ENABLED=0
CONFIG_ARCH_IS_WRS=0
CONFIG_ARCH_IS_WRPC=1
CONFIG_HAS_PPSI_ASSERT=0
#
# Automatically generated file; DO NOT EDIT.
# WR PTP Core software configuration
#
# CONFIG_ARCH_LM32 is not set
CONFIG_ARCH_RISCV=y
# CONFIG_RISCV_COMP_INSTR is not set
# CONFIG_TARGET_GENERIC_PHY_8BIT is not set
# CONFIG_TARGET_GENERIC_PHY_16BIT is not set
# CONFIG_TARGET_WR_SWITCH is not set
# CONFIG_TARGET_AFCZ_V2 is not set
# CONFIG_TARGET_ERTM14 is not set
# CONFIG_TARGET_SIS8300KU is not set
# CONFIG_TARGET_SPEC7 is not set
# CONFIG_TARGET_CLB_V2 is not set
# CONFIG_TARGET_CLB_V3 is not set
CONFIG_TARGET_CLB_V4=y
# CONFIG_TARGET_PXIE_FMC is not set
# CONFIG_TARGET_WR2RF_VME is not set
CONFIG_WR_NODE=y
CONFIG_STACKSIZE=2048
CONFIG_PRINT_BUFSIZE=256
CONFIG_RAMSIZE=131072
CONFIG_TEMP_POLL_INTERVAL=15
CONFIG_TEMP_HIGH_THRESHOLD=70
CONFIG_TEMP_HIGH_RAPPEL=60
# CONFIG_VLAN is not set
CONFIG_VLAN_NR=0
CONFIG_VLAN_1_FOR_CLASS7=0
CONFIG_VLAN_2_FOR_CLASS7=0
CONFIG_VLAN_FOR_CLASS6=0
# CONFIG_HOST_PROCESS is not set
CONFIG_EMBEDDED_NODE=y
CONFIG_WRPC_PPSI=y
CONFIG_LATENCY_ETHTYPE=291
# CONFIG_IP is not set
# CONFIG_CMD_CONFIG is not set
CONFIG_BUILD_INIT=y
CONFIG_INIT_COMMAND="vlan off;ptp stop;sfp match;mode slave;ptp start"
CONFIG_HAS_BUILD_INIT=1
CONFIG_HAS_FLASH_INIT=1
CONFIG_FLASH_INIT=y
# CONFIG_AUX_DIAG is not set
# CONFIG_CMD_CALIBRATION_SHOW is not set
# CONFIG_WR_DIAG is not set
# CONFIG_WR_NODE_SIM is not set
CONFIG_ABSCAL=y
# CONFIG_LLDP is not set
# CONFIG_CMD_REFRESH is not set
# CONFIG_CMD_PPS is not set
# CONFIG_CMD_SFP_INFO is not set
# CONFIG_SFP_DOM is not set
# CONFIG_CMD_LEAPSEC is not set
# CONFIG_CMD_PTP_ADV is not set
CONFIG_TEMP_SENSORS=y
# CONFIG_GENERIC_SENSORS is not set
CONFIG_W1=y
CONFIG_W1_TEMP=y
# CONFIG_W1_EEPROM is not set
# CONFIG_TRACE_MSGS is not set
CONFIG_TRACE_ALL=0
CONFIG_TRACE_MAIN=0
CONFIG_TRACE_STORAGE=0
CONFIG_TRACE_DEVICES=0
CONFIG_TRACE_BOARD=0
CONFIG_TRACE_MAC=0
CONFIG_TRACE_PHY=0
#
# wrpc-sw is tainted if you change the following options
#
# CONFIG_DEVELOPER is not set
CONFIG_LTO=y
# CONFIG_PRINTF_IS_XINT is not set
# CONFIG_PRINTF_IS_FULL is not set
# CONFIG_PRINTF_IS_MINI is not set
# CONFIG_PRINTF_IS_NONE is not set
# CONFIG_PRINTF_XINT is not set
CONFIG_PRINTF_FULL=y
# CONFIG_PRINTF_MINI is not set
# CONFIG_PRINTF_NONE is not set
#
# PPSI config
#
CONFIG_ARCH="wrpc"
CONFIG_ARCH_CFLAGS=""
CONFIG_ARCH_LDFLAGS=""
#
# Options
#
#
# PTP Protocol Options
#
CONFIG_E2E=y
# CONFIG_P2P is not set
CONFIG_E2E_ONLY=y
CONFIG_HAS_P2P=0
# CONFIG_PTP_OVERWRITE_BASIC_ATTRIBUTES is not set
# CONFIG_PTP_OPT_OVERWRITE_ATTRIBUTES is not set
CONFIG_LEAP_SECONDS_VAL=37
#
# Enabled profiles
#
CONFIG_PROFILE_WR=y
# CONFIG_PROFILE_HA is not set
# CONFIG_PROFILE_CUSTOM is not set
CONFIG_PROFILE_PTP=y
CONFIG_HAS_EXT_WR=1
CONFIG_HAS_EXT_L1SYNC=0
CONFIG_HAS_EXT_NONE=0
CONFIG_HAS_PROFILE_PTP=1
CONFIG_HAS_PROFILE_HA=0
CONFIG_HAS_PROFILE_WR=1
CONFIG_HAS_PROFILE_CUSTOM=0
CONFIG_VLAN_ARRAY_SIZE=0
# CONFIG_PPSI_ASSERT is not set
CONFIG_NR_FOREIGN_RECORDS=1
CONFIG_SINGLE_FMASTER=y
CONFIG_NR_PORTS=1
CONFIG_NR_INSTANCES_PER_PORT=1
#
# Code optimization
#
CONFIG_CODEOPT_ENABLED=y
CONFIG_SINGLE_INSTANCE_PER_PORT=y
CONFIG_SINGLE_INSTANCE=y
CONFIG_SINGLE_PORT=y
# CONFIG_CODEOPT_SINGLE_PORT is not set
# CONFIG_CODEOPT_SINGLE_FMASTER is not set
# CONFIG_CODEOPT_SINGLE_INSTANCE_PER_PORT is not set
CONFIG_CODEOPT_WRPC_SIZE=y
CONFIG_CODEOPT_EXT_PORT_CONF_FORCE_DISABLED=y
CONFIG_CODEOPT_SO_FORCE_DISABLED=y
CONFIG_CODEOPT_MO_FORCE_DISABLED=y
CONFIG_CODEOPT_EPC_SO_DISABLED=y
CONFIG_OPTIMIZATION="-Os -ggdb"
# CONFIG_FAULT_INJECTION_MECHANISM is not set
# CONFIG_NO_PTPDUMP is not set
CONFIG_HAS_FAULT_INJECTION_MECHANISM=0
CONFIG_HAS_WRPC_FAULTS=0
CONFIG_HAS_CODEOPT_SINGLE_FMASTER=0
CONFIG_HAS_CODEOPT_SINGLE_PORT=0
CONFIG_HAS_CODEOPT_SINGLE_INSTANCE_PER_PORT=0
CONFIG_HAS_CODEOPT_CODEOPT_WRPC_SIZE=1
CONFIG_HAS_CODEOPT_EXT_PORT_CONF_FORCE_DISABLED=1
CONFIG_HAS_CODEOPT_SO_FORCE_DISABLED=1
CONFIG_HAS_CODEOPT_MO_FORCE_DISABLED=1
CONFIG_HAS_CODEOPT_EPC_ENABLED=0
CONFIG_HAS_CODEOPT_SO_ENABLED=0
CONFIG_ARCH_IS_WRS=0
CONFIG_ARCH_IS_WRPC=1
CONFIG_HAS_PPSI_ASSERT=0
......@@ -28,6 +28,12 @@
# include "boards/sis8300ku/board.h"
#elif defined(CONFIG_TARGET_SPEC7)
# include "boards/spec7/board.h"
#elif defined(CONFIG_TARGET_CLB_V2)
# include "boards/clbv2/board.h"
#elif defined(CONFIG_TARGET_CLB_V3)
# include "boards/clbv3/board.h"
#elif defined(CONFIG_TARGET_CLB_V4)
# include "boards/clbv4/board.h"
#elif defined(CONFIG_TARGET_PXIE_FMC)
# include "boards/pxie-fmc/board.h"
#elif defined(CONFIG_TARGET_WR2RF_VME)
......
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