Add HPSEC to Kconfig

57f015ae · Peter Jansweijer · 909f03a5 · 57f015ae · 57f015ae
Commit 57f015ae authored Apr 15, 2022 by Peter Jansweijer
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Showing with 8 additions and 5 deletions

Kconfig Kconfig +6 -0

board.c boards/spec7/board.c +2 -5

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--- a/Kconfig
+++ b/Kconfig
@@ -66,6 +66,12 @@ config TARGET_SPEC7
 	help
 	  Simple PCIe FMC carrier 7 (Zynq-7000)

+config TARGET_HPSEC
+	depends on TARGET_SPEC7
+	bool "HPSEC"
+	help
+	  SPEC7 (Zynq-7000) with High Precision Secondairy External Clock
+
 config TARGET_PXIE_FMC
 	bool "ZU7 PXIe FMC Carrier"
 	help

--- a/boards/spec7/board.c
+++ b/boards/spec7/board.c
@@ -63,9 +63,6 @@ static struct ltc695x_config ltc6950_ext_10mhz_config =
 timeout_t pll_even_odd_timeout;
 timeout_t pll_sync_timeout;

-//#define CONFIG_HPSEC_GM
-#undef CONFIG_HPSEC_GM
-
 //volatile struct softpll_state softpll;

 void board_pre_pll_lock(int wrc_ptp_mode)
@@ -78,7 +75,7 @@ void board_pre_pll_lock(int wrc_ptp_mode)
        case WRC_MODE_GM || WRC_MODE_ABSCAL:
            // Default reference design locks local VCXO to external 10 MHz
            pll_wr_mode = PLL_WR_MODE_SLAVE;
-#if defined(CONFIG_HPSEC_GM)
+#if defined(CONFIG_TARGET_HPSEC)
            // When HPSEC is used in GM mode then HPSEC locks to external
            // 10 MHz via LTC6950 and WRC_MODE *must* be free running master.
            // Note: WRC_MODE_GM tries to align the local VCXO with the
@@ -88,7 +85,7 @@ void board_pre_pll_lock(int wrc_ptp_mode)
            break;
        case WRC_MODE_MASTER:
            pll_wr_mode = PLL_WR_MODE_MASTER;
-#if defined(CONFIG_HPSEC_GM)
+#if defined(CONFIG_TARGET_HPSEC)
            // When HPSEC is used in GM mode then HPSEC locks to external
            // 10 MHz via LTC6950 and WRC_MODE *must* be free running master.
            pll_wr_mode = PLL_WR_MODE_GM;