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Software for White Rabbit PTP Core
Commit 53a7289b authored by Alessandro Rubini's avatar Alessandro Rubini
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general: remove TRACE 

The misleading TRACE thing was only used in wrs builds, and expanded
to pp_printf.

Considering we don't want to remove messages from the softpll in wrpc,
this commit turns trace onto pp_printf.
Signed-off-by: Alessandro Rubini's avatarAlessandro Rubini <rubini@gnudd.com>
parent d2aa401a
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Showing with 15 additions and 16 deletions
dev/ad9516.c
View file @ 53a7289b
...@@ -169,7 +169,7 @@ static int ad9516_set_output_divider(int output, int ratio, int phase_offset) ...@@ -169,7 +169,7 @@ static int ad9516_set_output_divider(int output, int ratio, int phase_offset)
uint16_t base = ((output - 6) / 2) * 0x5 + 0x199; uint16_t base = ((output - 6) / 2) * 0x5 + 0x199;
TRACE("Output [divider %d]: %d ratio: %d base %x lc %d hc %d\n", secondary, output, ratio, base, lcycles ,hcycles); pp_printf("Output [divider %d]: %d ratio: %d base %x lc %d hc %d\n", secondary, output, ratio, base, lcycles ,hcycles);
if(!secondary) if(!secondary)
{ {
...@@ -222,7 +222,7 @@ static void ad9516_sync_outputs(void) ...@@ -222,7 +222,7 @@ static void ad9516_sync_outputs(void)
int ad9516_init(int scb_version) int ad9516_init(int scb_version)
{ {
TRACE("Initializing AD9516 PLL...\n"); pp_printf("Initializing AD9516 PLL...\n");
oc_spi_init((void *)BASE_SPI); oc_spi_init((void *)BASE_SPI);
...@@ -239,7 +239,7 @@ int ad9516_init(int scb_version) ...@@ -239,7 +239,7 @@ int ad9516_init(int scb_version)
/* Check the presence of the chip */ /* Check the presence of the chip */
if (ad9516_read_reg(0x3) != 0xc3) { if (ad9516_read_reg(0x3) != 0xc3) {
TRACE("Error: AD9516 PLL not responding.\n"); pp_printf("Error: AD9516 PLL not responding.\n");
return -1; return -1;
} }
...@@ -279,7 +279,7 @@ int ad9516_init(int scb_version) ...@@ -279,7 +279,7 @@ int ad9516_init(int scb_version)
ad9516_sync_outputs(); ad9516_sync_outputs();
ad9516_set_vco_divider(3); ad9516_set_vco_divider(3);
TRACE("AD9516 locked.\n"); pp_printf("AD9516 locked.\n");
gpio_out(GPIO_SYS_CLK_SEL, 1); /* switch the system clock to the PLL reference */ gpio_out(GPIO_SYS_CLK_SEL, 1); /* switch the system clock to the PLL reference */
gpio_out(GPIO_PERIPH_RESET_N, 0); /* reset all peripherals which use AD9516-provided clocks */ gpio_out(GPIO_PERIPH_RESET_N, 0); /* reset all peripherals which use AD9516-provided clocks */
......
include/trace.h
View file @ 53a7289b
...@@ -15,7 +15,6 @@ ...@@ -15,7 +15,6 @@
#else /* WR_SWITCH */ #else /* WR_SWITCH */
#include <pp-printf.h> #include <pp-printf.h>
#define TRACE(...) pp_printf(__VA_ARGS__)
#define TRACE_DEV(...) pp_printf(__VA_ARGS__) #define TRACE_DEV(...) pp_printf(__VA_ARGS__)
#endif /* node/switch */ #endif /* node/switch */
......
ipc/rt_ipc.c
View file @ 53a7289b
...@@ -40,7 +40,7 @@ static void clear_state(void) ...@@ -40,7 +40,7 @@ static void clear_state(void)
/* Sets the phase setpoint on a given channel */ /* Sets the phase setpoint on a given channel */
int rts_adjust_phase(int channel, int32_t phase_setpoint) int rts_adjust_phase(int channel, int32_t phase_setpoint)
{ {
// TRACE("Adjusting phase: ref channel %d, setpoint=%d ps.\n", channel, phase_setpoint); // pp_printf("Adjusting phase: ref channel %d, setpoint=%d ps.\n", channel, phase_setpoint);
spll_set_phase_shift(0, phase_setpoint); spll_set_phase_shift(0, phase_setpoint);
pstate.channels[channel].phase_setpoint = phase_setpoint; pstate.channels[channel].phase_setpoint = phase_setpoint;
return 0; return 0;
...@@ -69,7 +69,7 @@ int rts_set_mode(int mode) ...@@ -69,7 +69,7 @@ int rts_set_mode(int mode)
for(i=0;options[i].desc != NULL;i++) for(i=0;options[i].desc != NULL;i++)
if(mode == options[i].mode_rt) if(mode == options[i].mode_rt)
{ {
TRACE("RT: Setting mode to %s.\n", options[i].desc); pp_printf("RT: Setting mode to %s.\n", options[i].desc);
if(options[i].do_init) if(options[i].do_init)
spll_init(options[i].mode_spll, 0, 1); spll_init(options[i].mode_spll, 0, 1);
else else
...@@ -84,12 +84,12 @@ int rts_lock_channel(int channel, int priority) ...@@ -84,12 +84,12 @@ int rts_lock_channel(int channel, int priority)
{ {
if(pstate.mode != RTS_MODE_BC) if(pstate.mode != RTS_MODE_BC)
{ {
TRACE("trying to lock while not in slave mode,..\n"); pp_printf("trying to lock while not in slave mode,..\n");
return -1; return -1;
} }
TRACE("RT [slave]: Locking to: %d (prio %d)\n", channel, priority); pp_printf("RT [slave]: Locking to: %d (prio %d)\n", channel, priority);
spll_init(SPLL_MODE_SLAVE, channel, 0); spll_init(SPLL_MODE_SLAVE, channel, 0);
pstate.current_ref = channel; pstate.current_ref = channel;
......
wrs_main.c
View file @ 53a7289b
...@@ -34,16 +34,16 @@ int main(void) ...@@ -34,16 +34,16 @@ int main(void)
stats.start_cnt++; stats.start_cnt++;
_endram = ENDRAM_MAGIC; _endram = ENDRAM_MAGIC;
uart_init_hw(); uart_init_hw();
TRACE("\n"); pp_printf("\n");
TRACE("WR Switch Real Time Subsystem (c) CERN 2011 - 2014\n"); pp_printf("WR Switch Real Time Subsystem (c) CERN 2011 - 2014\n");
TRACE("Revision: %s, built: %s %s.\n", pp_printf("Revision: %s, built: %s %s.\n",
build_revision, build_date, build_time); build_revision, build_date, build_time);
TRACE("SCB version: %d. %s\n", scb_ver,(scb_ver>=34)?"10 MHz SMC Output.":"" ); pp_printf("SCB version: %d. %s\n", scb_ver,(scb_ver>=34)?"10 MHz SMC Output.":"" );
TRACE("Start counter %d\n", stats.start_cnt); pp_printf("Start counter %d\n", stats.start_cnt);
TRACE("--\n"); pp_printf("--\n");
if (stats.start_cnt > 1) { if (stats.start_cnt > 1) {
TRACE("!!spll does not work after restart!!\n"); pp_printf("!!spll does not work after restart!!\n");
/* for sure problem is in calling second time ad9516_init, /* for sure problem is in calling second time ad9516_init,
* but not only */ * but not only */
} }
......
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