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Software for White Rabbit PTP Core
Commits
4beb8b18
Commit
4beb8b18
authored
Apr 19, 2022
by
Peter Jansweijer
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spec7 (default) and hpsec gain schedule
parent
a2a46ba6
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2 changed files
with
37 additions
and
5 deletions
+37
-5
board.c
boards/spec7/board.c
+33
-3
spll_main.c
softpll/spll_main.c
+4
-2
No files found.
boards/spec7/board.c
View file @
4beb8b18
...
...
@@ -29,9 +29,7 @@
#include "dev/endpoint.h"
#include "storage.h"
#include <wrc_ptp.h>
#include "spll_defs.h"
#include "spll_common.h"
#include "hw/pps_gen_regs.h"
#include "softpll_ng.h"
struct
spec7_board
board
;
...
...
@@ -57,6 +55,8 @@ static struct ltc695x_config ltc6950_base_config =
static
struct
ltc695x_config
ltc6950_ext_10mhz_config
=
#include "configs/ltc6950_ext_10mhz_config.h"
spll_gain_schedule_t
spll_main_ocxo_gain_sched
;
#define PLL_EVEN_ODD_TIMEOUT_MS 10000
#define PLL_SYNC_TIMEOUT_MS 4000
...
...
@@ -65,6 +65,33 @@ timeout_t pll_sync_timeout;
//volatile struct softpll_state softpll;
static
void
spec7_spll_setup
(
void
)
{
/* configure a suitable PI gain schedule for the SoftPLL: */
spll_gain_schedule_t
*
gs
=
&
spll_main_ocxo_gain_sched
;
/* we start with ~100 Hz bandwidth to make it lock reasonably fast */
gs
->
stages
[
0
].
kp
=
-
5500
;
gs
->
stages
[
0
].
ki
=
-
30
;
gs
->
stages
[
0
].
lock_samples
=
30000
;
gs
->
stages
[
0
].
shift
=
12
;
/* once it's locked, the loop bandwidth is switched to ~0.1 Hz to filter out WR link added phase noise */
gs
->
stages
[
1
].
kp
=
-
3000
;
gs
->
stages
[
1
].
ki
=
-
5
;
gs
->
stages
[
1
].
lock_samples
=
10000
;
gs
->
stages
[
1
].
shift
=
16
;
#if defined(CONFIG_TARGET_HPSEC)
gs
->
n_stages
=
2
;
// 2 stages: SPEC7 Crysteck => HPSEC Morion MV336
spll_set_gain_schedule
(
gs
);
#else
gs
->
n_stages
=
1
;
// 1 stage: SPEC7 Crysteck
//spll_set_gain_schedule( gs ); // Repair: Gain schedule keeps restarting in mode gm
#endif
}
void
board_pre_pll_lock
(
int
wrc_ptp_mode
)
{
int
pll_wr_mode
;
...
...
@@ -143,6 +170,9 @@ int spec7_init()
&
pin_pll_sck_o
,
100
);
/* Setup the SoftPLL for the OCXO we have */
spec7_spll_setup
();
ltc695x_init
(
&
board
.
ltc6950_pll
,
&
board
.
spi_ltc6950
);
// Reset the PLL (RES6950 clears itself)
...
...
softpll/spll_main.c
View file @
4beb8b18
...
...
@@ -116,7 +116,8 @@ static inline void mpll_handle_gain_schedule( struct spll_main_state *s )
s
->
ld
.
lock_changed
=
0
;
s
->
ld
.
locked
=
0
;
s
->
gain_sched
->
locked_d
=
0
;
}
board_dbg
(
"Gain schedule stage: %d, Kp: %d, ki: %d, shift: %d
\n
"
,
s
->
gain_sched
->
current_stage
,
stage
->
kp
,
stage
->
ki
,
stage
->
shift
);
}
s
->
gain_sched
->
locked_d
=
s
->
ld
.
locked
;
}
...
...
@@ -150,7 +151,8 @@ void mpll_start(struct spll_main_state *s)
s
->
pi
.
shift
=
s
->
gain_sched
->
stages
[
0
].
shift
;
s
->
ld
.
lock_samples
=
s
->
gain_sched
->
stages
[
0
].
lock_samples
;
s
->
ld
.
lock_cnt
=
0
;
}
board_dbg
(
"Gain schedule stage: 0, Kp: %d, ki: %d, shift: %d
\n
"
,
s
->
gain_sched
->
stages
[
0
].
kp
,
s
->
gain_sched
->
stages
[
0
].
ki
,
s
->
gain_sched
->
stages
[
0
].
shift
);
}
pi_init
((
spll_pi_t
*
)
&
s
->
pi
);
...
...
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