Commit 46d215eb authored by Peter Jansweijer's avatar Peter Jansweijer

try Morion MV336 Gain Schedule

parent b2161598
Pipeline #419 failed with stages
in 12 seconds
......@@ -34,6 +34,8 @@ static struct ltc6950_config ltc6950_base_config =
static struct ltc6950_config ltc6950_ext_10mhz_config =
#include "configs/ltc6950_ext_10mhz_config.h"
static spll_gain_schedule_t spll_main_ocxo_gain_sched;
#define PLL_EVEN_ODD_TIMEOUT_MS 10000
#define PLL_SYNC_TIMEOUT_MS 4000
......@@ -45,6 +47,43 @@ timeout_t pll_sync_timeout;
//volatile struct softpll_state softpll;
static void spec7_spll_setup(void)
{
/* configure a suitable PI gain schedule for the SoftPLL: */
spll_gain_schedule_t* gs= &spll_main_ocxo_gain_sched;
/* we start with ~100 Hz bandwidth to make it lock reasonably fast */
// SPEC7 Crystek
gs->stages[0].kp = -5500;
gs->stages[0].ki = -30;
gs->stages[0].lock_samples = 30000;
gs->stages[0].shift = 12;
// HPSEC Morion MV336
/*
gs->stages[0].kp = -4000 * 16;
gs->stages[0].ki = -5 * 16;
gs->stages[0].lock_samples = 30000;
gs->stages[0].shift = 16;
*/
/* once it's locked, the loop bandwidth is switched to ~0.1 Hz to filter out WR link added phase noise */
// SPEC7 Crystek
/*
gs->stages[1].kp = -1550;
gs->stages[1].ki = -5;
gs->stages[1].lock_samples = 10000;
gs->stages[1].shift = 12;
*/
// HPSEC Morion MV336
gs->stages[1].kp = -3000;
gs->stages[1].ki = -5;
gs->stages[1].lock_samples = 10000;
gs->stages[1].shift = 16;
gs->n_stages = 2;
spll_set_gain_schedule( gs );
}
void spec7_set_pll_wr_mode(int wrc_ptp_mode)
{
int pll_wr_mode;
......@@ -205,6 +244,9 @@ int spec7_init()
&pin_pll_sck_o,
100 );
/* Setup the SoftPLL for the OCXO we have */
spec7_spll_setup();
ltc6950_init(&board.ltc6950_pll, &board.spi_ltc6950);
// Reset the PLL (RES6950 clears itself)
......
......@@ -39,14 +39,15 @@ void mpll_init(struct spll_main_state *s, int id_ref,
s->pi.kp = 1100; // / 2;
s->pi.ki = 30; // / 2;
}
#elif defined(CONFIG_WR_NODE) && !defined(CONFIG_TARGET_SPEC7)
//#elif defined(CONFIG_WR_NODE) && !defined(CONFIG_TARGET_SPEC7)
#elif defined(CONFIG_WR_NODE)
s->pi.kp = -1100; // / 2;
s->pi.ki = -30; // / 2;
#elif defined(CONFIG_WR_NODE) && defined(CONFIG_TARGET_SPEC7)
//#elif defined(CONFIG_WR_NODE) && defined(CONFIG_TARGET_SPEC7)
// s->pi.kp = -800; // / 2;
// s->pi.ki = -10; // / 2;
s->pi.kp = -5500; // / 2;
s->pi.ki = -30; // / 2;
// s->pi.kp = -5500; // / 2;
// s->pi.ki = -30; // / 2;
#else
#error "Please set CONFIG for wr switch or wr node"
#endif
......@@ -59,7 +60,7 @@ void mpll_init(struct spll_main_state *s, int id_ref,
s->id_ref = id_ref;
s->id_out = id_out;
s->dac_index = id_out - spll_n_chan_ref;
pp_printf("Main PLL PI Values: Kp %i\t Ki%i\n",s->pi.kp,s->pi.ki);
//board_dbg("Main PLL PI Values: Kp %i\t Ki%i\n",s->pi.kp,s->pi.ki);
if( s->gain_sched )
{
......@@ -115,6 +116,7 @@ static inline void mpll_handle_gain_schedule( struct spll_main_state *s )
s->ld.lock_changed = 0;
s->ld.locked = 0;
s->gain_sched->locked_d = 0;
board_dbg("Gain schedule stage: %d, Kp: %d, ki: %d, shift: %d\n",s->gain_sched->current_stage, stage->kp,stage->ki, stage->shift);
}
s->gain_sched->locked_d = s->ld.locked;
......@@ -146,6 +148,7 @@ void mpll_start(struct spll_main_state *s)
s->pi.shift = s->gain_sched->stages[0].shift;
s->ld.lock_samples = s->gain_sched->stages[0].lock_samples;
s->ld.lock_cnt = 0;
board_dbg("Gain schedule stage: 0, Kp: %d, ki: %d, shift: %d\n",s->gain_sched->stages[0].kp,s->gain_sched->stages[0].ki,s->gain_sched->stages[0].shift);
}
......
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