boards/afcz: more clock & I2C diagnostics

45f4894c · Tomasz Wlostowski · 96757b24 · 45f4894c · 45f4894c
Commit 45f4894c authored Jul 28, 2020 by Tomasz Wlostowski
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Showing with 69 additions and 4 deletions

board.c boards/afcz/board.c +67 -4

board.h boards/afcz/board.h +2 -0

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--- a/boards/afcz/board.c
+++ b/boards/afcz/board.c
@@ -468,6 +468,8 @@ void set_main_dac( int value )

 const struct gpio_pin pin_rtm_4sfp_led_orange = { &board.gpio_rtm_main.gpio, 3 };
 const struct gpio_pin pin_rtm_4sfp_i2c_reset_n = { &board.gpio_rtm_main.gpio, 5 };
+const struct gpio_pin pin_rtm_4sfp_i2c_enable_n = { &board.gpio_rtm_main.gpio, 6 };
+const struct gpio_pin pin_rtm_4sfp_i2c_pgood_n = { &board.gpio_rtm_main.gpio, 4 };


 const struct gpio_pin pin_rtm_4sfp_sfp_tx_disable = { &board.gpio_rtm_sfp.gpio, 1 };
@@ -482,9 +484,27 @@ void sfp_setup()
 	pca9554_gpio_init( &board.gpio_rtm_main, &board.si57x.master, 0x20 ); // fixme : constants
 	pca9554_gpio_init( &board.gpio_rtm_sfp, &board.si57x.master, 0x22 ); // fixme : constants

+	gen_gpio_set_dir( &pin_rtm_4sfp_i2c_enable_n, 1);
+	gen_gpio_set_dir( &pin_rtm_4sfp_i2c_reset_n, 1);
+
+	gen_gpio_out( &pin_rtm_4sfp_i2c_enable_n, 0 );
 	gen_gpio_out( &pin_rtm_4sfp_i2c_reset_n, 0 );
 	gen_gpio_out( &pin_rtm_4sfp_i2c_reset_n, 1 );

+	gen_gpio_set_dir( &pin_rtm_4sfp_i2c_pgood_n, 0 );
+
+	int i;
+
+	for(i=0;i<5;i++)
+	{
+		pp_printf("blinky...\n");
+		gen_gpio_out( &pin_rtm_4sfp_led_orange, 1 );
+		timer_delay_ms(100);
+		gen_gpio_out( &pin_rtm_4sfp_led_orange, 0 );
+		timer_delay_ms(100);
+	}
+
+	pp_printf("Power_good_n: %d]n", gen_gpio_in( &pin_rtm_4sfp_i2c_pgood_n ) );

 	const int sfp_busses [] = 
 	{
@@ -497,15 +517,20 @@ void sfp_setup()
 		RTM_4SFP_MUX_SFP6,
 		-1
 	};
-	int i;

 	for( i = 0; sfp_busses[i] >= 0; i++ )
 	{
 		// select SFPx
 		tca9548_select_channels( &board.si57x.master, 0x74, 1 << sfp_busses[i] );

+	
 		gen_gpio_set_dir( &pin_rtm_4sfp_sfp_tx_disable, 1 );
 		gen_gpio_out( &pin_rtm_4sfp_sfp_tx_disable, 0 );
+
+		int rv_pca = bb_i2c_devprobe( &board.si57x.master, 0x22 );
+		int rv_sfp = bb_i2c_devprobe( &board.si57x.master, 0xa0 >> 1 );
+
+		pp_printf("Probe/init SFP%d: SFP found=%d PCA found=%d\n", sfp_busses[i], rv_sfp, rv_pca );
 	}


@@ -591,15 +616,53 @@ int wrc_board_early_init()
 	set_dmtd_dac(32767);
 	set_main_dac(32767);

+	ep_reset_phy();
+	afcz_check_clocks();
+
 // cross-check the REF and DDMTD clocks
-	pp_printf("Checking DDMTD and REF clock frequencies:\n");
-	check_vco_freq( AFCZ_CM_CHANNEL_CLK_DMTD, AFCZ_CM_CHANNEL_CLK_REF, set_dmtd_dac );
-	check_vco_freq( AFCZ_CM_CHANNEL_CLK_REF, AFCZ_CM_CHANNEL_CLK_DMTD, set_main_dac );
+
+/*	wb_cm_configure( &board.clk_mon, AFCZ_CM_CHANNEL_CLK_DMTD, 5, 1000000 );
+	wb_cm_set_ref_frequency( &board.clk_mon, CPU_CLOCK );
+	wb_cm_restart( &board.clk_mon );
+	timer_delay_ms(4000);
+	wb_cm_read(  &board.clk_mon );
+	wb_cm_show(  &board.clk_mon );
+	}*/

 #endif
 	return 0;
 }

+#define AFCZ_CLOCK_MON_TIMEOUT_MS 4000
+
+int afcz_check_clocks()
+{
+	wb_cm_configure( &board.clk_mon, AFCZ_CM_CHANNEL_CLK_SYS, 5, 10000000 );
+	wb_cm_set_ref_frequency( &board.clk_mon, CPU_CLOCK );
+	wb_cm_restart(&board.clk_mon);
+	int timeout_cntr = 0;
+
+	while( ! (wb_cm_read( &board.clk_mon ) & ( 1<< AFCZ_CM_CHANNEL_CLK_RX) ) )
+	{
+		timer_delay_ms(100);
+		timeout_cntr+=100;
+		if( timeout_cntr > AFCZ_CLOCK_MON_TIMEOUT_MS )
+		{
+			pp_printf("Can't get the PHY RX clock measurement. Aborting oscillator test.\n");
+			return -1;
+		}
+	}
+
+
+	pp_printf("Checking clocks: RX clock freq = %d Hz\n", board.clk_mon.freqs[ AFCZ_CM_CHANNEL_CLK_RX ]);
+	
+	pp_printf("Checking DDMTD and REF clock frequencies:\n");
+	check_vco_freq( AFCZ_CM_CHANNEL_CLK_DMTD, AFCZ_CM_CHANNEL_CLK_RX, set_dmtd_dac );
+	check_vco_freq( AFCZ_CM_CHANNEL_CLK_REF,  AFCZ_CM_CHANNEL_CLK_RX, set_main_dac );
+
+	return 0;
+}
+
 int wrc_board_init()
 {
 	/* initialize I2C bus */

--- a/boards/afcz/board.h
+++ b/boards/afcz/board.h
@@ -26,6 +26,8 @@
 #define BASE_CLOCK_MONITOR (BASE_AUXWB + 0xc0)

 #define AFCZ_CM_CHANNEL_CLK_PCB 0
+#define AFCZ_CM_CHANNEL_CLK_SYS 3
+#define AFCZ_CM_CHANNEL_CLK_RX 2
 #define AFCZ_CM_CHANNEL_CLK_REF 1
 #define AFCZ_CM_CHANNEL_CLK_DMTD 5