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Software for White Rabbit PTP Core
Commit 3f3a2b00 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski Committed by Grzegorz Daniluk
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snapshort for Greg 

Signed-off-by: 's avatarGrzegorz Daniluk <g.daniluk@elproma.com.pl>
parent 6025c47c
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Showing with 134 additions and 116 deletions
Makefile
View file @ 3f3a2b00
PLATFORM = lm32
OBJS_WRC = wrc_main.o dev/uart.o dev/endpoint.o dev/minic.o dev/pps_gen.o dev/syscon.o dev/softpll_ng.o lib/mprintf.o monitor/monitor.o dev/ep_pfilter.o dev/dna.o #dev/onewire.o dev/i2c.o #dev/eeprom.o
OBJS_WRC = wrc_main.o dev/uart.o dev/endpoint.o dev/minic.o dev/pps_gen.o dev/syscon.o dev/softpll_ng.o lib/mprintf.o dev/ep_pfilter.o dev/dna.o dev/i2c.o monitor/monitor.o #dev/onewire.o dev/i2c.o #dev/eeprom.o
D = ptp-noposix
PTPD_CFLAGS = -ffreestanding -DPTPD_FREESTANDING -DWRPC_EXTRA_SLIM -DPTPD_MSBF -DPTPD_DBG
......@@ -75,7 +75,7 @@ clean:
%.o: %.c
${CC} $(CFLAGS) $(PTPD_CFLAGS) $(INCLUDE_DIR) $(LIB_DIR) -c $^ -o $@
load: all
load: #all
./tools/lm32-loader $(OUTPUT).bin
tools:
......
dev/endpoint.c
View file @ 3f3a2b00
......@@ -101,6 +101,8 @@ int ep_enable(int enabled, int autoneg)
/* Disable the endpoint */
EP->ECR = 0;
mprintf("ID: %x", EP->IDCODE);
/* Load default packet classifier rules - see ep_pfilter.c for details */
pfilter_init_default();
......
dev/pps_gen.c
View file @ 3f3a2b00
......@@ -6,63 +6,46 @@
#define PPS_PULSE_WIDTH 100000
static inline void ppsg_writel(uint32_t reg,uint32_t data)
{
*(volatile uint32_t *) (BASE_PPSGEN + reg) = data;
}
static inline uint32_t ppsg_readl(uint32_t reg)
{
return *(volatile uint32_t *)(BASE_PPSGEN + reg);
}
static volatile struct PPSG_WB *PPSG = (volatile struct PPS_GEN_WB *) BASE_PPS_GEN;
void pps_gen_init()
{
uint32_t cr;
cr = PPSG_CR_CNT_EN | PPSG_CR_PWIDTH_W(PPS_PULSE_WIDTH);
ppsg_writel( PPSG_REG_CR, cr);
ppsg_writel( PPSG_REG_ESCR, 0);
PPSG->CR = cr;
PPSG->ESCR = 0;
ppsg_writel( PPSG_REG_ADJ_UTCLO, 100 );
ppsg_writel( PPSG_REG_ADJ_UTCHI, 0);
ppsg_writel( PPSG_REG_ADJ_NSEC, 0);
PPSG->ADJ_UTCLO = 100;
PPSG->ADJ_UTCHI = 0;
PPSG->ADJ_NSEC = 0;
ppsg_writel( PPSG_REG_CR, cr | PPSG_CR_CNT_SET);
ppsg_writel( PPSG_REG_CR, cr);
PPSG->CR = cr | PPSG_CR_CNT_SET;
PPSG->CR = cr;
}
void pps_gen_adjust_nsec(int32_t how_much)
{
TRACE_DEV("ADJ: nsec %d nanoseconds\n", how_much);
#if 1
ppsg_writel( PPSG_REG_ADJ_UTCLO, 0);
ppsg_writel( PPSG_REG_ADJ_UTCHI, 0);
ppsg_writel( PPSG_REG_ADJ_NSEC, ( how_much / 8 ));
ppsg_writel( PPSG_REG_CR, PPSG_CR_CNT_EN | PPSG_CR_PWIDTH_W(PPS_PULSE_WIDTH) | PPSG_CR_CNT_ADJ);
#endif
PPSG->ADJ_UTCLO = 0;
PPSG->ADJ_UTCHI = 0;
PPSG->ADJ_NSEC = ( how_much / 8 );
PPSG->CR = PPSG_CR_CNT_EN | PPSG_CR_PWIDTH_W(PPS_PULSE_WIDTH) | PPSG_CR_CNT_ADJ;
}
void pps_gen_adjust_utc(int32_t how_much)
{
#if 1
TRACE_DEV("ADJ: utc %d seconds\n", how_much);
ppsg_writel( PPSG_REG_ADJ_UTCLO, how_much);
ppsg_writel( PPSG_REG_ADJ_UTCHI, 0);
ppsg_writel( PPSG_REG_ADJ_NSEC, 0);
ppsg_writel( PPSG_REG_CR, PPSG_CR_CNT_EN | PPSG_CR_PWIDTH_W(PPS_PULSE_WIDTH) | PPSG_CR_CNT_ADJ);
#endif
TRACE_DEV("ADJ: utc %d seconds\n", how_much);
PPSG->ADJ_UTCLO = how_much;
PPSG->ADJ_UTCHI = 0;
PPSG->ADJ_NSEC = 0;
PPSG->CR = PPSG_CR_CNT_EN | PPSG_CR_PWIDTH_W(PPS_PULSE_WIDTH) | PPSG_CR_CNT_ADJ;
}
int pps_gen_busy()
{
return ppsg_readl(PPSG_REG_CR) & PPSG_CR_CNT_ADJ ? 0 : 1;
return PPSG->CR & PPSG_CR_CNT_ADJ ? 0 : 1;
}
void pps_gen_get_time(uint32_t *utc, uint32_t *cntr_nsec)
......@@ -71,12 +54,12 @@ void pps_gen_get_time(uint32_t *utc, uint32_t *cntr_nsec)
uint32_t utc_lo;
do {
cyc_before =ppsg_readl(PPSG_REG_CNTR_NSEC) & 0xfffffff;
utc_lo = ppsg_readl(PPSG_REG_CNTR_UTCLO) ;
cyc_after = ppsg_readl(PPSG_REG_CNTR_NSEC) & 0xfffffff;
cyc_before = PPSG->CNTR_NSEC & 0xfffffff;
utc_lo = PPSG->CNTR_UTCLO ;
cyc_after = PPSG->CNTR_NSEC & 0xfffffff;
} while (cyc_after < cyc_before);
delay(100000);
// delay(100000);
if(utc) *utc = utc_lo;
if(cntr_nsec) *cntr_nsec = cyc_after;
......@@ -86,8 +69,8 @@ void pps_gen_get_time(uint32_t *utc, uint32_t *cntr_nsec)
void pps_gen_enable_output(int enable)
{
if(enable)
ppsg_writel(PPSG_REG_ESCR, PPSG_ESCR_PPS_VALID | PPSG_ESCR_TM_VALID);
PPSG->ESCR = PPSG_ESCR_PPS_VALID | PPSG_ESCR_TM_VALID;
else
ppsg_writel(PPSG_REG_ESCR, 0);
PPSG->ESCR = 0;
}
dev/softpll_ng.c
View file @ 3f3a2b00
......@@ -14,7 +14,9 @@
volatile int irq_count = 0;
static volatile struct SPLL_WB *SPLL = (volatile struct SPLL_WB *) BASE_SOFTPLL;
static volatile struct PPSG_WB *PPSG = (volatile struct PPSG_WB *) BASE_PPSGEN;
static volatile struct PPSG_WB *PPSG = (volatile struct PPSG_WB *) BASE_PPS_GEN;
#define TRACE TRACE_DEV
/* The includes below contain code (not only declarations) to enable the compiler
to inline functions where necessary and save some CPU cycles */
......@@ -53,6 +55,7 @@ struct softpll_state {
static volatile struct softpll_state softpll;
static volatile int ptracker_mask = 0; /* fixme: should be done by spll_init() but spll_init is called to switch modes (and we won't like messing around with ptrackers there) */
void _irq_entry()
{
......@@ -61,7 +64,10 @@ void _irq_entry()
struct softpll_state *s = (struct softpll_state *) &softpll;
/* check if there are more tags in the FIFO */
if(! (SPLL->CSR & SPLL_TRR_CSR_EMPTY))
// softpll.seq_state = SEQ_WAIT_CLEAR_DACS;
if(! (SPLL->TRR_CSR & SPLL_TRR_CSR_EMPTY))
{
trr = SPLL->TRR_R0;
src = SPLL_TRR_R0_CHAN_ID_R(trr);
......@@ -73,13 +79,13 @@ void _irq_entry()
case SEQ_CLEAR_DACS:
SPLL->DAC_HPLL = 65535;
SPLL->DAC_MAIN = softpll.default_dac_main;
SPLL->OCER |= 1;
// SPLL->OCER |= 1;
softpll.seq_state = SEQ_WAIT_CLEAR_DACS;
softpll.dac_timeout = timer_get_tics();
break;
case SEQ_WAIT_CLEAR_DACS:
if(timer_get_tics() - softpll.dac_timeout > 10000)
if(timer_get_tics() - softpll.dac_timeout > TICS_PER_SECOND/20)
softpll.seq_state = (softpll.mode == SPLL_MODE_GRAND_MASTER ? SEQ_START_EXT : SEQ_START_HELPER);
break;
......@@ -112,7 +118,8 @@ void _irq_entry()
softpll.seq_state = SEQ_START_MAIN;
else {
for(i=0;i<n_chan_ref; i++)
ptracker_start((struct spll_ptracker_state *) &s->ptrackers[i]);
if(ptracker_mask & (1<<i))
ptracker_start((struct spll_ptracker_state *) &s->ptrackers[i]);
softpll.seq_state = SEQ_READY;
}
}
......@@ -129,7 +136,8 @@ void _irq_entry()
softpll.seq_state = SEQ_READY;
for(i=0;i<n_chan_ref; i++)
ptracker_start((struct spll_ptracker_state *) &s->ptrackers[i]);
if(ptracker_mask & (1<<i))
ptracker_start((struct spll_ptracker_state *) &s->ptrackers[i]);
}
break;
......@@ -175,7 +183,8 @@ void _irq_entry()
mpll_update((struct spll_main_state *) &s->mpll, tag, src);
for(i=0;i<n_chan_ref; i++)
ptracker_update((struct spll_ptracker_state *) &s->ptrackers[i], tag, src);
if(ptracker_mask & (1<<i))
ptracker_update((struct spll_ptracker_state *) &s->ptrackers[i], tag, src);
break;
......@@ -238,7 +247,7 @@ void spll_init(int mode, int slave_ref_channel, int align_pps)
strcpy(mode_str, "Grand Master");
softpll.seq_state = SEQ_CLEAR_DACS;
external_init(&softpll.ext, n_chan_ref + n_chan_out, align_pps);
helper_init(&softpll.helper, n_chan_ref);
......@@ -261,7 +270,6 @@ void spll_init(int mode, int slave_ref_channel, int align_pps)
mpll_init(&softpll.aux[i], slave_ref_channel, n_chan_ref + i + 1);
PPSG->ESCR = PPSG_ESCR_PPS_VALID | PPSG_ESCR_TM_VALID;
break;
case SPLL_MODE_SLAVE:
......@@ -273,6 +281,9 @@ void spll_init(int mode, int slave_ref_channel, int align_pps)
for(i=0;i<n_chan_out-1;i++)
mpll_init(&softpll.aux[i], slave_ref_channel, n_chan_ref + i + 1);
// PPSG->ESCR = PPSG_ESCR_PPS_VALID | PPSG_ESCR_TM_VALID;
break;
}
......@@ -280,7 +291,7 @@ void spll_init(int mode, int slave_ref_channel, int align_pps)
ptracker_init(&softpll.ptrackers[i], n_chan_ref, i, PTRACKER_AVERAGE_SAMPLES);
TRACE_DEV("SPLL_Init: running as %s, %d ref channels, %d out channels\n", mode_str, n_chan_ref, n_chan_out);
TRACE("SPLL_Init: running as %s, %d ref channels, %d out channels\n", mode_str, n_chan_ref, n_chan_out);
/* Purge tag buffer */
while(! (SPLL->TRR_CSR & SPLL_TRR_CSR_EMPTY)) dummy = SPLL->TRR_R0;
......@@ -288,7 +299,16 @@ void spll_init(int mode, int slave_ref_channel, int align_pps)
SPLL->EIC_IER = 1;
_irq_entry();
// _irq_entry();
SPLL->OCER |= 1;
// SPLL->RCER |= 1;
/* for(;;)
{
TRACE_DEV("OCER %x TRR_CSR %x %x\n", SPLL->OCER, SPLL->TRR_CSR, SPLL->TRR_R0);
}*/
enable_irq();
......@@ -362,7 +382,7 @@ void spll_get_phase_shift(int channel, int32_t *current, int32_t *target)
if(target) *target = to_picos(st->phase_shift_target);
}
int spll_read_ptracker(int channel, int32_t *phase_ps)
int spll_read_ptracker(int channel, int32_t *phase_ps, int *enabled)
{
volatile struct spll_ptracker_state *st = &softpll.ptrackers[channel];
int phase = st->phase_val;
......@@ -370,6 +390,8 @@ int spll_read_ptracker(int channel, int32_t *phase_ps)
else if (phase >= (1<<HPLL_N)) phase -= (1<<HPLL_N);
*phase_ps = to_picos(phase);
if(enabled)
*enabled = ptracker_mask & (1<<st->id_b) ? 1 : 0;
return st->ready;
}
......@@ -382,7 +404,7 @@ void spll_get_num_channels(int *n_ref, int *n_out)
void spll_show_stats()
{
if(softpll.mode > 0)
TRACE_DEV("Irq_count %d Sequencer_state %d mode %d Alignment_state %d HL%d EL%d ML%d HY=%d MY=%d\n",
TRACE("Irq_count %d Sequencer_state %d mode %d Alignment_state %d HL%d EL%d ML%d HY=%d MY=%d\n",
irq_count, softpll.seq_state, softpll.mode, softpll.ext.realign_state,
softpll.helper.ld.locked, softpll.ext.ld.locked, softpll.mpll.ld.locked,
softpll.helper.pi.y, softpll.mpll.pi.y);
......@@ -396,3 +418,20 @@ int spll_shifter_busy(int channel)
else
return mpll_shifter_busy(&softpll.aux[channel-1]);
}
void spll_enable_ptracker(int ref_channel, int enable)
{
if(enable) {
spll_enable_tagger(ref_channel, 1);
ptracker_start((struct spll_ptracker_state *) &softpll.ptrackers[ref_channel]);
ptracker_mask |= (1<<ref_channel);
TRACE("Enabling ptracker channel: %d\n", ref_channel);
} else {
ptracker_mask &= ~(1<<ref_channel);
if(ref_channel != softpll.mpll.id_ref)
spll_enable_tagger(ref_channel, 0);
TRACE("Disabling ptracker tagger: %d\n", ref_channel);
}
}
include/board.h
View file @ 3f3a2b00
......@@ -4,7 +4,7 @@
#define BASE_MINIC 0x20000
#define BASE_EP 0x20100
#define BASE_SOFTPLL 0x20200
#define BASE_PPSGEN 0x20300
#define BASE_PPS_GEN 0x20300
#define BASE_SYSCON 0x20400
#define BASE_UART 0x20500
#define BASE_ONEWIRE 0x20600
......
include/hw/pps_gen_regs.h
View file @ 3f3a2b00
......@@ -2,19 +2,17 @@
Register definitions for slave core: WR Switch PPS generator and RTC
* File : pps_gen_regs.h
* Author : auto-generated by wbgen2 from pps_gen_wb.wb
* Created : Sun Oct 30 01:54:53 2011
* Author : auto-generated by wbgen2 from wrsw_pps_gen.wb
* Created : Thu Oct 27 21:29:19 2011
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE pps_gen_wb.wb
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrsw_pps_gen.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_PPS_GEN_WB_WB
#define __WBGEN2_REGDEFS_PPS_GEN_WB_WB
#include <inttypes.h>
#ifndef __WBGEN2_REGDEFS_WRSW_PPS_GEN_WB
#define __WBGEN2_REGDEFS_WRSW_PPS_GEN_WB
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
......@@ -73,20 +71,24 @@
/* definitions for field: Timecode output(UTC+cycles) valid in reg: External sync control register */
#define PPSG_ESCR_TM_VALID WBGEN2_GEN_MASK(2, 1)
/* [0x0]: REG Control Register */
#define PPSG_REG_CR 0x00000000
/* [0x4]: REG Nanosecond counter register */
#define PPSG_REG_CNTR_NSEC 0x00000004
/* [0x8]: REG UTC Counter register (least-significant part) */
#define PPSG_REG_CNTR_UTCLO 0x00000008
/* [0xc]: REG UTC Counter register (most-significant part) */
#define PPSG_REG_CNTR_UTCHI 0x0000000c
/* [0x10]: REG Nanosecond adjustment register */
#define PPSG_REG_ADJ_NSEC 0x00000010
/* [0x14]: REG UTC Adjustment register (least-significant part) */
#define PPSG_REG_ADJ_UTCLO 0x00000014
/* [0x18]: REG UTC Adjustment register (most-significant part) */
#define PPSG_REG_ADJ_UTCHI 0x00000018
/* [0x1c]: REG External sync control register */
#define PPSG_REG_ESCR 0x0000001c
PACKED struct PPSG_WB {
/* [0x0]: REG Control Register */
uint32_t CR;
/* [0x4]: REG Nanosecond counter register */
uint32_t CNTR_NSEC;
/* [0x8]: REG UTC Counter register (least-significant part) */
uint32_t CNTR_UTCLO;
/* [0xc]: REG UTC Counter register (most-significant part) */
uint32_t CNTR_UTCHI;
/* [0x10]: REG Nanosecond adjustment register */
uint32_t ADJ_NSEC;
/* [0x14]: REG UTC Adjustment register (least-significant part) */
uint32_t ADJ_UTCLO;
/* [0x18]: REG UTC Adjustment register (most-significant part) */
uint32_t ADJ_UTCHI;
/* [0x1c]: REG External sync control register */
uint32_t ESCR;
};
#endif
include/hw/softpll_regs.h
View file @ 3f3a2b00
......@@ -3,7 +3,7 @@
* File : softpll_regs.h
* Author : auto-generated by wbgen2 from spll_wb_slave.wb
* Created : Tue Apr 17 14:39:36 2012
* Created : Mon Apr 16 16:49:35 2012
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE spll_wb_slave.wb
......@@ -14,8 +14,6 @@
#ifndef __WBGEN2_REGDEFS_SPLL_WB_SLAVE_WB
#define __WBGEN2_REGDEFS_SPLL_WB_SLAVE_WB
#include <inttypes.h>
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
......
include/softpll_ng.h
View file @ 3f3a2b00
......@@ -18,7 +18,7 @@ void spll_stop_channel(int channel);
int spll_check_lock(int channel);
void spll_set_phase_shift(int channel, int32_t value_picoseconds);
void spll_get_phase_shift(int channel, int32_t *current, int32_t *target);
int spll_read_ptracker(int channel, int32_t *phase_ps);
int spll_read_ptracker(int channel, int32_t *phase_ps, int *enabled);
void spll_get_num_channels(int *n_ref, int *n_out);
int spll_shifter_busy(int channel);
......
include/spll_defs.h
View file @ 3f3a2b00
......@@ -34,7 +34,7 @@ WARNING: These parameters must be in sync with the generics of the HDL instantia
#define MAX_CHAN_AUX 1
/* Max. allowed number of phase trackers */
#define MAX_PTRACKERS 6
#define MAX_PTRACKERS 1
/* Number of bits of the DAC(s) driving the oscillator(s). Must be the same for
all the outputs. */
......
include/spll_external.h
View file @ 3f3a2b00
#include <timer.h>
#include <hw/pps_gen_regs.h>
/* Number of bits of the BB phase detector error counter. Bit [BB_ERROR_BITS] is the wrap-around bit */
#define BB_ERROR_BITS 16
......@@ -44,21 +43,6 @@ Internal PPS __________________________________|^^^^^^^^^|________
#define REALIGN_DONE 7
//GGDD
PACKED struct PPSG_WB
{
uint32_t CR;
uint32_t CNTR_NSEC;
uint32_t CNTR_UTCLO;
uint32_t CNTR_UTCHI;
uint32_t ADJ_NSEC;
uint32_t ADJ_UTCLO;
uint32_t ADJ_UTCHI;
uint32_t ESCR;
};
//volatile struct temp_ppsg_regs *PPSG = BASE_PPSGEN;
//
struct spll_external_state {
int ref_src;
int sample_n;
......
wrc_main.c
View file @ 3f3a2b00
......@@ -153,7 +153,7 @@ int32_t sfp_deltaRx = 0;
// }
//}
#if 0
#if 1
int get_sfp_id(char *sfp_pn)
{
uint8_t data, sum=0;
......@@ -207,16 +207,17 @@ void wrc_initialize()
uart_init();
uart_write_string(__FILE__ " is up (compiled on "
__DATE__ " " __TIME__ ")\n");
// uart_write_string(__FILE__ " is up (compiled on "
// __DATE__ " " __TIME__ ")\n");
mprintf("wr_core: starting up (press G to launch the GUI and D for extra debug messages)....\n");
//SFP
#if 0
#if 1
// mprintf("Detecting transceiver...");
if( get_sfp_id(sfp_pn) >= 0)
{
mprintf("Found SFP transceiver ID: ");
// mprintf("Found SFP transceiver ID: ");
for(i=0;i<16;i++)
mprintf("%c", sfp_pn[i]);
mprintf("\n");
......@@ -245,10 +246,12 @@ void wrc_initialize()
mac_addr[4] = ds18_id[2]; // APPLICATION NOTE 186
mac_addr[5] = ds18_id[1]; // Creating Global Identifiers Using 1-Wire® Devices
TRACE_DEV("wr_core: local MAC address: %x:%x:%x:%x:%x:%x\n", mac_addr[0],mac_addr[1],mac_addr[2],mac_addr[3],mac_addr[4],mac_addr[5]);
// TRACE_DEV("wr_core: local MAC address: %x:%x:%x:%x:%x:%x\n", mac_addr[0],mac_addr[1],mac_addr[2],mac_addr[3],mac_addr[4],mac_addr[5]);
ep_init(mac_addr);
ep_enable(1, 1);
// for(;;);
minic_init();
pps_gen_init();
// for(;;);
......@@ -337,7 +340,7 @@ void wrc_handle_input()
case 'd':
wrc_extra_debug = 1 - wrc_extra_debug;
wrc_debug_printf(0,"Verbose debug %s.\n", wrc_extra_debug ? "enabled" : "disabled");
// wrc_debug_printf(0,"Verbose debug %s.\n", wrc_extra_debug ? "enabled" : "disabled");
break;
......@@ -345,13 +348,13 @@ void wrc_handle_input()
wrc_enable_tracking = 1 - wrc_enable_tracking;
wr_servo_enable_tracking(wrc_enable_tracking);
wrc_debug_printf(0,"Phase tracking %s.\n", wrc_enable_tracking ? "enabled" : "disabled");
// wrc_debug_printf(0,"Phase tracking %s.\n", wrc_enable_tracking ? "enabled" : "disabled");
break;
case '+':
case '-':
wrc_man_phase += (x=='+' ? 100 : -100);
wrc_debug_printf(0,"Manual phase adjust: %d\n", wrc_man_phase);
// wrc_debug_printf(0,"Manual phase adjust: %d\n", wrc_man_phase);
wr_servo_man_adjust_phase(wrc_man_phase);
break;
......@@ -369,8 +372,7 @@ int main(void)
wrc_initialize();
//spll_init(SPLL_MODE_GRAND_MASTER, 0, 1);
//spll_init(SPLL_MODE_FREE_RUNNING_MASTER, 0, 1);
spll_init(SPLL_MODE_SLAVE, 0, 1);
spll_init(SPLL_MODE_FREE_RUNNING_MASTER, 0, 1);
//for(;;)
//{
......@@ -387,7 +389,8 @@ int main(void)
wrc_handle_input();
if(wrc_gui_mode)
wrc_mon_gui();
#if 1
int l_status = wrc_check_link();
switch (l_status)
{
......@@ -415,11 +418,18 @@ int main(void)
break;
case LINK_WENT_DOWN:
spll_init(SPLL_MODE_FREE_RUNNING_MASTER, 0, 1);
break;
}
protocol_nonblock(&rtOpts, ptpPortDS);
singlePortLoop(&rtOpts, ptpPortDS, 0);// RunTimeOpts *rtOpts, PtpPortDS *ptpPortDS, int portIndex)
sharedPortsLoop(ptpPortDS);
delay(100000);
// protocol_nonblock(&rtOpts, ptpPortDS);
#endif
}
}
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