Commit 245d3efb authored by Tomasz Wlostowski's avatar Tomasz Wlostowski

tools/trivial-init: a small footprint, delay-free WRPC firmware for VHDL/Verilog…

tools/trivial-init: a small footprint, delay-free WRPC firmware for VHDL/Verilog simulations (initial commit)
parent 9b6b9b98
# and don't touch the rest unless you know what you're doing.
CROSS_COMPILE ?= lm32-elf-
CC = $(CROSS_COMPILE)gcc
LD = $(CROSS_COMPILE)ld
OBJDUMP = $(CROSS_COMPILE)objdump
OBJCOPY = $(CROSS_COMPILE)objcopy
SIZE = $(CROSS_COMPILE)size
CFLAGS = -Os -I../../include -I../../softpll
OBJS = startup.o main.o
LDS = ram.ld
OUTPUT=wrc_simulation_sw
$(OUTPUT): $(LDS) $(OBJS)
${CC} -o $(OUTPUT).elf -nostartfiles $(OBJS) -T $(LDS)
${OBJCOPY} -O binary $(OUTPUT).elf $(OUTPUT).bin
# ${OBJDUMP} -D $(OUTPUT).elf
$(SIZE) $(OUTPUT).elf
../genramvhd -p wrc_simulation_firmware $(OUTPUT).bin > wrc_simulation_firmware_pkg.vhd
../genraminit $(OUTPUT).bin 1000 > wrc-simulation.ram
#include <stdint.h>
#include <stddef.h>
#include <hw/pps_gen_regs.h>
#include <hw/endpoint_regs.h>
#include <hw/softpll_regs.h>
#include <hw/endpoint_mdio.h>
#include <hw/wb_uart.h>
#define BASE_ENDPOINT 0x20100
#define BASE_PPS_GEN 0x20300
#define BASE_UART 0x20500
#define BASE_SOFTPLL 0x20200
#define ppsg_write(reg, val) \
*(volatile uint32_t *) (BASE_PPS_GEN + (offsetof(struct PPSG_WB, reg))) = (val)
#define ppsg_read(reg) \
*(volatile uint32_t *) (BASE_PPS_GEN + (offsetof(struct PPSG_WB, reg)))
#define CALC_BAUD(baudrate) \
( ((( (unsigned long long)baudrate * 8ULL) << (16 - 7)) + \
(CPU_CLOCK >> 8)) / (CPU_CLOCK >> 7) )
#define CPU_CLOCK 62500000
#define UART_BAUDRATE 6000000
void uart_init()
{
volatile struct UART_WB *uart;
uart = (volatile struct UART_WB *)BASE_UART;
uart->BCR = CALC_BAUD(UART_BAUDRATE);
}
void uart_write_byte(int b)
{
volatile struct UART_WB *uart;
uart = (volatile struct UART_WB *)BASE_UART;
while (uart->SR & UART_SR_TX_BUSY)
;
uart->TDR = b;
}
void uart_write_string(char *s)
{
char c;
while(c=*s++)
uart_write_byte(c);
}
volatile struct EP_WB *EP = (volatile struct EP_WB *)BASE_ENDPOINT;
volatile struct SPLL_WB *SPLL = (volatile struct EP_WB *)BASE_SOFTPLL;
static void pcs_write(int location, int value)
{
EP->MDIO_CR = EP_MDIO_CR_ADDR_W(location >> 2)
| EP_MDIO_CR_DATA_W(value)
| EP_MDIO_CR_RW;
while ((EP->MDIO_ASR & EP_MDIO_ASR_READY) == 0) ;
}
void endpoint_init()
{
EP->PFCR0 = 0; // disable pfilter
#include "pf-microcode.h"
EP->PFCR0 = EP_PFCR0_ENABLE;
EP->ECR = 0; /* disable Endpoint */
EP->VCR0 = EP_VCR0_QMODE_W(3); /* disable VLAN unit - not used by WRPC */
EP->RFCR = EP_RFCR_MRU_W(1518); /* Set the max RX packet size */
EP->TSCR = EP_TSCR_EN_TXTS | EP_TSCR_EN_RXTS; /* Enable timestamping */
EP->MACL = 0x33445566;
EP->MACH = 0x1122;
EP->ECR = EP_ECR_TX_EN | EP_ECR_RX_EN | EP_ECR_RST_CNT;
pcs_write(MDIO_REG_MCR, MDIO_MCR_PDOWN); /* reset the PHY */
pcs_write(MDIO_REG_MCR, 0); /* reset th */
}
main()
{
uint32_t cr;
cr = PPSG_CR_CNT_EN | PPSG_CR_PWIDTH_W(1);
ppsg_write(CR, cr);
ppsg_write(ADJ_UTCLO, 0);
ppsg_write(ADJ_UTCHI, 0);
ppsg_write(ADJ_NSEC, 0);
ppsg_write(CR, cr | PPSG_CR_CNT_SET);
ppsg_write(CR, cr);
ppsg_write(ESCR, PPSG_ESCR_TM_VALID);
endpoint_init();
uart_init();
int i=0;
for(i=0;i<50;i++)
uart_write_string("Hello!\n");
for(;;)
{
SPLL->DAC_MAIN = (1<<16) | (i++);
uart_write_string(" ");
}
for(;;);
}
\ No newline at end of file
EP->PFCR1 = 0x00000000;
EP->PFCR0 = 0x40000040;
EP->PFCR1 = 0x0000000b;
EP->PFCR0 = 0x1ffffe41;
EP->PFCR1 = 0x00000088;
EP->PFCR0 = 0x1ffffe42;
EP->PFCR1 = 0x00000108;
EP->PFCR0 = 0x1ffffe43;
EP->PFCR1 = 0x00000013;
EP->PFCR0 = 0x1e023644;
EP->PFCR1 = 0x00000090;
EP->PFCR0 = 0x1e320045;
EP->PFCR1 = 0x00000110;
EP->PFCR0 = 0x1e000046;
EP->PFCR1 = 0x0000001b;
EP->PFCR0 = 0x1e224447;
EP->PFCR1 = 0x00000098;
EP->PFCR0 = 0x1e668848;
EP->PFCR1 = 0x00000118;
EP->PFCR0 = 0x1eaacc49;
EP->PFCR1 = 0x00000323;
EP->PFCR0 = 0x1e10004a;
EP->PFCR1 = 0x0000032b;
EP->PFCR0 = 0x1f11ee4b;
EP->PFCR1 = 0x00000333;
EP->PFCR0 = 0x1e100c4c;
EP->PFCR1 = 0x0000034b;
EP->PFCR0 = 0x1fb7fe4d;
EP->PFCR1 = 0x000005bb;
EP->PFCR0 = 0x0600024e;
EP->PFCR1 = 0x000005c3;
EP->PFCR0 = 0x0600224f;
EP->PFCR1 = 0x00000351;
EP->PFCR0 = 0x40010050;
EP->PFCR1 = 0x00000159;
EP->PFCR0 = 0x40010651;
EP->PFCR1 = 0x00000170;
EP->PFCR0 = 0x40094c52;
EP->PFCR1 = 0x00000a78;
EP->PFCR0 = 0x400b8e53;
EP->PFCR1 = 0x00000973;
EP->PFCR0 = 0x1e008854;
EP->PFCR1 = 0x00000e70;
EP->PFCR0 = 0x4002d055;
EP->PFCR1 = 0x00000e79;
EP->PFCR0 = 0x40181e56;
EP->PFCR1 = 0x00000ba0;
EP->PFCR0 = 0x400bd057;
EP->PFCR1 = 0x000004b9;
EP->PFCR0 = 0x40381358;
EP->PFCR1 = 0x00000bf8;
EP->PFCR0 = 0x40181059;
EP->PFCR1 = 0x000001f0;
EP->PFCR0 = 0x4018125a;
EP->PFCR1 = 0x00000fc3;
EP->PFCR0 = 0x4018005b;
EP->PFCR1 = 0x00000000;
EP->PFCR0 = 0x8000005c;
/*
* Link script for Lattice Mico32. Very loosely based on
* code contributed by Jon Beniston <jon@beniston.com>
*
* Jon's license (BSD-style):
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
OUTPUT_FORMAT("elf32-lm32")
ENTRY(_start)
MEMORY
{
ram :
ORIGIN = 0x00000000,
LENGTH = 0x1000 - 0x100
stack :
ORIGIN = 0x1000 - 0x100
LENGTH = 0x100
}
SECTIONS
{
.boot : { *(.boot) } > ram
.text : { *(.text .text.*) } > ram =0
.rodata : { *(.rodata .rodata.*) } > ram
.data : {
*(.data .data.*)
_gp = ALIGN(16) + 0x7ff0; /* FIXME: what is this? */
} > ram
.bss : {
_fbss = .;
*(.bss .bss.*)
*(COMMON)
_ebss = .;
} > ram
/* End of RAM for checking stack overflows */
PROVIDE(_endram = ORIGIN(stack));
/* First location in stack is highest address in STACK */
PROVIDE(_fstack = ORIGIN(stack) + LENGTH(stack) - 4);
}
.section .boot, "ax", @progbits
.global _start
_start:
.global _reset_handler
.type _reset_handler, @function
_reset_handler:
xor r0, r0, r0
wcsr IE, r0
wcsr IM, r0
mvhi r1, hi(_reset_handler)
ori r1, r1, lo(_reset_handler)
wcsr EBA, r1
xor r0, r0, r0
mvhi sp, hi(_fstack)
ori sp, sp, lo(_fstack)
mvhi gp, hi(_gp)
ori gp, gp, lo(_gp)
calli main
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