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Software for White Rabbit PTP Core
Commit 1f9ac2c0 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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added reg layout headers

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include/hw/endpoint_mdio.h 0 → 100644
View file @ 1f9ac2c0
/*
Register definitions for slave core: WR Endpoint 1000base-X TBI PCS register block
* File : ../../../software/include/hw/endpoint_mdio.h
* Author : auto-generated by wbgen2 from pcs_regs.wb
* Created : Tue Dec 7 17:14:23 2010
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE pcs_regs.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_PCS_REGS_WB
#define __WBGEN2_REGDEFS_PCS_REGS_WB
#include <inttypes.h>
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: MDIO Control Register */
/* definitions for field: Reserved in reg: MDIO Control Register */
#define MDIO_MCR_RESV_MASK WBGEN2_GEN_MASK(0, 5)
#define MDIO_MCR_RESV_SHIFT 0
#define MDIO_MCR_RESV_W(value) WBGEN2_GEN_WRITE(value, 0, 5)
#define MDIO_MCR_RESV_R(reg) WBGEN2_GEN_READ(reg, 0, 5)
/* definitions for field: Unidirectional Enable in reg: MDIO Control Register */
#define MDIO_MCR_UNI_EN WBGEN2_GEN_MASK(5, 1)
/* definitions for field: Speed Selection (MSB) in reg: MDIO Control Register */
#define MDIO_MCR_SPEED1000_MASK WBGEN2_GEN_MASK(6, 1)
#define MDIO_MCR_SPEED1000_SHIFT 6
#define MDIO_MCR_SPEED1000_W(value) WBGEN2_GEN_WRITE(value, 6, 1)
#define MDIO_MCR_SPEED1000_R(reg) WBGEN2_GEN_READ(reg, 6, 1)
/* definitions for field: Collision Test in reg: MDIO Control Register */
#define MDIO_MCR_CTST_MASK WBGEN2_GEN_MASK(7, 1)
#define MDIO_MCR_CTST_SHIFT 7
#define MDIO_MCR_CTST_W(value) WBGEN2_GEN_WRITE(value, 7, 1)
#define MDIO_MCR_CTST_R(reg) WBGEN2_GEN_READ(reg, 7, 1)
/* definitions for field: Duplex Mode in reg: MDIO Control Register */
#define MDIO_MCR_FULLDPLX_MASK WBGEN2_GEN_MASK(8, 1)
#define MDIO_MCR_FULLDPLX_SHIFT 8
#define MDIO_MCR_FULLDPLX_W(value) WBGEN2_GEN_WRITE(value, 8, 1)
#define MDIO_MCR_FULLDPLX_R(reg) WBGEN2_GEN_READ(reg, 8, 1)
/* definitions for field: Restart Auto-Negotiation in reg: MDIO Control Register */
#define MDIO_MCR_ANRESTART WBGEN2_GEN_MASK(9, 1)
/* definitions for field: Isolate in reg: MDIO Control Register */
#define MDIO_MCR_ISOLATE_MASK WBGEN2_GEN_MASK(10, 1)
#define MDIO_MCR_ISOLATE_SHIFT 10
#define MDIO_MCR_ISOLATE_W(value) WBGEN2_GEN_WRITE(value, 10, 1)
#define MDIO_MCR_ISOLATE_R(reg) WBGEN2_GEN_READ(reg, 10, 1)
/* definitions for field: Power Down in reg: MDIO Control Register */
#define MDIO_MCR_PDOWN WBGEN2_GEN_MASK(11, 1)
/* definitions for field: Auto-Negotiation Enable in reg: MDIO Control Register */
#define MDIO_MCR_ANENABLE WBGEN2_GEN_MASK(12, 1)
/* definitions for field: Speed Selection (LSB) in reg: MDIO Control Register */
#define MDIO_MCR_SPEED100_MASK WBGEN2_GEN_MASK(13, 1)
#define MDIO_MCR_SPEED100_SHIFT 13
#define MDIO_MCR_SPEED100_W(value) WBGEN2_GEN_WRITE(value, 13, 1)
#define MDIO_MCR_SPEED100_R(reg) WBGEN2_GEN_READ(reg, 13, 1)
/* definitions for field: Loopback in reg: MDIO Control Register */
#define MDIO_MCR_LOOPBACK WBGEN2_GEN_MASK(14, 1)
/* definitions for field: Reset in reg: MDIO Control Register */
#define MDIO_MCR_RESET WBGEN2_GEN_MASK(15, 1)
/* definitions for register: MDIO Status Register */
/* definitions for field: Extended Capability in reg: MDIO Status Register */
#define MDIO_MSR_ERCAP_MASK WBGEN2_GEN_MASK(0, 1)
#define MDIO_MSR_ERCAP_SHIFT 0
#define MDIO_MSR_ERCAP_W(value) WBGEN2_GEN_WRITE(value, 0, 1)
#define MDIO_MSR_ERCAP_R(reg) WBGEN2_GEN_READ(reg, 0, 1)
/* definitions for field: Jabber Detect in reg: MDIO Status Register */
#define MDIO_MSR_JCD_MASK WBGEN2_GEN_MASK(1, 1)
#define MDIO_MSR_JCD_SHIFT 1
#define MDIO_MSR_JCD_W(value) WBGEN2_GEN_WRITE(value, 1, 1)
#define MDIO_MSR_JCD_R(reg) WBGEN2_GEN_READ(reg, 1, 1)
/* definitions for field: Link Status in reg: MDIO Status Register */
#define MDIO_MSR_LSTATUS WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Auto-Negotiation Ability in reg: MDIO Status Register */
#define MDIO_MSR_ANEGCAPABLE_MASK WBGEN2_GEN_MASK(3, 1)
#define MDIO_MSR_ANEGCAPABLE_SHIFT 3
#define MDIO_MSR_ANEGCAPABLE_W(value) WBGEN2_GEN_WRITE(value, 3, 1)
#define MDIO_MSR_ANEGCAPABLE_R(reg) WBGEN2_GEN_READ(reg, 3, 1)
/* definitions for field: Remote Fault in reg: MDIO Status Register */
#define MDIO_MSR_RFAULT WBGEN2_GEN_MASK(4, 1)
/* definitions for field: Auto-Negotiation Complete in reg: MDIO Status Register */
#define MDIO_MSR_ANEGCOMPLETE WBGEN2_GEN_MASK(5, 1)
/* definitions for field: MF Preamble Suppression in reg: MDIO Status Register */
#define MDIO_MSR_MFSUPPRESS_MASK WBGEN2_GEN_MASK(6, 1)
#define MDIO_MSR_MFSUPPRESS_SHIFT 6
#define MDIO_MSR_MFSUPPRESS_W(value) WBGEN2_GEN_WRITE(value, 6, 1)
#define MDIO_MSR_MFSUPPRESS_R(reg) WBGEN2_GEN_READ(reg, 6, 1)
/* definitions for field: Unidirectional Ability in reg: MDIO Status Register */
#define MDIO_MSR_UNIDIRABLE_MASK WBGEN2_GEN_MASK(7, 1)
#define MDIO_MSR_UNIDIRABLE_SHIFT 7
#define MDIO_MSR_UNIDIRABLE_W(value) WBGEN2_GEN_WRITE(value, 7, 1)
#define MDIO_MSR_UNIDIRABLE_R(reg) WBGEN2_GEN_READ(reg, 7, 1)
/* definitions for field: Extended Status Capable in reg: MDIO Status Register */
#define MDIO_MSR_ESTATEN_MASK WBGEN2_GEN_MASK(8, 1)
#define MDIO_MSR_ESTATEN_SHIFT 8
#define MDIO_MSR_ESTATEN_W(value) WBGEN2_GEN_WRITE(value, 8, 1)
#define MDIO_MSR_ESTATEN_R(reg) WBGEN2_GEN_READ(reg, 8, 1)
/* definitions for field: 100BASE-T2 Half Duplex in reg: MDIO Status Register */
#define MDIO_MSR_100HALF2_MASK WBGEN2_GEN_MASK(9, 1)
#define MDIO_MSR_100HALF2_SHIFT 9
#define MDIO_MSR_100HALF2_W(value) WBGEN2_GEN_WRITE(value, 9, 1)
#define MDIO_MSR_100HALF2_R(reg) WBGEN2_GEN_READ(reg, 9, 1)
/* definitions for field: 100BASE-T2 Full Duplex in reg: MDIO Status Register */
#define MDIO_MSR_100FULL2_MASK WBGEN2_GEN_MASK(10, 1)
#define MDIO_MSR_100FULL2_SHIFT 10
#define MDIO_MSR_100FULL2_W(value) WBGEN2_GEN_WRITE(value, 10, 1)
#define MDIO_MSR_100FULL2_R(reg) WBGEN2_GEN_READ(reg, 10, 1)
/* definitions for field: 10 Mbps Half Duplex in reg: MDIO Status Register */
#define MDIO_MSR_10HALF_MASK WBGEN2_GEN_MASK(11, 1)
#define MDIO_MSR_10HALF_SHIFT 11
#define MDIO_MSR_10HALF_W(value) WBGEN2_GEN_WRITE(value, 11, 1)
#define MDIO_MSR_10HALF_R(reg) WBGEN2_GEN_READ(reg, 11, 1)
/* definitions for field: 10 Mbps Full Duplex in reg: MDIO Status Register */
#define MDIO_MSR_10FULL_MASK WBGEN2_GEN_MASK(12, 1)
#define MDIO_MSR_10FULL_SHIFT 12
#define MDIO_MSR_10FULL_W(value) WBGEN2_GEN_WRITE(value, 12, 1)
#define MDIO_MSR_10FULL_R(reg) WBGEN2_GEN_READ(reg, 12, 1)
/* definitions for field: 100BASE-X Half Duplex in reg: MDIO Status Register */
#define MDIO_MSR_100HALF_MASK WBGEN2_GEN_MASK(13, 1)
#define MDIO_MSR_100HALF_SHIFT 13
#define MDIO_MSR_100HALF_W(value) WBGEN2_GEN_WRITE(value, 13, 1)
#define MDIO_MSR_100HALF_R(reg) WBGEN2_GEN_READ(reg, 13, 1)
/* definitions for field: 100BASE-X Full Duplex in reg: MDIO Status Register */
#define MDIO_MSR_100FULL_MASK WBGEN2_GEN_MASK(14, 1)
#define MDIO_MSR_100FULL_SHIFT 14
#define MDIO_MSR_100FULL_W(value) WBGEN2_GEN_WRITE(value, 14, 1)
#define MDIO_MSR_100FULL_R(reg) WBGEN2_GEN_READ(reg, 14, 1)
/* definitions for field: 100BASE-T4 in reg: MDIO Status Register */
#define MDIO_MSR_100BASE4_MASK WBGEN2_GEN_MASK(15, 1)
#define MDIO_MSR_100BASE4_SHIFT 15
#define MDIO_MSR_100BASE4_W(value) WBGEN2_GEN_WRITE(value, 15, 1)
#define MDIO_MSR_100BASE4_R(reg) WBGEN2_GEN_READ(reg, 15, 1)
/* definitions for register: MDIO PHY Identification Register 1 */
/* definitions for field: Organizationally Unique Identifier (bits 7-21) in reg: MDIO PHY Identification Register 1 */
#define MDIO_PHYSID1_OUI_MASK WBGEN2_GEN_MASK(0, 16)
#define MDIO_PHYSID1_OUI_SHIFT 0
#define MDIO_PHYSID1_OUI_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define MDIO_PHYSID1_OUI_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for register: MDIO PHY Identification Register 2 */
/* definitions for field: Revision Number in reg: MDIO PHY Identification Register 2 */
#define MDIO_PHYSID2_REV_NUM_MASK WBGEN2_GEN_MASK(0, 4)
#define MDIO_PHYSID2_REV_NUM_SHIFT 0
#define MDIO_PHYSID2_REV_NUM_W(value) WBGEN2_GEN_WRITE(value, 0, 4)
#define MDIO_PHYSID2_REV_NUM_R(reg) WBGEN2_GEN_READ(reg, 0, 4)
/* definitions for field: Manufacturer Model Number in reg: MDIO PHY Identification Register 2 */
#define MDIO_PHYSID2_MMNUM_MASK WBGEN2_GEN_MASK(4, 6)
#define MDIO_PHYSID2_MMNUM_SHIFT 4
#define MDIO_PHYSID2_MMNUM_W(value) WBGEN2_GEN_WRITE(value, 4, 6)
#define MDIO_PHYSID2_MMNUM_R(reg) WBGEN2_GEN_READ(reg, 4, 6)
/* definitions for field: Organizationally Unique Identifier (bits 0-5) in reg: MDIO PHY Identification Register 2 */
#define MDIO_PHYSID2_OUI_MASK WBGEN2_GEN_MASK(10, 6)
#define MDIO_PHYSID2_OUI_SHIFT 10
#define MDIO_PHYSID2_OUI_W(value) WBGEN2_GEN_WRITE(value, 10, 6)
#define MDIO_PHYSID2_OUI_R(reg) WBGEN2_GEN_READ(reg, 10, 6)
/* definitions for register: MDIO Auto-Negotiation Advertisement Register */
/* definitions for field: Reserved in reg: MDIO Auto-Negotiation Advertisement Register */
#define MDIO_ADVERTISE_RSVD3_MASK WBGEN2_GEN_MASK(0, 5)
#define MDIO_ADVERTISE_RSVD3_SHIFT 0
#define MDIO_ADVERTISE_RSVD3_W(value) WBGEN2_GEN_WRITE(value, 0, 5)
#define MDIO_ADVERTISE_RSVD3_R(reg) WBGEN2_GEN_READ(reg, 0, 5)
/* definitions for field: Full Duplex in reg: MDIO Auto-Negotiation Advertisement Register */
#define MDIO_ADVERTISE_FULL_MASK WBGEN2_GEN_MASK(5, 1)
#define MDIO_ADVERTISE_FULL_SHIFT 5
#define MDIO_ADVERTISE_FULL_W(value) WBGEN2_GEN_WRITE(value, 5, 1)
#define MDIO_ADVERTISE_FULL_R(reg) WBGEN2_GEN_READ(reg, 5, 1)
/* definitions for field: Half Duplex in reg: MDIO Auto-Negotiation Advertisement Register */
#define MDIO_ADVERTISE_HALF_MASK WBGEN2_GEN_MASK(6, 1)
#define MDIO_ADVERTISE_HALF_SHIFT 6
#define MDIO_ADVERTISE_HALF_W(value) WBGEN2_GEN_WRITE(value, 6, 1)
#define MDIO_ADVERTISE_HALF_R(reg) WBGEN2_GEN_READ(reg, 6, 1)
/* definitions for field: Pause in reg: MDIO Auto-Negotiation Advertisement Register */
#define MDIO_ADVERTISE_PAUSE_MASK WBGEN2_GEN_MASK(7, 2)
#define MDIO_ADVERTISE_PAUSE_SHIFT 7
#define MDIO_ADVERTISE_PAUSE_W(value) WBGEN2_GEN_WRITE(value, 7, 2)
#define MDIO_ADVERTISE_PAUSE_R(reg) WBGEN2_GEN_READ(reg, 7, 2)
/* definitions for field: Reserved in reg: MDIO Auto-Negotiation Advertisement Register */
#define MDIO_ADVERTISE_RSVD2_MASK WBGEN2_GEN_MASK(9, 3)
#define MDIO_ADVERTISE_RSVD2_SHIFT 9
#define MDIO_ADVERTISE_RSVD2_W(value) WBGEN2_GEN_WRITE(value, 9, 3)
#define MDIO_ADVERTISE_RSVD2_R(reg) WBGEN2_GEN_READ(reg, 9, 3)
/* definitions for field: Remote Fault in reg: MDIO Auto-Negotiation Advertisement Register */
#define MDIO_ADVERTISE_RFAULT_MASK WBGEN2_GEN_MASK(12, 2)
#define MDIO_ADVERTISE_RFAULT_SHIFT 12
#define MDIO_ADVERTISE_RFAULT_W(value) WBGEN2_GEN_WRITE(value, 12, 2)
#define MDIO_ADVERTISE_RFAULT_R(reg) WBGEN2_GEN_READ(reg, 12, 2)
/* definitions for field: Reserved in reg: MDIO Auto-Negotiation Advertisement Register */
#define MDIO_ADVERTISE_RSVD1_MASK WBGEN2_GEN_MASK(14, 1)
#define MDIO_ADVERTISE_RSVD1_SHIFT 14
#define MDIO_ADVERTISE_RSVD1_W(value) WBGEN2_GEN_WRITE(value, 14, 1)
#define MDIO_ADVERTISE_RSVD1_R(reg) WBGEN2_GEN_READ(reg, 14, 1)
/* definitions for field: Next Page in reg: MDIO Auto-Negotiation Advertisement Register */
#define MDIO_ADVERTISE_NPAGE_MASK WBGEN2_GEN_MASK(15, 1)
#define MDIO_ADVERTISE_NPAGE_SHIFT 15
#define MDIO_ADVERTISE_NPAGE_W(value) WBGEN2_GEN_WRITE(value, 15, 1)
#define MDIO_ADVERTISE_NPAGE_R(reg) WBGEN2_GEN_READ(reg, 15, 1)
/* definitions for register: MDIO Auto-Negotiation Link Partner Ability Register */
/* definitions for field: Reserved in reg: MDIO Auto-Negotiation Link Partner Ability Register */
#define MDIO_LPA_RSVD3_MASK WBGEN2_GEN_MASK(0, 5)
#define MDIO_LPA_RSVD3_SHIFT 0
#define MDIO_LPA_RSVD3_W(value) WBGEN2_GEN_WRITE(value, 0, 5)
#define MDIO_LPA_RSVD3_R(reg) WBGEN2_GEN_READ(reg, 0, 5)
/* definitions for field: Full Duplex in reg: MDIO Auto-Negotiation Link Partner Ability Register */
#define MDIO_LPA_FULL WBGEN2_GEN_MASK(5, 1)
/* definitions for field: Half Duplex in reg: MDIO Auto-Negotiation Link Partner Ability Register */
#define MDIO_LPA_HALF WBGEN2_GEN_MASK(6, 1)
/* definitions for field: Pause in reg: MDIO Auto-Negotiation Link Partner Ability Register */
#define MDIO_LPA_PAUSE_MASK WBGEN2_GEN_MASK(7, 2)
#define MDIO_LPA_PAUSE_SHIFT 7
#define MDIO_LPA_PAUSE_W(value) WBGEN2_GEN_WRITE(value, 7, 2)
#define MDIO_LPA_PAUSE_R(reg) WBGEN2_GEN_READ(reg, 7, 2)
/* definitions for field: Reserved in reg: MDIO Auto-Negotiation Link Partner Ability Register */
#define MDIO_LPA_RSVD2_MASK WBGEN2_GEN_MASK(9, 3)
#define MDIO_LPA_RSVD2_SHIFT 9
#define MDIO_LPA_RSVD2_W(value) WBGEN2_GEN_WRITE(value, 9, 3)
#define MDIO_LPA_RSVD2_R(reg) WBGEN2_GEN_READ(reg, 9, 3)
/* definitions for field: Remote Fault in reg: MDIO Auto-Negotiation Link Partner Ability Register */
#define MDIO_LPA_RFAULT_MASK WBGEN2_GEN_MASK(12, 2)
#define MDIO_LPA_RFAULT_SHIFT 12
#define MDIO_LPA_RFAULT_W(value) WBGEN2_GEN_WRITE(value, 12, 2)
#define MDIO_LPA_RFAULT_R(reg) WBGEN2_GEN_READ(reg, 12, 2)
/* definitions for field: Acknowledge in reg: MDIO Auto-Negotiation Link Partner Ability Register */
#define MDIO_LPA_LPACK WBGEN2_GEN_MASK(14, 1)
/* definitions for field: Next Page in reg: MDIO Auto-Negotiation Link Partner Ability Register */
#define MDIO_LPA_NPAGE WBGEN2_GEN_MASK(15, 1)
/* definitions for register: MDIO Auto-Negotiation Expansion Register */
/* definitions for field: Reserved in reg: MDIO Auto-Negotiation Expansion Register */
#define MDIO_EXPANSION_RSVD1_MASK WBGEN2_GEN_MASK(0, 1)
#define MDIO_EXPANSION_RSVD1_SHIFT 0
#define MDIO_EXPANSION_RSVD1_W(value) WBGEN2_GEN_WRITE(value, 0, 1)
#define MDIO_EXPANSION_RSVD1_R(reg) WBGEN2_GEN_READ(reg, 0, 1)
/* definitions for field: Page Received in reg: MDIO Auto-Negotiation Expansion Register */
#define MDIO_EXPANSION_LWCP_MASK WBGEN2_GEN_MASK(1, 1)
#define MDIO_EXPANSION_LWCP_SHIFT 1
#define MDIO_EXPANSION_LWCP_W(value) WBGEN2_GEN_WRITE(value, 1, 1)
#define MDIO_EXPANSION_LWCP_R(reg) WBGEN2_GEN_READ(reg, 1, 1)
/* definitions for field: Next Page Able in reg: MDIO Auto-Negotiation Expansion Register */
#define MDIO_EXPANSION_ENABLENPAGE_MASK WBGEN2_GEN_MASK(2, 1)
#define MDIO_EXPANSION_ENABLENPAGE_SHIFT 2
#define MDIO_EXPANSION_ENABLENPAGE_W(value) WBGEN2_GEN_WRITE(value, 2, 1)
#define MDIO_EXPANSION_ENABLENPAGE_R(reg) WBGEN2_GEN_READ(reg, 2, 1)
/* definitions for field: Reserved in reg: MDIO Auto-Negotiation Expansion Register */
#define MDIO_EXPANSION_RSVD2_MASK WBGEN2_GEN_MASK(3, 13)
#define MDIO_EXPANSION_RSVD2_SHIFT 3
#define MDIO_EXPANSION_RSVD2_W(value) WBGEN2_GEN_WRITE(value, 3, 13)
#define MDIO_EXPANSION_RSVD2_R(reg) WBGEN2_GEN_READ(reg, 3, 13)
/* definitions for register: MDIO Extended Status Register */
/* definitions for field: Reserved in reg: MDIO Extended Status Register */
#define MDIO_ESTATUS_RSVD1_MASK WBGEN2_GEN_MASK(0, 12)
#define MDIO_ESTATUS_RSVD1_SHIFT 0
#define MDIO_ESTATUS_RSVD1_W(value) WBGEN2_GEN_WRITE(value, 0, 12)
#define MDIO_ESTATUS_RSVD1_R(reg) WBGEN2_GEN_READ(reg, 0, 12)
/* definitions for field: 1000Base-T Half Duplex in reg: MDIO Extended Status Register */
#define MDIO_ESTATUS_1000_THALF_MASK WBGEN2_GEN_MASK(12, 1)
#define MDIO_ESTATUS_1000_THALF_SHIFT 12
#define MDIO_ESTATUS_1000_THALF_W(value) WBGEN2_GEN_WRITE(value, 12, 1)
#define MDIO_ESTATUS_1000_THALF_R(reg) WBGEN2_GEN_READ(reg, 12, 1)
/* definitions for field: 1000Base-T Full Duplex in reg: MDIO Extended Status Register */
#define MDIO_ESTATUS_1000_TFULL_MASK WBGEN2_GEN_MASK(13, 1)
#define MDIO_ESTATUS_1000_TFULL_SHIFT 13
#define MDIO_ESTATUS_1000_TFULL_W(value) WBGEN2_GEN_WRITE(value, 13, 1)
#define MDIO_ESTATUS_1000_TFULL_R(reg) WBGEN2_GEN_READ(reg, 13, 1)
/* definitions for field: 1000Base-X Half Duplex in reg: MDIO Extended Status Register */
#define MDIO_ESTATUS_1000_XHALF_MASK WBGEN2_GEN_MASK(14, 1)
#define MDIO_ESTATUS_1000_XHALF_SHIFT 14
#define MDIO_ESTATUS_1000_XHALF_W(value) WBGEN2_GEN_WRITE(value, 14, 1)
#define MDIO_ESTATUS_1000_XHALF_R(reg) WBGEN2_GEN_READ(reg, 14, 1)
/* definitions for field: 1000Base-X Full Duplex in reg: MDIO Extended Status Register */
#define MDIO_ESTATUS_1000_XFULL_MASK WBGEN2_GEN_MASK(15, 1)
#define MDIO_ESTATUS_1000_XFULL_SHIFT 15
#define MDIO_ESTATUS_1000_XFULL_W(value) WBGEN2_GEN_WRITE(value, 15, 1)
#define MDIO_ESTATUS_1000_XFULL_R(reg) WBGEN2_GEN_READ(reg, 15, 1)
/* definitions for register: WhiteRabbit-specific Configuration Register */
/* definitions for field: TX Calibration Pattern in reg: WhiteRabbit-specific Configuration Register */
#define MDIO_WR_SPEC_TX_CAL WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Calibration Pattern RX Status in reg: WhiteRabbit-specific Configuration Register */
#define MDIO_WR_SPEC_RX_CAL_STAT WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Reset calibration counter in reg: WhiteRabbit-specific Configuration Register */
#define MDIO_WR_SPEC_CAL_CRST WBGEN2_GEN_MASK(2, 1)
/* definitions for field: GTP RX Bitslide in reg: WhiteRabbit-specific Configuration Register */
#define MDIO_WR_SPEC_BSLIDE_MASK WBGEN2_GEN_MASK(4, 4)
#define MDIO_WR_SPEC_BSLIDE_SHIFT 4
#define MDIO_WR_SPEC_BSLIDE_W(value) WBGEN2_GEN_WRITE(value, 4, 4)
#define MDIO_WR_SPEC_BSLIDE_R(reg) WBGEN2_GEN_READ(reg, 4, 4)
/* [0x0]: REG MDIO Control Register */
#define MDIO_REG_MCR 0x00000000
/* [0x4]: REG MDIO Status Register */
#define MDIO_REG_MSR 0x00000004
/* [0x8]: REG MDIO PHY Identification Register 1 */
#define MDIO_REG_PHYSID1 0x00000008
/* [0xc]: REG MDIO PHY Identification Register 2 */
#define MDIO_REG_PHYSID2 0x0000000c
/* [0x10]: REG MDIO Auto-Negotiation Advertisement Register */
#define MDIO_REG_ADVERTISE 0x00000010
/* [0x14]: REG MDIO Auto-Negotiation Link Partner Ability Register */
#define MDIO_REG_LPA 0x00000014
/* [0x18]: REG MDIO Auto-Negotiation Expansion Register */
#define MDIO_REG_EXPANSION 0x00000018
/* [0x3c]: REG MDIO Extended Status Register */
#define MDIO_REG_ESTATUS 0x0000003c
/* [0x40]: REG WhiteRabbit-specific Configuration Register */
#define MDIO_REG_WR_SPEC 0x00000040
#endif
include/hw/endpoint_regs.h 0 → 100644
View file @ 1f9ac2c0
/*
Register definitions for slave core: WR switch endpoint controller
* File : endpoint_regs.h
* Author : auto-generated by wbgen2 from ep_wishbone_controller.wb
* Created : Wed Apr 6 22:46:02 2011
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE ep_wishbone_controller.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_EP_WISHBONE_CONTROLLER_WB
#define __WBGEN2_REGDEFS_EP_WISHBONE_CONTROLLER_WB
#include <inttypes.h>
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: Endpoint Control Register */
/* definitions for field: Port identifier in reg: Endpoint Control Register */
#define EP_ECR_PORTID_MASK WBGEN2_GEN_MASK(0, 5)
#define EP_ECR_PORTID_SHIFT 0
#define EP_ECR_PORTID_W(value) WBGEN2_GEN_WRITE(value, 0, 5)
#define EP_ECR_PORTID_R(reg) WBGEN2_GEN_READ(reg, 0, 5)
/* definitions for field: Reset event counters in reg: Endpoint Control Register */
#define EP_ECR_RST_CNT WBGEN2_GEN_MASK(5, 1)
/* definitions for field: Transmit framer enable in reg: Endpoint Control Register */
#define EP_ECR_TX_EN_FRA WBGEN2_GEN_MASK(6, 1)
/* definitions for field: Receive deframer enable in reg: Endpoint Control Register */
#define EP_ECR_RX_EN_FRA WBGEN2_GEN_MASK(7, 1)
/* definitions for register: Timestamping Control Register */
/* definitions for field: Transmit timestamping enable in reg: Timestamping Control Register */
#define EP_TSCR_EN_TXTS WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Receive timestamping enable in reg: Timestamping Control Register */
#define EP_TSCR_EN_RXTS WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Timestamping counter synchronization start in reg: Timestamping Control Register */
#define EP_TSCR_CS_START WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Timestamping counter synchronization done in reg: Timestamping Control Register */
#define EP_TSCR_CS_DONE WBGEN2_GEN_MASK(3, 1)
/* definitions for register: RX Deframer Control Register */
/* definitions for field: RX accept runts in reg: RX Deframer Control Register */
#define EP_RFCR_A_RUNT WBGEN2_GEN_MASK(0, 1)
/* definitions for field: RX accept giants in reg: RX Deframer Control Register */
#define EP_RFCR_A_GIANT WBGEN2_GEN_MASK(1, 1)
/* definitions for field: RX accept HP in reg: RX Deframer Control Register */
#define EP_RFCR_A_HP WBGEN2_GEN_MASK(2, 1)
/* definitions for field: RX accept fragments in reg: RX Deframer Control Register */
#define EP_RFCR_A_FRAG WBGEN2_GEN_MASK(3, 1)
/* definitions for field: RX 802.1q port mode in reg: RX Deframer Control Register */
#define EP_RFCR_QMODE_MASK WBGEN2_GEN_MASK(4, 2)
#define EP_RFCR_QMODE_SHIFT 4
#define EP_RFCR_QMODE_W(value) WBGEN2_GEN_WRITE(value, 4, 2)
#define EP_RFCR_QMODE_R(reg) WBGEN2_GEN_READ(reg, 4, 2)
/* definitions for field: Force 802.1q priority in reg: RX Deframer Control Register */
#define EP_RFCR_FIX_PRIO WBGEN2_GEN_MASK(6, 1)
/* definitions for field: Port-assigned 802.1x priority in reg: RX Deframer Control Register */
#define EP_RFCR_PRIO_VAL_MASK WBGEN2_GEN_MASK(8, 3)
#define EP_RFCR_PRIO_VAL_SHIFT 8
#define EP_RFCR_PRIO_VAL_W(value) WBGEN2_GEN_WRITE(value, 8, 3)
#define EP_RFCR_PRIO_VAL_R(reg) WBGEN2_GEN_READ(reg, 8, 3)
/* definitions for field: Port-assigned VID in reg: RX Deframer Control Register */
#define EP_RFCR_VID_VAL_MASK WBGEN2_GEN_MASK(16, 12)
#define EP_RFCR_VID_VAL_SHIFT 16
#define EP_RFCR_VID_VAL_W(value) WBGEN2_GEN_WRITE(value, 16, 12)
#define EP_RFCR_VID_VAL_R(reg) WBGEN2_GEN_READ(reg, 16, 12)
/* definitions for register: Flow Control Register */
/* definitions for field: RX Pause enable in reg: Flow Control Register */
#define EP_FCR_RXPAUSE WBGEN2_GEN_MASK(0, 1)
/* definitions for field: TX Pause enable in reg: Flow Control Register */
#define EP_FCR_TXPAUSE WBGEN2_GEN_MASK(1, 1)
/* definitions for field: TX pause threshold in reg: Flow Control Register */
#define EP_FCR_TX_THR_MASK WBGEN2_GEN_MASK(8, 8)
#define EP_FCR_TX_THR_SHIFT 8
#define EP_FCR_TX_THR_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
#define EP_FCR_TX_THR_R(reg) WBGEN2_GEN_READ(reg, 8, 8)
/* definitions for field: TX pause quanta in reg: Flow Control Register */
#define EP_FCR_TX_QUANTA_MASK WBGEN2_GEN_MASK(16, 16)
#define EP_FCR_TX_QUANTA_SHIFT 16
#define EP_FCR_TX_QUANTA_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define EP_FCR_TX_QUANTA_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: Endpoint MAC address high part register */
/* definitions for register: Endpoint MAC address low part register */
/* definitions for register: DMTD Control Register */
/* definitions for field: DMTD Phase measurement enable in reg: DMTD Control Register */
#define EP_DMCR_EN WBGEN2_GEN_MASK(0, 1)
/* definitions for field: DMTD averaging samples in reg: DMTD Control Register */
#define EP_DMCR_N_AVG_MASK WBGEN2_GEN_MASK(16, 12)
#define EP_DMCR_N_AVG_SHIFT 16
#define EP_DMCR_N_AVG_W(value) WBGEN2_GEN_WRITE(value, 16, 12)
#define EP_DMCR_N_AVG_R(reg) WBGEN2_GEN_READ(reg, 16, 12)
/* definitions for register: DMTD Status register */
/* definitions for field: DMTD Phase shift value in reg: DMTD Status register */
#define EP_DMSR_PS_VAL_MASK WBGEN2_GEN_MASK(0, 24)
#define EP_DMSR_PS_VAL_SHIFT 0
#define EP_DMSR_PS_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 24)
#define EP_DMSR_PS_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 24)
/* definitions for field: DMTD Phase shift value ready in reg: DMTD Status register */
#define EP_DMSR_PS_RDY WBGEN2_GEN_MASK(24, 1)
/* definitions for register: MDIO Control Register */
/* definitions for field: MDIO Register Value in reg: MDIO Control Register */
#define EP_MDIO_CR_DATA_MASK WBGEN2_GEN_MASK(0, 16)
#define EP_MDIO_CR_DATA_SHIFT 0
#define EP_MDIO_CR_DATA_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define EP_MDIO_CR_DATA_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: MDIO Register Address in reg: MDIO Control Register */
#define EP_MDIO_CR_ADDR_MASK WBGEN2_GEN_MASK(16, 8)
#define EP_MDIO_CR_ADDR_SHIFT 16
#define EP_MDIO_CR_ADDR_W(value) WBGEN2_GEN_WRITE(value, 16, 8)
#define EP_MDIO_CR_ADDR_R(reg) WBGEN2_GEN_READ(reg, 16, 8)
/* definitions for field: MDIO Read/Write select in reg: MDIO Control Register */
#define EP_MDIO_CR_RW WBGEN2_GEN_MASK(31, 1)
/* definitions for register: MDIO Status Register */
/* definitions for field: MDIO Read Value in reg: MDIO Status Register */
#define EP_MDIO_SR_RDATA_MASK WBGEN2_GEN_MASK(0, 16)
#define EP_MDIO_SR_RDATA_SHIFT 0
#define EP_MDIO_SR_RDATA_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define EP_MDIO_SR_RDATA_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: MDIO Ready in reg: MDIO Status Register */
#define EP_MDIO_SR_READY WBGEN2_GEN_MASK(31, 1)
/* definitions for register: Identification register */
/* definitions for register: Debug/Status register */
/* definitions for field: Link status in reg: Debug/Status register */
#define EP_DSR_LSTATUS WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Link activity in reg: Debug/Status register */
#define EP_DSR_LACT WBGEN2_GEN_MASK(1, 1)
/* definitions for RAM: Event counters memory */
#define EP_RMON_RAM_BYTES 0x00000080 /* size in bytes */
#define EP_RMON_RAM_WORDS 0x00000020 /* size in 32-bit words, 32-bit aligned */
PACKED struct EP_WB {
/* [0x0]: REG Endpoint Control Register */
uint32_t ECR;
/* [0x4]: REG Timestamping Control Register */
uint32_t TSCR;
/* [0x8]: REG RX Deframer Control Register */
uint32_t RFCR;
/* [0xc]: REG Flow Control Register */
uint32_t FCR;
/* [0x10]: REG Endpoint MAC address high part register */
uint32_t MACH;
/* [0x14]: REG Endpoint MAC address low part register */
uint32_t MACL;
/* [0x18]: REG DMTD Control Register */
uint32_t DMCR;
/* [0x1c]: REG DMTD Status register */
uint32_t DMSR;
/* [0x20]: REG MDIO Control Register */
uint32_t MDIO_CR;
/* [0x24]: REG MDIO Status Register */
uint32_t MDIO_SR;
/* [0x28]: REG Identification register */
uint32_t IDCODE;
/* [0x2c]: REG Debug/Status register */
uint32_t DSR;
/* padding to: 32 words */
uint32_t __padding_0[20];
/* [0x80 - 0xff]: RAM Event counters memory, 32 32-bit words, 32-bit aligned, word-addressable */
uint32_t RMON_RAM [32];
};
#endif
include/hw/minic_regs.h 0 → 100644
View file @ 1f9ac2c0
/*
Register definitions for slave core: Mini NIC for WhiteRabbit
* File : ../../../software/include/hw/minic_regs.h
* Author : auto-generated by wbgen2 from mini_nic.wb
* Created : Fri Aug 13 02:17:20 2010
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE mini_nic.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_MINI_NIC_WB
#define __WBGEN2_REGDEFS_MINI_NIC_WB
#include <inttypes.h>
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: miNIC Control Register */
/* definitions for field: TX DMA start in reg: miNIC Control Register */
#define MINIC_MCR_TX_START WBGEN2_GEN_MASK(0, 1)
/* definitions for field: TX DMA idle in reg: miNIC Control Register */
#define MINIC_MCR_TX_IDLE WBGEN2_GEN_MASK(1, 1)
/* definitions for field: TX DMA error in reg: miNIC Control Register */
#define MINIC_MCR_TX_ERROR WBGEN2_GEN_MASK(2, 1)
/* definitions for field: RX DMA ready in reg: miNIC Control Register */
#define MINIC_MCR_RX_READY WBGEN2_GEN_MASK(8, 1)
/* definitions for field: RX DMA buffer full in reg: miNIC Control Register */
#define MINIC_MCR_RX_FULL WBGEN2_GEN_MASK(9, 1)
/* definitions for field: RX DMA enable in reg: miNIC Control Register */
#define MINIC_MCR_RX_EN WBGEN2_GEN_MASK(10, 1)
/* definitions for register: TX DMA Address */
/* definitions for register: RX DMA Address */
/* definitions for register: RX buffer size register */
/* definitions for register: Debug register */
/* definitions for field: interrupt counter in reg: Debug register */
#define MINIC_DBGR_IRQ_CNT_MASK WBGEN2_GEN_MASK(0, 24)
#define MINIC_DBGR_IRQ_CNT_SHIFT 0
#define MINIC_DBGR_IRQ_CNT_W(value) WBGEN2_GEN_WRITE(value, 0, 24)
#define MINIC_DBGR_IRQ_CNT_R(reg) WBGEN2_GEN_READ(reg, 0, 24)
/* definitions for field: status of wb_irq_o line in reg: Debug register */
#define MINIC_DBGR_WB_IRQ_VAL WBGEN2_GEN_MASK(24, 1)
/* definitions for register: Interrupt disable register */
/* definitions for field: TX DMA interrupt in reg: Interrupt disable register */
#define MINIC_EIC_IDR_TX WBGEN2_GEN_MASK(0, 1)
/* definitions for field: RX DMA interrupt in reg: Interrupt disable register */
#define MINIC_EIC_IDR_RX WBGEN2_GEN_MASK(1, 1)
/* definitions for field: TX timestamp available in reg: Interrupt disable register */
#define MINIC_EIC_IDR_TXTS WBGEN2_GEN_MASK(2, 1)
/* definitions for register: Interrupt enable register */
/* definitions for field: TX DMA interrupt in reg: Interrupt enable register */
#define MINIC_EIC_IER_TX WBGEN2_GEN_MASK(0, 1)
/* definitions for field: RX DMA interrupt in reg: Interrupt enable register */
#define MINIC_EIC_IER_RX WBGEN2_GEN_MASK(1, 1)
/* definitions for field: TX timestamp available in reg: Interrupt enable register */
#define MINIC_EIC_IER_TXTS WBGEN2_GEN_MASK(2, 1)
/* definitions for register: Interrupt mask register */
/* definitions for field: TX DMA interrupt in reg: Interrupt mask register */
#define MINIC_EIC_IMR_TX WBGEN2_GEN_MASK(0, 1)
/* definitions for field: RX DMA interrupt in reg: Interrupt mask register */
#define MINIC_EIC_IMR_RX WBGEN2_GEN_MASK(1, 1)
/* definitions for field: TX timestamp available in reg: Interrupt mask register */
#define MINIC_EIC_IMR_TXTS WBGEN2_GEN_MASK(2, 1)
/* definitions for register: Interrupt status register */
/* definitions for field: TX DMA interrupt in reg: Interrupt status register */
#define MINIC_EIC_ISR_TX WBGEN2_GEN_MASK(0, 1)
/* definitions for field: RX DMA interrupt in reg: Interrupt status register */
#define MINIC_EIC_ISR_RX WBGEN2_GEN_MASK(1, 1)
/* definitions for field: TX timestamp available in reg: Interrupt status register */
#define MINIC_EIC_ISR_TXTS WBGEN2_GEN_MASK(2, 1)
/* definitions for register: FIFO 'TX timestamp FIFO' data output register 0 */
/* definitions for field: Timestamp value in reg: FIFO 'TX timestamp FIFO' data output register 0 */
#define MINIC_TSFIFO_R0_TSVAL_MASK WBGEN2_GEN_MASK(0, 32)
#define MINIC_TSFIFO_R0_TSVAL_SHIFT 0
#define MINIC_TSFIFO_R0_TSVAL_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define MINIC_TSFIFO_R0_TSVAL_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: FIFO 'TX timestamp FIFO' data output register 1 */
/* definitions for field: Port ID in reg: FIFO 'TX timestamp FIFO' data output register 1 */
#define MINIC_TSFIFO_R1_PID_MASK WBGEN2_GEN_MASK(0, 5)
#define MINIC_TSFIFO_R1_PID_SHIFT 0
#define MINIC_TSFIFO_R1_PID_W(value) WBGEN2_GEN_WRITE(value, 0, 5)
#define MINIC_TSFIFO_R1_PID_R(reg) WBGEN2_GEN_READ(reg, 0, 5)
/* definitions for field: Frame ID in reg: FIFO 'TX timestamp FIFO' data output register 1 */
#define MINIC_TSFIFO_R1_FID_MASK WBGEN2_GEN_MASK(5, 16)
#define MINIC_TSFIFO_R1_FID_SHIFT 5
#define MINIC_TSFIFO_R1_FID_W(value) WBGEN2_GEN_WRITE(value, 5, 16)
#define MINIC_TSFIFO_R1_FID_R(reg) WBGEN2_GEN_READ(reg, 5, 16)
/* definitions for register: FIFO 'TX timestamp FIFO' control/status register */
/* definitions for field: FIFO empty flag in reg: FIFO 'TX timestamp FIFO' control/status register */
#define MINIC_TSFIFO_CSR_EMPTY WBGEN2_GEN_MASK(17, 1)
/* [0x0]: REG miNIC Control Register */
#define MINIC_REG_MCR 0x00000000
/* [0x4]: REG TX DMA Address */
#define MINIC_REG_TX_ADDR 0x00000004
/* [0x8]: REG RX DMA Address */
#define MINIC_REG_RX_ADDR 0x00000008
/* [0xc]: REG RX buffer size register */
#define MINIC_REG_RX_AVAIL 0x0000000c
/* [0x10]: REG Debug register */
#define MINIC_REG_DBGR 0x00000010
/* [0x20]: REG Interrupt disable register */
#define MINIC_REG_EIC_IDR 0x00000020
/* [0x24]: REG Interrupt enable register */
#define MINIC_REG_EIC_IER 0x00000024
/* [0x28]: REG Interrupt mask register */
#define MINIC_REG_EIC_IMR 0x00000028
/* [0x2c]: REG Interrupt status register */
#define MINIC_REG_EIC_ISR 0x0000002c
/* [0x30]: REG FIFO 'TX timestamp FIFO' data output register 0 */
#define MINIC_REG_TSFIFO_R0 0x00000030
/* [0x34]: REG FIFO 'TX timestamp FIFO' data output register 1 */
#define MINIC_REG_TSFIFO_R1 0x00000034
/* [0x38]: REG FIFO 'TX timestamp FIFO' control/status register */
#define MINIC_REG_TSFIFO_CSR 0x00000038
#endif
include/hw/pps_gen_regs.h 0 → 100644
View file @ 1f9ac2c0
/*
Register definitions for slave core: WR Switch PPS generator and RTC
* File : ../../../software/include/hw/pps_gen_regs.h
* Author : auto-generated by wbgen2 from wrsw_pps_gen.wb
* Created : Sat Sep 11 22:22:55 2010
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrsw_pps_gen.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_WRSW_PPS_GEN_WB
#define __WBGEN2_REGDEFS_WRSW_PPS_GEN_WB
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: Control Register */
/* definitions for field: Reset counter in reg: Control Register */
#define PPSG_CR_CNT_RST WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Enable counter in reg: Control Register */
#define PPSG_CR_CNT_EN WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Adjust offset in reg: Control Register */
#define PPSG_CR_CNT_ADJ WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Set time in reg: Control Register */
#define PPSG_CR_CNT_SET WBGEN2_GEN_MASK(3, 1)
/* definitions for field: PPS Pulse width in reg: Control Register */
#define PPSG_CR_PWIDTH_MASK WBGEN2_GEN_MASK(4, 28)
#define PPSG_CR_PWIDTH_SHIFT 4
#define PPSG_CR_PWIDTH_W(value) WBGEN2_GEN_WRITE(value, 4, 28)
#define PPSG_CR_PWIDTH_R(reg) WBGEN2_GEN_READ(reg, 4, 28)
/* definitions for register: Nanosecond counter register */
/* definitions for register: UTC Counter register (least-significant part) */
/* definitions for register: UTC Counter register (most-significant part) */
/* definitions for register: Nanosecond adjustment register */
/* definitions for register: UTC Adjustment register (least-significant part) */
/* definitions for register: UTC Adjustment register (most-significant part) */
/* [0x0]: REG Control Register */
#define PPSG_REG_CR 0x00000000
/* [0x4]: REG Nanosecond counter register */
#define PPSG_REG_CNTR_NSEC 0x00000004
/* [0x8]: REG UTC Counter register (least-significant part) */
#define PPSG_REG_CNTR_UTCLO 0x00000008
/* [0xc]: REG UTC Counter register (most-significant part) */
#define PPSG_REG_CNTR_UTCHI 0x0000000c
/* [0x10]: REG Nanosecond adjustment register */
#define PPSG_REG_ADJ_NSEC 0x00000010
/* [0x14]: REG UTC Adjustment register (least-significant part) */
#define PPSG_REG_ADJ_UTCLO 0x00000014
/* [0x18]: REG UTC Adjustment register (most-significant part) */
#define PPSG_REG_ADJ_UTCHI 0x00000018
#endif
include/hw/wb_uart.h 0 → 100644
View file @ 1f9ac2c0
/*
Register definitions for slave core: Simple Wishbone UART
* File : ../../../../software/include/hw/wb_uart.h
* Author : auto-generated by wbgen2 from uart.wb
* Created : Mon Feb 21 22:25:02 2011
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE uart.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_UART_WB
#define __WBGEN2_REGDEFS_UART_WB
#include <inttypes.h>
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: Status Register */
/* definitions for field: TX busy in reg: Status Register */
#define UART_SR_TX_BUSY WBGEN2_GEN_MASK(0, 1)
/* definitions for field: RX ready in reg: Status Register */
#define UART_SR_RX_RDY WBGEN2_GEN_MASK(1, 1)
/* definitions for register: Baudrate control register */
/* definitions for register: Transmit data regsiter */
/* definitions for field: Transmit data in reg: Transmit data regsiter */
#define UART_TDR_TX_DATA_MASK WBGEN2_GEN_MASK(0, 8)
#define UART_TDR_TX_DATA_SHIFT 0
#define UART_TDR_TX_DATA_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
#define UART_TDR_TX_DATA_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
/* definitions for register: Receive data regsiter */
/* definitions for field: Received data in reg: Receive data regsiter */
#define UART_RDR_RX_DATA_MASK WBGEN2_GEN_MASK(0, 8)
#define UART_RDR_RX_DATA_SHIFT 0
#define UART_RDR_RX_DATA_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
#define UART_RDR_RX_DATA_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
/* [0x0]: REG Status Register */
#define UART_REG_SR 0x00000000
/* [0x4]: REG Baudrate control register */
#define UART_REG_BCR 0x00000004
/* [0x8]: REG Transmit data regsiter */
#define UART_REG_TDR 0x00000008
/* [0xc]: REG Receive data regsiter */
#define UART_REG_RDR 0x0000000c
PACKED struct UART_WB {
/* [0x0]: REG Status Register */
uint32_t SR;
/* [0x4]: REG Baudrate control register */
uint32_t BCR;
/* [0x8]: REG Transmit data regsiter */
uint32_t TDR;
/* [0xc]: REG Receive data regsiter */
uint32_t RDR;
};
#endif
include/hw/wb_vuart.h 0 → 100644
View file @ 1f9ac2c0
/*
Register definitions for slave core: Virtual UART
* File : wb_vuart.h
* Author : auto-generated by wbgen2 from wb_virtual_uart.wb
* Created : Wed Apr 6 23:02:01 2011
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wb_virtual_uart.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_WB_VIRTUAL_UART_WB
#define __WBGEN2_REGDEFS_WB_VIRTUAL_UART_WB
#include <inttypes.h>
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: Status Register */
/* definitions for field: TX busy in reg: Status Register */
#define UART_SR_TX_BUSY WBGEN2_GEN_MASK(0, 1)
/* definitions for field: RX ready in reg: Status Register */
#define UART_SR_RX_RDY WBGEN2_GEN_MASK(1, 1)
/* definitions for register: Baudrate control register */
/* definitions for register: Transmit data regsiter */
/* definitions for field: Transmit data in reg: Transmit data regsiter */
#define UART_TDR_TX_DATA_MASK WBGEN2_GEN_MASK(0, 8)
#define UART_TDR_TX_DATA_SHIFT 0
#define UART_TDR_TX_DATA_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
#define UART_TDR_TX_DATA_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
/* definitions for register: Receive data regsiter */
/* definitions for field: Received data in reg: Receive data regsiter */
#define UART_RDR_RX_DATA_MASK WBGEN2_GEN_MASK(0, 8)
#define UART_RDR_RX_DATA_SHIFT 0
#define UART_RDR_RX_DATA_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
#define UART_RDR_RX_DATA_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
/* definitions for register: FIFO 'UART TX FIFO' data output register 0 */
/* definitions for field: Char sent by UART to TX in reg: FIFO 'UART TX FIFO' data output register 0 */
#define UART_DEBUG_R0_TX_MASK WBGEN2_GEN_MASK(0, 8)
#define UART_DEBUG_R0_TX_SHIFT 0
#define UART_DEBUG_R0_TX_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
#define UART_DEBUG_R0_TX_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
/* definitions for register: FIFO 'UART TX FIFO' control/status register */
/* definitions for field: FIFO full flag in reg: FIFO 'UART TX FIFO' control/status register */
#define UART_DEBUG_CSR_FULL WBGEN2_GEN_MASK(16, 1)
/* definitions for field: FIFO empty flag in reg: FIFO 'UART TX FIFO' control/status register */
#define UART_DEBUG_CSR_EMPTY WBGEN2_GEN_MASK(17, 1)
/* definitions for field: FIFO counter in reg: FIFO 'UART TX FIFO' control/status register */
#define UART_DEBUG_CSR_USEDW_MASK WBGEN2_GEN_MASK(0, 8)
#define UART_DEBUG_CSR_USEDW_SHIFT 0
#define UART_DEBUG_CSR_USEDW_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
#define UART_DEBUG_CSR_USEDW_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
PACKED struct UART_WB {
/* [0x0]: REG Status Register */
uint32_t SR;
/* [0x4]: REG Baudrate control register */
uint32_t BCR;
/* [0x8]: REG Transmit data regsiter */
uint32_t TDR;
/* [0xc]: REG Receive data regsiter */
uint32_t RDR;
/* [0x10]: REG FIFO 'UART TX FIFO' data output register 0 */
uint32_t DEBUG_R0;
/* [0x14]: REG FIFO 'UART TX FIFO' control/status register */
uint32_t DEBUG_CSR;
};
#endif
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