Commit 1c028e8e authored by Grzegorz Daniluk's avatar Grzegorz Daniluk

Merge branch 'minic_fifo' into proposed_master

parents 077dab43 6c2f298d
This diff is collapsed.
......@@ -3,7 +3,7 @@
* File : minic_regs.h
* Author : auto-generated by wbgen2 from mini_nic.wb
* Created : Thu Mar 7 14:45:52 2013
* Created : Thu Oct 27 16:54:11 2016
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE mini_nic.wb
......@@ -42,11 +42,17 @@
/* definitions for field: TX DMA error in reg: miNIC Control Register */
#define MINIC_MCR_TX_ERROR WBGEN2_GEN_MASK(2, 1)
/* definitions for field: TX_FIFO_EMPTY in reg: miNIC Control Register */
#define MINIC_MCR_TX_EMPTY WBGEN2_GEN_MASK(3, 1)
/* definitions for field: TX_FIFO_FULL in reg: miNIC Control Register */
#define MINIC_MCR_TX_FULL WBGEN2_GEN_MASK(4, 1)
/* definitions for field: RX DMA ready in reg: miNIC Control Register */
#define MINIC_MCR_RX_READY WBGEN2_GEN_MASK(8, 1)
/* definitions for field: RX DMA buffer full in reg: miNIC Control Register */
#define MINIC_MCR_RX_FULL WBGEN2_GEN_MASK(9, 1)
/* definitions for field: RX DMA error in reg: miNIC Control Register */
#define MINIC_MCR_RX_ERROR WBGEN2_GEN_MASK(9, 1)
/* definitions for field: RX DMA enable in reg: miNIC Control Register */
#define MINIC_MCR_RX_EN WBGEN2_GEN_MASK(10, 1)
......@@ -54,19 +60,57 @@
/* definitions for field: TX TS ready in reg: miNIC Control Register */
#define MINIC_MCR_TX_TS_READY WBGEN2_GEN_MASK(11, 1)
/* definitions for field: RX_FIFO_EMPTY in reg: miNIC Control Register */
#define MINIC_MCR_RX_EMPTY WBGEN2_GEN_MASK(12, 1)
/* definitions for field: RX_FIFO_FULL in reg: miNIC Control Register */
#define MINIC_MCR_RX_FULL WBGEN2_GEN_MASK(13, 1)
/* definitions for field: RX Accepted Packet Classes in reg: miNIC Control Register */
#define MINIC_MCR_RX_CLASS_MASK WBGEN2_GEN_MASK(16, 8)
#define MINIC_MCR_RX_CLASS_SHIFT 16
#define MINIC_MCR_RX_CLASS_W(value) WBGEN2_GEN_WRITE(value, 16, 8)
#define MINIC_MCR_RX_CLASS_R(reg) WBGEN2_GEN_READ(reg, 16, 8)
/* definitions for register: TX DMA Address */
/* definitions for field: Regs map version in reg: miNIC Control Register */
#define MINIC_MCR_VER_MASK WBGEN2_GEN_MASK(24, 4)
#define MINIC_MCR_VER_SHIFT 24
#define MINIC_MCR_VER_W(value) WBGEN2_GEN_WRITE(value, 24, 4)
#define MINIC_MCR_VER_R(reg) WBGEN2_GEN_READ(reg, 24, 4)
/* definitions for register: TX FIFO Register */
/* definitions for field: Data to send in reg: TX FIFO Register */
#define MINIC_TX_FIFO_DAT_MASK WBGEN2_GEN_MASK(0, 16)
#define MINIC_TX_FIFO_DAT_SHIFT 0
#define MINIC_TX_FIFO_DAT_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define MINIC_TX_FIFO_DAT_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Data type in reg: TX FIFO Register */
#define MINIC_TX_FIFO_TYPE_MASK WBGEN2_GEN_MASK(16, 2)
#define MINIC_TX_FIFO_TYPE_SHIFT 16
#define MINIC_TX_FIFO_TYPE_W(value) WBGEN2_GEN_WRITE(value, 16, 2)
#define MINIC_TX_FIFO_TYPE_R(reg) WBGEN2_GEN_READ(reg, 16, 2)
/* definitions for register: RX FIFO Register */
/* definitions for field: Data to send in reg: RX FIFO Register */
#define MINIC_RX_FIFO_DAT_MASK WBGEN2_GEN_MASK(0, 16)
#define MINIC_RX_FIFO_DAT_SHIFT 0
#define MINIC_RX_FIFO_DAT_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define MINIC_RX_FIFO_DAT_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for register: RX DMA Address */
/* definitions for field: Data type in reg: RX FIFO Register */
#define MINIC_RX_FIFO_TYPE_MASK WBGEN2_GEN_MASK(16, 2)
#define MINIC_RX_FIFO_TYPE_SHIFT 16
#define MINIC_RX_FIFO_TYPE_W(value) WBGEN2_GEN_WRITE(value, 16, 2)
#define MINIC_RX_FIFO_TYPE_R(reg) WBGEN2_GEN_READ(reg, 16, 2)
/* definitions for register: RX buffer size register */
/* definitions for field: RX_FIFO_EMPTY in reg: RX FIFO Register */
#define MINIC_RX_FIFO_EMPTY WBGEN2_GEN_MASK(30, 1)
/* definitions for register: RX buffer available words register */
/* definitions for field: RX_FIFO_FULL in reg: RX FIFO Register */
#define MINIC_RX_FIFO_FULL WBGEN2_GEN_MASK(31, 1)
/* definitions for register: TX timestamp register 0 */
......@@ -163,14 +207,14 @@
#define MINIC_EIC_ISR_TXTS WBGEN2_GEN_MASK(2, 1)
/* [0x0]: REG miNIC Control Register */
#define MINIC_REG_MCR 0x00000000
/* [0x4]: REG TX DMA Address */
#define MINIC_REG_TX_ADDR 0x00000004
/* [0x8]: REG RX DMA Address */
#define MINIC_REG_RX_ADDR 0x00000008
/* [0xc]: REG RX buffer size register */
#define MINIC_REG_RX_SIZE 0x0000000c
/* [0x10]: REG RX buffer available words register */
#define MINIC_REG_RX_AVAIL 0x00000010
/* [0x4]: REG TX FIFO Register */
#define MINIC_REG_TX_FIFO 0x00000004
/* [0x8]: REG RX FIFO Register */
#define MINIC_REG_RX_FIFO 0x00000008
/* [0xc]: REG reserved 1 */
#define MINIC_REG_RESV_1 0x0000000c
/* [0x10]: REG reserved 2 */
#define MINIC_REG_RESV_2 0x00000010
/* [0x14]: REG TX timestamp register 0 */
#define MINIC_REG_TSR0 0x00000014
/* [0x18]: REG TX timestamp register 1 */
......
......@@ -14,6 +14,13 @@
#define WRPC_FID 0
#define WRF_DATA 0
#define WRF_OOB 1
#define WRF_STATUS 2
#define WRF_BYTESEL 3
#define TX_OOB 0x1000
void minic_init(void);
void minic_disable(void);
int minic_poll_rx(void);
......@@ -34,11 +41,6 @@ struct wr_ethhdr_vlan {
};
struct wr_minic {
volatile uint32_t *rx_head, *rx_base;
uint32_t rx_avail, rx_size;
volatile uint32_t *tx_head, *tx_base;
uint32_t tx_avail, tx_size;
int tx_count, rx_count;
};
......
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