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Software for White Rabbit PTP Core
Commit 1794bdc6 authored by Juan David González Cobas's avatar Juan David González Cobas
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Merge branch 'merge-sps-tom-rf' into david-libertm-devel

parents 70faae42 18ac0f1a
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Showing with 1393 additions and 443 deletions
Kconfig
View file @ 1794bdc6
......@@ -19,10 +19,15 @@ config TARGET_WR_SWITCH
help
Builds the rt_cpu.bin, for the WR Switch FPGA
config TARGET_AFCZ
bool "AFCZ FMC Carrier"
config TARGET_AFCZ_V2
bool "AFCZ FMC Carrier (V1)"
help
AFCZ FMC Carrier (Zynq Ultrascale+)
AFCZ FMC Carrier version 1 (Zynq Ultrascale+)
config TARGET_AFCZ_V2
bool "AFCZ FMC Carrier (V2, EXPERIMENTAL)"
help
AFCZ FMC Carrier version 2 (Zynq Ultrascale+)
config TARGET_ERTM14
bool "eRTM14/15 MTCA.4 WR Receiver"
......
boards/afcz/board.c
View file @ 1794bdc6
......@@ -468,7 +468,7 @@ static int measure_vcxo_freq( int cm_channel, int cm_ref, int gate_freq, int n_s
int f_min = 0, f_max = 0;
int tune_min = 3000;
int tune_max = 65535;
int tune_step = 1; //(tune_max-tune_min) / n_steps;
int tune_step = (tune_max-tune_min) / n_steps;
wb_cm_configure( &board.clk_mon, cm_ref, 5, gate_freq );
wb_cm_set_ref_frequency( &board.clk_mon, CPU_CLOCK );
......@@ -539,10 +539,14 @@ int afcz_check_clocks()
//check_vco_freq( AFCZ_CM_CHANNEL_CLK_REF, AFCZ_CM_CHANNEL_CLK_RX, set_main_dac );
board_dbg("Check REF VCXO (Si570)\n");
measure_vcxo_freq( AFCZ_CM_CHANNEL_CLK_REF, AFCZ_CM_CHANNEL_CLK_RX, 10000000, 10, 62500000, set_main_dac, NULL, NULL );
set_dmtd_dac(32768);
timer_delay_ms(10);
measure_vcxo_freq( AFCZ_CM_CHANNEL_CLK_REF, AFCZ_CM_CHANNEL_CLK_DMTD, 10000000, 4, 62500000, set_main_dac, NULL, NULL );
board_dbg("Check DMTD VCXO\n");
measure_vcxo_freq( AFCZ_CM_CHANNEL_CLK_DMTD, AFCZ_CM_CHANNEL_CLK_RX, 100000, 10, 62500000, set_dmtd_dac, NULL, NULL );
set_main_dac(32768);
timer_delay_ms(10);
measure_vcxo_freq( AFCZ_CM_CHANNEL_CLK_DMTD, AFCZ_CM_CHANNEL_CLK_REF, 100000, 4, 62500000, set_dmtd_dac, NULL, NULL );
return 0;
}
......@@ -614,8 +618,8 @@ static void sfp_setup(void)
}
static void afcz_read_persistent_mac(void)
#if 0
static void afczv1_read_persistent_mac(void)
{
uint8_t mac_addr[6];
......@@ -651,6 +655,55 @@ static void afcz_read_persistent_mac(void)
mac_addr[4], mac_addr[5]);
ep_set_mac_addr( &board.ep_btrain, mac_addr );
}
#endif
static void afczv2_read_dna_mac( uint8_t *mac )
{
uint32_t id, ver, nrw, nro;
uint32_t sn;
uint32_t dna[3];
diag_read_info(&id, &ver, &nrw, &nro );
board_dbg("diags: id %d ver %d nrw %d nro %d\n", id, ver, nrw, nro );
diag_read_word(nro - 4, DIAG_RO_BANK, &dna[0] );
diag_read_word(nro - 3, DIAG_RO_BANK, &dna[1] );
diag_read_word(nro - 2, DIAG_RO_BANK, &dna[2] );
diag_read_word(nro - 1, DIAG_RO_BANK, &sn );
board_dbg("S/N %x DNA %08x %08x %08x\n", sn, dna[0], dna[1], dna[2] );
// well, we can't do anything else than generate this crap from the device's DNA. The serial numbers
// provided by the MMC don't appear to be really UNIQUE...
uint32_t seed = dna[0] ^ dna[1] ^ dna[2];
mac[0] = 0x22;
mac[1] = 0x33;
mac[2] = (seed >> 24) & 0xff;
mac[3] = (seed >> 16) & 0xff;
mac[4] = (seed >> 8) & 0xff;
mac[5] = seed & 0xff;
}
static void afczv2_read_persistent_mac(void)
{
uint8_t mac_addr[6];
afczv2_read_dna_mac( mac_addr );
board_dbg("Local MAC address from device DNA: %02x:%02x:%02x:%02x:%02x:%02x\n",
mac_addr[0], mac_addr[1], mac_addr[2], mac_addr[3],
mac_addr[4], mac_addr[5]);
ep_set_mac_addr( &wrc_endpoint_dev, mac_addr );
/* ugly hack, but what can I do about this crappy card (with 8 network interfaces)
having a single MAC address chip? */
mac_addr[2] += 1;
board_dbg("B-Train MAC address from device DNA: %02x:%02x:%02x:%02x:%02x:%02x\n",
mac_addr[0], mac_addr[1], mac_addr[2], mac_addr[3],
mac_addr[4], mac_addr[5]);
ep_set_mac_addr( &board.ep_btrain, mac_addr );
}
int wrc_board_early_init()
......@@ -658,8 +711,12 @@ int wrc_board_early_init()
// wb_gpio_create( &board.gpio_aux, 0x48000 );
board_dbg("WR Core AFCZ port starting up\n");
wr_si57x_interface_init( &board.si57x, (void *) BASE_SI57X_INTERFACE, SI57X_I2C_ADDR );
#if defined(CONFIG_TARGET_AFCZ_V1)
tca9548_select_channels( &board.si57x.master, 0x70, 1 << AFCZ_I2C_MUX_CHANNEL_SI570 );
#endif
uint8_t regs[16];
......@@ -674,6 +731,7 @@ int wrc_board_early_init()
si57x_get_xtal_frequency( &board.si57x, &f_xtal );
si57x_set_frequency( &board.si57x, f_xtal, 125000000 );
#if defined(CONFIG_TARGET_AFCZ_V1)
idt8v_clock_mux_init ( &board.clk_mux, &board.si57x.master, IDT8V_I2C_ADDR );
idt8v_configure_io ( &board.clk_mux, AFCZ_IC33_CLK_SI570_1_IN, 1, 1, 0);
idt8v_configure_io ( &board.clk_mux, AFCZ_IC33_CLK_SI570_2_IN, 1, 1, 0);
......@@ -681,12 +739,14 @@ int wrc_board_early_init()
idt8v_configure_io ( &board.clk_mux, AFCZ_IC33_FPGA_CLK_GTX_CUST2_OUT, 0, 0, AFCZ_IC33_CLK_SI570_1_IN);
idt8v_configure_io ( &board.clk_mux, AFCZ_IC33_FPGA_FMC2_CLK2_BIDIR_OUT, 0, 0, AFCZ_IC33_CLK_SI570_1_IN);
idt8v_configure_io ( &board.clk_mux, 10, 0, 0, AFCZ_IC33_CLK_SI570_1_IN);
idt8v_commit_configuration ( &board.clk_mux );
#endif
wb_cm_init( &board.clk_mon, BASE_CLOCK_MONITOR, 6 );
#if defined(CONFIG_TARGET_AFCZ_V1)
sfp_setup();
#endif
net_rst();
ep_init( &wrc_endpoint_dev, (void *) BASE_WR_ENDPOINT_MAIN );
......@@ -694,7 +754,14 @@ int wrc_board_early_init()
netif_register_device( "wru0", "default", &wrc_endpoint_dev );
netif_register_device( "wru1", "btrain", &board.ep_btrain );
afcz_read_persistent_mac();
#if defined (CONFIG_TARGET_AFCZ_V1)
afczv1_read_persistent_mac();
#endif
#if defined (CONFIG_TARGET_AFCZ_V2)
afczv2_read_persistent_mac();
#endif
/* Sleep for 1s to make sure WRS v4.2 always realizes that
* the link is down */
......@@ -703,26 +770,28 @@ int wrc_board_early_init()
ep_enable( &board.ep_btrain, 1, 1);
timer_delay_ms(200);
#if defined(CONFIG_TARGET_AFCZ_V1)
tca9548_select_channels( &board.si57x.master, 0x70, 1 << AFCZ_I2C_MUX_CHANNEL_SI570 );
#endif
#if 1
#if 0
set_dmtd_dac(32767);
set_main_dac(30000);
ep_reset_phy(&wrc_endpoint_dev);
//afcz_check_clocks();
afcz_check_clocks();
// cross-check the REF and DDMTD clocks
/* wb_cm_configure( &board.clk_mon, AFCZ_CM_CHANNEL_CLK_DMTD, 5, 1000000 );
wb_cm_configure( &board.clk_mon, AFCZ_CM_CHANNEL_CLK_DMTD, 5, 1000000 );
wb_cm_set_ref_frequency( &board.clk_mon, CPU_CLOCK );
wb_cm_restart( &board.clk_mon );
timer_delay_ms(4000);
wb_cm_read( &board.clk_mon );
wb_cm_show( &board.clk_mon );
}*/
#endif
return 0;
}
......
boards/afcz/board.h
View file @ 1794bdc6
......@@ -21,6 +21,7 @@
#define BASE_ONEWIRE 0x20600
#define BASE_SOFTPLL 0x20200
#define BASE_PPS_GEN 0x20300
#define BASE_WDIAGS_PRIV 0x20900
#define BASE_AUXWB 0x28000
#define BASE_SI57X_INTERFACE (BASE_AUXWB + 0x80)
......
boards/boards.mk
View file @ 1794bdc6
obj-$(CONFIG_TARGET_GENERIC_PHY_8BIT) += boards/generic/board.o
obj-$(CONFIG_TARGET_GENERIC_PHY_16BIT) += boards/generic/board.o
obj-$(CONFIG_TARGET_WR_SWITCH) += boards/wr-switch/main.o boards/wr-switch/gpio-wrs.o boards/wr-switch/ad9516.o
obj-$(CONFIG_TARGET_AFCZ) += boards/afcz/board.o
obj-$(CONFIG_TARGET_AFCZ_V1) += boards/afcz/board.o
obj-$(CONFIG_TARGET_AFCZ_V2) += boards/afcz/board.o
obj-$(CONFIG_TARGET_SIS8300KU) += boards/sis8300ku/board.o
obj-$(CONFIG_TARGET_ERTM14) += boards/ertm14/board.o boards/ertm14/ertm15_rf_distr.o boards/ertm14/phy_calibration.o boards/ertm14/rf_frame_transceiver.o boards/ertm14/cmd_ertm14.o boards/ertm14/sdbfs-custom-image.o
obj-$(CONFIG_TARGET_ERTM14) += boards/ertm14/common-uart-link.o boards/ertm14/wrpc-uart-link.o
......
boards/ertm14/board-state.h
View file @ 1794bdc6
......@@ -241,6 +241,6 @@ struct ertm14_version_info {
};
/* FIXME: this is not the best place for this declaration */
int wrc_diags_dump(struct WRC_DIAGS_WB *buf);
int wrc_diags_dump(struct wrc_diags *buf);
#endif /* __BOARD_STATE_ERTM14_H */
boards/ertm14/board.c
View file @ 1794bdc6
......@@ -40,11 +40,11 @@
#include "dev/74x595.h"
#include "dev/netif.h"
#include "dev/leds.h"
#include "dev/wdiags.h"
#include "hw/wrc_diags_regs.h"
#include "revision.h"
/* FIXME: this is the 127th (re)(non)(un)definition of the ntohl macros
* in the entire wrpc-sw codebase. This is insane and as non-portable
* as can be. If arpa/inet.h or netinet/in.h is not given by the arch
......@@ -386,6 +386,12 @@ struct ertm14_mmc_link
static struct ertm14_mmc_link mmc14_link;
static struct ertm14_mmc_link mmc15_link;
/* Non-hw implementation of the diagnostic registers. The eRTM is a
special board in the sense that it has no externally accessibe memory map -
therefore it's pointless to keep dedicated hardware diagnostic registers. We
just keep a structure reflecting the diag register layout in the RAM below. */
static struct wrc_diags wrc_diags_nonhw;
static void mmc_show_version_info( const char *brdname, struct ertm14_mmc_state *st );
static void streamers_init(void);
......@@ -1195,14 +1201,14 @@ void get_fpga_info(uint8_t *bi)
info[i] = htonl(regs[i]);
}
static void get_wrc_diags(struct WRC_DIAGS_WB *diags)
static void get_wrc_diags(struct wrc_diags *diags)
{
uint32_t *word = (void *)diags;
int i;
int n = sizeof(*diags)/sizeof(uint32_t);
memset(diags, 0xa5, sizeof(*diags));
wrc_diags_dump(diags);
memcpy(diags, &wrc_diags_nonhw, sizeof(struct wrc_diags ));
for (i = 0; i < n; i++)
word[i] = htonl(word[i]);
}
......@@ -1289,7 +1295,7 @@ static void subscribe_nco(struct ertm14_nco_reset *nco)
static int ertm_process_psnmp(struct uart_packet *rx_pkt, struct uart_packet *tx_pkt)
{
struct ertm14_board_state *bs;
struct WRC_DIAGS_WB *diags;
struct wrc_diags *diags;
struct ertm14_nco_reset *nco;
struct wrc_sensor *sensors;
uint8_t opcode = rx_pkt->payload[0];
......@@ -1329,7 +1335,7 @@ static int ertm_process_psnmp(struct uart_packet *rx_pkt, struct uart_packet *tx
get_sim_board_config(bs);
break;
case ertm14_get_wrc_diags:
diags = (struct WRC_DIAGS_WB *)&tx_pkt->payload[0];
diags = (struct wrc_diags *)&tx_pkt->payload[0];
get_wrc_diags(diags);
break;
case ertm14_get_wrc_nco:
......@@ -2461,6 +2467,8 @@ int wrc_board_early_init()
bist_init( ertm_bist );
wdiags_set_base_address( &wrc_diags_nonhw );
wrc_register_sensors( ertm_sensors );
/* initialize SPI flash */
......
boards/ertm14/psnmp-proto.h
View file @ 1794bdc6
......@@ -81,7 +81,7 @@ static struct ertm14_protocol_op {
.offset1 = 1,
.length1 = 0,
.offset2 = 0,
.length2 = sizeof(struct WRC_DIAGS_WB),
.length2 = sizeof(struct wrc_diags),
},
{
.opcode = ertm14_get_wrc_nco,
......
boards/sis8300ku/board.h
View file @ 1794bdc6
......@@ -21,6 +21,7 @@
#define BASE_SYSCON 0x20400
#define BASE_UART 0x20500
#define BASE_ONEWIRE 0x20600
#define BASE_WDIAGS_PRIV 0x20900
#define BASE_GPIO 0x28080
......
configs/afczv2_defconfig 0 → 100644
View file @ 1794bdc6
#
# Automatically generated file; DO NOT EDIT.
# WR PTP Core software configuration
#
# CONFIG_TARGET_GENERIC_PHY_8BIT is not set
# CONFIG_TARGET_GENERIC_PHY_16BIT is not set
# CONFIG_TARGET_WR_SWITCH is not set
CONFIG_TARGET_AFCZ_V2=y
# CONFIG_TARGET_ERTM14 is not set
# CONFIG_TARGET_SIS8300KU is not set
# CONFIG_TARGET_PXIE_FMC is not set
# CONFIG_TARGET_WR2RF_VME is not set
CONFIG_WR_NODE=y
CONFIG_PPSI_FORCE_CONFIG=y
CONFIG_STACKSIZE=2048
CONFIG_PRINT_BUFSIZE=128
CONFIG_RAMSIZE=131072
CONFIG_TEMP_POLL_INTERVAL=15
CONFIG_TEMP_HIGH_THRESHOLD=70
CONFIG_TEMP_HIGH_RAPPEL=60
# CONFIG_PLL_VERBOSE is not set
# CONFIG_WRC_VERBOSE is not set
# CONFIG_VLAN is not set
CONFIG_VLAN_NR=0
CONFIG_VLAN_1_FOR_CLASS7=0
CONFIG_VLAN_2_FOR_CLASS7=0
CONFIG_VLAN_FOR_CLASS6=0
# CONFIG_HOST_PROCESS is not set
CONFIG_LM32=y
CONFIG_EMBEDDED_NODE=y
CONFIG_PPSI=y
CONFIG_W1=y
CONFIG_LATENCY_ETHTYPE=291
CONFIG_IPMI_CONSOLE=y
# CONFIG_P2P is not set
CONFIG_IP=y
# CONFIG_CMD_CONFIG is not set
# CONFIG_SYSLOG is not set
# CONFIG_ETHERBONE is not set
CONFIG_SNMP=y
CONFIG_SNMP_SET=y
CONFIG_SNMP_SDB=y
CONFIG_SNMP_AUX_DIAG=y
# CONFIG_BUILD_INIT is not set
CONFIG_INIT_COMMAND=""
CONFIG_HAS_BUILD_INIT=0
CONFIG_HAS_FLASH_INIT=1
CONFIG_FLASH_INIT=y
CONFIG_AUX_DIAG=y
CONFIG_SDB_STORAGE=y
CONFIG_GENSDBFS=y
# CONFIG_LEGACY_EEPROM is not set
CONFIG_WR_DIAG=y
# CONFIG_WR_NODE_SIM is not set
CONFIG_ABSCAL=y
# CONFIG_LLDP is not set
CONFIG_TRACE_MSGS=y
# CONFIG_TRACE_ALL_ENABLE is not set
CONFIG_TRACE_MAIN_ENABLE=y
CONFIG_TRACE_STORAGE_ENABLE=y
CONFIG_TRACE_DEVICES_ENABLE=y
CONFIG_TRACE_BOARD_ENABLE=y
# CONFIG_TRACE_MAC_ENABLE is not set
# CONFIG_TRACE_PHY_ENABLE is not set
CONFIG_TRACE_ALL=0
CONFIG_TRACE_MAIN=1
CONFIG_TRACE_STORAGE=1
CONFIG_TRACE_DEVICES=1
CONFIG_TRACE_BOARD=1
CONFIG_TRACE_MAC=0
CONFIG_TRACE_PHY=0
#
# wrpc-sw is tainted if you change the following options
#
CONFIG_DEVELOPER=y
CONFIG_CUSTOM_RAMSIZE=131072
CONFIG_CUSTOM_STACKSIZE=2048
CONFIG_CUSTOM_PRINT_BUFSIZE=128
# CONFIG_CMD_LL is not set
# CONFIG_DAC_LOG is not set
# CONFIG_CHECK_RESET is not set
# CONFIG_SPLL_FIFO_LOG is not set
CONFIG_PRINTF_IS_XINT=y
# CONFIG_PRINTF_IS_FULL is not set
# CONFIG_PRINTF_IS_MINI is not set
# CONFIG_PRINTF_IS_NONE is not set
CONFIG_ASSERT=y
# CONFIG_DETERMINISTIC_BINARY is not set
# CONFIG_NET_VERBOSE is not set
# CONFIG_SNMP_VERBOSE is not set
# CONFIG_FAKE_TEMPERATURES is not set
# CONFIG_LATENCY_PROBE is not set
CONFIG_DEFAULT_PRINT_TASK_TIME_THRESHOLD=0
CONFIG_VLAN_ARRAY_SIZE=1
CONFIG_PRINTF_XINT=y
# CONFIG_PRINTF_FULL is not set
# CONFIG_PRINTF_MINI is not set
# CONFIG_PRINTF_NONE is not set
configs/ertm14_defconfig 0 → 100644
View file @ 1794bdc6
#
# Automatically generated file; DO NOT EDIT.
# WR PTP Core software configuration
#
# CONFIG_TARGET_GENERIC_PHY_8BIT is not set
# CONFIG_TARGET_GENERIC_PHY_16BIT is not set
# CONFIG_TARGET_WR_SWITCH is not set
# CONFIG_TARGET_AFCZ_V2 is not set
CONFIG_TARGET_ERTM14=y
# CONFIG_TARGET_SIS8300KU is not set
# CONFIG_TARGET_PXIE_FMC is not set
# CONFIG_TARGET_WR2RF_VME is not set
CONFIG_WR_NODE=y
# CONFIG_PPSI_FORCE_CONFIG is not set
CONFIG_STACKSIZE=2048
CONFIG_PRINT_BUFSIZE=128
CONFIG_RAMSIZE=196608
CONFIG_TEMP_POLL_INTERVAL=15
CONFIG_TEMP_HIGH_THRESHOLD=70
CONFIG_TEMP_HIGH_RAPPEL=60
# CONFIG_PLL_VERBOSE is not set
# CONFIG_WRC_VERBOSE is not set
# CONFIG_VLAN is not set
CONFIG_VLAN_NR=0
CONFIG_VLAN_1_FOR_CLASS7=0
CONFIG_VLAN_2_FOR_CLASS7=0
CONFIG_VLAN_FOR_CLASS6=0
# CONFIG_HOST_PROCESS is not set
CONFIG_LM32=y
CONFIG_EMBEDDED_NODE=y
CONFIG_PPSI=y
CONFIG_W1=y
CONFIG_LATENCY_ETHTYPE=291
CONFIG_IPMI_CONSOLE=y
# CONFIG_P2P is not set
CONFIG_IP=y
# CONFIG_CMD_CONFIG is not set
# CONFIG_SYSLOG is not set
# CONFIG_ETHERBONE is not set
CONFIG_SNMP=y
CONFIG_SNMP_SET=y
CONFIG_SNMP_SDB=y
CONFIG_SNMP_AUX_DIAG=y
# CONFIG_BUILD_INIT is not set
CONFIG_INIT_COMMAND=""
CONFIG_HAS_BUILD_INIT=0
CONFIG_HAS_FLASH_INIT=1
CONFIG_FLASH_INIT=y
CONFIG_AUX_DIAG=y
CONFIG_SDB_STORAGE=y
CONFIG_GENSDBFS=y
# CONFIG_LEGACY_EEPROM is not set
CONFIG_WR_DIAG=y
# CONFIG_WR_NODE_SIM is not set
# CONFIG_ABSCAL is not set
# CONFIG_LLDP is not set
CONFIG_TRACE_MSGS=y
# CONFIG_TRACE_ALL_ENABLE is not set
CONFIG_TRACE_MAIN_ENABLE=y
CONFIG_TRACE_STORAGE_ENABLE=y
CONFIG_TRACE_DEVICES_ENABLE=y
CONFIG_TRACE_BOARD_ENABLE=y
CONFIG_TRACE_MAC_ENABLE=y
CONFIG_TRACE_PHY_ENABLE=y
CONFIG_TRACE_ALL=0
CONFIG_TRACE_MAIN=1
CONFIG_TRACE_STORAGE=1
CONFIG_TRACE_DEVICES=1
CONFIG_TRACE_BOARD=1
CONFIG_TRACE_MAC=1
CONFIG_TRACE_PHY=1
#
# wrpc-sw is tainted if you change the following options
#
CONFIG_DEVELOPER=y
CONFIG_CUSTOM_RAMSIZE=131072
CONFIG_CUSTOM_STACKSIZE=2048
CONFIG_CUSTOM_PRINT_BUFSIZE=128
# CONFIG_CMD_LL is not set
# CONFIG_DAC_LOG is not set
# CONFIG_CHECK_RESET is not set
# CONFIG_SPLL_FIFO_LOG is not set
# CONFIG_PRINTF_IS_XINT is not set
CONFIG_PRINTF_IS_FULL=y
# CONFIG_PRINTF_IS_MINI is not set
# CONFIG_PRINTF_IS_NONE is not set
# CONFIG_ASSERT is not set
# CONFIG_DETERMINISTIC_BINARY is not set
# CONFIG_NET_VERBOSE is not set
# CONFIG_SNMP_VERBOSE is not set
# CONFIG_FAKE_TEMPERATURES is not set
# CONFIG_LATENCY_PROBE is not set
CONFIG_DEFAULT_PRINT_TASK_TIME_THRESHOLD=0
CONFIG_VLAN_ARRAY_SIZE=1
# CONFIG_PRINTF_XINT is not set
CONFIG_PRINTF_FULL=y
# CONFIG_PRINTF_MINI is not set
# CONFIG_PRINTF_NONE is not set
configs/sis8300ku_defconfig
View file @ 1794bdc6
......@@ -8,8 +8,10 @@
# CONFIG_TARGET_AFCZ is not set
# CONFIG_TARGET_ERTM14 is not set
CONFIG_TARGET_SIS8300KU=y
# CONFIG_TARGET_PXIE_FMC is not set
# CONFIG_TARGET_WR2RF_VME is not set
CONFIG_WR_NODE=y
# CONFIG_PPSI_FORCE_CONFIG is not set
CONFIG_PPSI_FORCE_CONFIG=y
CONFIG_STACKSIZE=2048
CONFIG_PRINT_BUFSIZE=128
CONFIG_RAMSIZE=131072
......@@ -31,20 +33,27 @@ CONFIG_W1=y
CONFIG_LATENCY_ETHTYPE=291
CONFIG_IPMI_CONSOLE=y
# CONFIG_P2P is not set
# CONFIG_IP is not set
CONFIG_IP=y
# CONFIG_CMD_CONFIG is not set
CONFIG_BUILD_INIT=y
CONFIG_INIT_COMMAND="vlan off;ptp stop;sfp match;mode slave;ptp start"
CONFIG_HAS_BUILD_INIT=1
# CONFIG_SYSLOG is not set
# CONFIG_ETHERBONE is not set
CONFIG_SNMP=y
CONFIG_SNMP_SET=y
CONFIG_SNMP_SDB=y
CONFIG_SNMP_AUX_DIAG=y
# CONFIG_BUILD_INIT is not set
CONFIG_INIT_COMMAND=""
CONFIG_HAS_BUILD_INIT=0
CONFIG_HAS_FLASH_INIT=1
CONFIG_FLASH_INIT=y
CONFIG_AUX_DIAG=y
CONFIG_SDB_STORAGE=y
CONFIG_GENSDBFS=y
# CONFIG_LEGACY_EEPROM is not set
CONFIG_WR_DIAG=y
# CONFIG_WR_DIAG is not set
# CONFIG_WR_NODE_SIM is not set
CONFIG_ABSCAL=y
# CONFIG_LLDP is not set
CONFIG_TRACE_MSGS=y
# CONFIG_TRACE_ALL_ENABLE is not set
CONFIG_TRACE_MAIN_ENABLE=y
......@@ -52,14 +61,14 @@ CONFIG_TRACE_STORAGE_ENABLE=y
CONFIG_TRACE_DEVICES_ENABLE=y
CONFIG_TRACE_BOARD_ENABLE=y
# CONFIG_TRACE_MAC_ENABLE is not set
CONFIG_TRACE_PHY_ENABLE=y
# CONFIG_TRACE_PHY_ENABLE is not set
CONFIG_TRACE_ALL=0
CONFIG_TRACE_MAIN=1
CONFIG_TRACE_STORAGE=1
CONFIG_TRACE_DEVICES=1
CONFIG_TRACE_BOARD=1
CONFIG_TRACE_MAC=0
CONFIG_TRACE_PHY=1
CONFIG_TRACE_PHY=0
#
# wrpc-sw is tainted if you change the following options
......@@ -79,6 +88,7 @@ CONFIG_PRINTF_IS_XINT=y
CONFIG_ASSERT=y
# CONFIG_DETERMINISTIC_BINARY is not set
# CONFIG_NET_VERBOSE is not set
# CONFIG_SNMP_VERBOSE is not set
# CONFIG_FAKE_TEMPERATURES is not set
# CONFIG_LATENCY_PROBE is not set
CONFIG_DEFAULT_PRINT_TASK_TIME_THRESHOLD=0
......
dev/dev.mk
View file @ 1794bdc6
......@@ -30,7 +30,8 @@ obj-$(CONFIG_EMBEDDED_NODE) += \
dev/storage.o \
dev/fine_pulse_generator.o \
dev/netif.o \
dev/leds.o
dev/leds.o \
dev/wdiags.o
obj-$(CONFIG_WR_NODE) += \
dev/sensors.o \
......
dev/endpoint.c
View file @ 1794bdc6
......@@ -108,8 +108,10 @@ void ep_reset_phy(struct wr_endpoint_device* dev)
/* Reset the GTP Transceiver - it's important to do the GTP phase alignment every time
we start up the software, otherwise the calibration RX/TX deltas may not be correct */
ep_pcs_write(dev, MDIO_REG_MCR, MDIO_MCR_PDOWN); /* reset the PHY */
if (!IS_WR_NODE_SIM)
timer_delay_ms(200);
pp_printf("Running long PHY reset...\n");
timer_delay_ms(10000);
pp_printf("PHY reset complete\n");
ep_pcs_write(dev, MDIO_REG_MCR, MDIO_MCR_RESET); /* reset the PHY */
ep_pcs_write(dev, MDIO_REG_MCR, 0); /* reset the PHY */
......
dev/ltc695x.c
View file @ 1794bdc6
......@@ -99,6 +99,7 @@ int ltc6953_configure_output( struct ltc695x_device *dev, int output, int divide
case 8: div_mp = 7; div_md = 1; break;
case 16: div_mp = 15; div_md = 1; break;
case 10: div_mp = 9; div_md = 1; break;
case 50: div_mp = 25-1; div_md = 1; break;
case 100: div_mp = 25 - 1; div_md = 2; break;
default: return -EINVAL; // unsupported divider
}
......
dev/syscon.c
View file @ 1794bdc6
......@@ -190,80 +190,3 @@ void net_rst(void)
syscon->GPSR |= SYSC_GPSR_NET_RST;
}
int wdiag_set_valid(int enable)
{
if (enable)
syscon->WDIAG_CTRL |= SYSC_WDIAG_CTRL_DATA_VALID;
if (!enable)
syscon->WDIAG_CTRL &= ~SYSC_WDIAG_CTRL_DATA_VALID;
return (int)(syscon->WDIAG_CTRL & SYSC_WDIAG_CTRL_DATA_VALID);
}
int wdiag_get_valid(void)
{
if (syscon->WDIAG_CTRL & SYSC_WDIAG_CTRL_DATA_VALID)
return 1;
else
return 0;
}
int wdiag_get_snapshot(void)
{
if (syscon->WDIAG_CTRL & SYSC_WDIAG_CTRL_DATA_SNAPSHOT)
return 1;
else
return 0;
}
void wdiags_write_servo_state(int wr_mode, uint8_t servostate, uint64_t mu,
uint64_t dms, int32_t asym, int32_t cko,
int32_t setp, int32_t ucnt)
{
syscon->WDIAG_SSTAT = wr_mode ? SYSC_WDIAG_SSTAT_WR_MODE:0;
syscon->WDIAG_SSTAT |= SYSC_WDIAG_SSTAT_SERVOSTATE_W(servostate);
syscon->WDIAG_MU_MSB = 0xFFFFFFFF & (mu>>32);
syscon->WDIAG_MU_LSB = 0xFFFFFFFF & mu;
syscon->WDIAG_DMS_MSB = 0xFFFFFFFF & (dms>>32);
syscon->WDIAG_DMS_LSB = 0xFFFFFFFF & dms;
syscon->WDIAG_ASYM = asym;
syscon->WDIAG_CKO = cko;
syscon->WDIAG_SETP = setp;
syscon->WDIAG_UCNT = ucnt;
}
void wdiags_write_port_state(int link, int locked)
{
uint32_t val = 0;
val = link ? SYSC_WDIAG_PSTAT_LINK : 0;
val |= locked ? SYSC_WDIAG_PSTAT_LOCKED : 0;
syscon->WDIAG_PSTAT = val;
}
void wdiags_write_ptp_state(uint8_t ptpstate)
{
syscon->WDIAG_PTPSTAT = SYSC_WDIAG_PTPSTAT_PTPSTATE_W(ptpstate);
}
void wdiags_write_aux_state(uint32_t aux_states)
{
syscon->WDIAG_ASTAT = SYSC_WDIAG_ASTAT_AUX_W(aux_states);
}
void wdiags_write_cnts(uint32_t tx, uint32_t rx)
{
syscon->WDIAG_TXFCNT = tx;
syscon->WDIAG_RXFCNT = rx;
}
void wdiags_write_time(uint64_t sec, uint32_t nsec)
{
syscon->WDIAG_SEC_MSB = 0xFFFFFFFF & (sec>>32);
syscon->WDIAG_SEC_LSB = 0xFFFFFFFF & sec;
syscon->WDIAG_NS = nsec;
}
void wdiags_write_temp(uint32_t temp)
{
syscon->WDIAG_TEMP = temp;
}
dev/wdiags.c 0 → 100644
View file @ 1794bdc6
/*
* This work is part of the White Rabbit project
*
* Copyright (C) 2011-2021 CERN (www.cern.ch)
* Author: Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
*
* Released according to the GNU GPL, version 2 or any later version.
*/
#include "board.h"
#include "dev/wdiags.h"
#include <hw/wrc_diags_regs.h>
#include <errno.h>
#include <string.h>
#define WDIAGS_VERSION 2
#if defined(BASE_WDIAGS_PRIV)
static void *wdiags_base = BASE_WDIAGS_PRIV;
#else
static void *wdiags_base = NULL;
#endif
int wdiag_write( uint32_t reg, uint32_t value )
{
if( !wdiags_base )
return -1;
// fixme: there's a max of 64 diag registers.
writel( value, (void*) ( wdiags_base + reg ) );
return 0;
}
uint32_t wdiag_read( uint32_t reg )
{
if( !wdiags_base )
return 0xdeadbeef;
return readl( (void*) ( wdiags_base + reg ) );
}
int wdiag_set_valid(int enable)
{
uint32_t ctl = wdiag_read( WRC_DIAGS_CTRL );
if (enable)
{
wdiag_write( WRC_DIAGS_CTRL, ctl | WRC_DIAGS_CTRL_DATA_VALID );
}
else
{
wdiag_write( WRC_DIAGS_CTRL, ctl & ~WRC_DIAGS_CTRL_DATA_VALID );
}
return wdiag_read( WRC_DIAGS_CTRL );
}
int wdiag_get_valid(void)
{
uint32_t ctl = wdiag_read( WRC_DIAGS_CTRL );
return (ctl & WRC_DIAGS_CTRL_DATA_VALID ) ? 1 : 0;
}
int wdiag_get_snapshot(void)
{
uint32_t ctl = wdiag_read( WRC_DIAGS_CTRL );
return (ctl & WRC_DIAGS_CTRL_DATA_SNAPSHOT ) ? 1 : 0;
}
void wdiags_write_servo_state(int wr_mode, uint8_t servostate, uint64_t mu,
uint64_t dms, int32_t asym, int32_t cko,
int32_t setp, int32_t ucnt, uint32_t restart_cnt, uint64_t up_timestamp )
{
uint32_t sstat = wr_mode ? WRC_DIAGS_WDIAG_SSTAT_WR_MODE:0;
sstat |= servostate << WRC_DIAGS_WDIAG_SSTAT_SERVOSTATE_SHIFT;
wdiag_write( WRC_DIAGS_WDIAG_SSTAT, sstat );
wdiag_write( WRC_DIAGS_WDIAG_MU_MSB , 0xFFFFFFFF & (mu>>32) );
wdiag_write( WRC_DIAGS_WDIAG_MU_LSB , 0xFFFFFFFF & mu );
wdiag_write( WRC_DIAGS_WDIAG_DMS_MSB , 0xFFFFFFFF & (dms>>32) );
wdiag_write( WRC_DIAGS_WDIAG_DMS_LSB , 0xFFFFFFFF & dms );
wdiag_write( WRC_DIAGS_WDIAG_ASYM , asym );
wdiag_write( WRC_DIAGS_WDIAG_CKO , cko );
wdiag_write( WRC_DIAGS_WDIAG_SETP , setp );
wdiag_write( WRC_DIAGS_WDIAG_UCNT , ucnt );
}
void wdiags_write_port_state(int link, int locked)
{
uint32_t val = 0;
val = link ? WRC_DIAGS_WDIAG_PSTAT_LINK : 0;
val |= locked ? WRC_DIAGS_WDIAG_PSTAT_LOCKED : 0;
wdiag_write( WRC_DIAGS_WDIAG_PSTAT , val );
//pp_printf("wdiags_write_port_state: %x\n", val );
}
void wdiags_write_ptp_state(uint8_t ptpstate)
{
wdiag_write( WRC_DIAGS_WDIAG_PTPSTAT, ptpstate << WRC_DIAGS_WDIAG_PTPSTAT_PTPSTATE_SHIFT );
}
void wdiags_write_aux_state(uint32_t aux_states)
{
wdiag_write( WRC_DIAGS_WDIAG_ASTAT, aux_states << WRC_DIAGS_WDIAG_ASTAT_AUX_SHIFT );
}
void wdiags_write_cnts(uint32_t tx, uint32_t rx, uint32_t rx_errors)
{
wdiag_write( WRC_DIAGS_WDIAG_TXFCNT, tx);
wdiag_write( WRC_DIAGS_WDIAG_RXFCNT, rx);
wdiag_write( WRC_DIAGS_WDIAG_RX_ERR_CNT, rx_errors);
}
void wdiags_write_time(uint64_t sec, uint32_t nsec)
{
wdiag_write( WRC_DIAGS_WDIAG_SEC_MSB, 0xFFFFFFFF & (sec>>32) );
wdiag_write( WRC_DIAGS_WDIAG_SEC_LSB, 0xFFFFFFFF & sec );
wdiag_write( WRC_DIAGS_WDIAG_NS, nsec );
}
void wdiags_write_temp(uint32_t temp)
{
wdiag_write( WRC_DIAGS_WDIAG_TEMP, temp );
}
void wdiags_set_base_address( void *base )
{
wdiags_base = base;
}
int wdiags_init()
{
int i;
if( wdiags_base == NULL )
{
dev_dbg("wdiags: no base address specified.\n");
return -1;
}
else
{
dev_dbg("wdiags: base addr = 0x%x.\n", wdiags_base );
}
for( i = 0; i < 64; i++ )
wdiag_write( i * 4, 0 );
wdiag_write( WRC_DIAGS_VER, WDIAGS_VERSION );
return 0;
}
void wdiags_write_aux_clock_details( int clk_id, uint32_t mode, uint32_t phase, int enabled, int ready )
{
uint32_t reg;
switch(clk_id)
{
case 0: reg = WRC_DIAGS_WDIAG_AUX0_DETAIL_STAT; break;
case 1: reg = WRC_DIAGS_WDIAG_AUX1_DETAIL_STAT; break;
case 2: reg = WRC_DIAGS_WDIAG_AUX2_DETAIL_STAT; break;
case 3: reg = WRC_DIAGS_WDIAG_AUX3_DETAIL_STAT; break;
default: return;
}
uint32_t v = 0;
v |= mode << WRC_DIAGS_WDIAG_AUX0_DETAIL_STAT_MODE_SHIFT;
v |= (enabled ? WRC_DIAGS_WDIAG_AUX0_DETAIL_STAT_ENABLED : 0);
v |= (ready ? WRC_DIAGS_WDIAG_AUX0_DETAIL_STAT_LOCKED : 0);
v |= (phase << WRC_DIAGS_WDIAG_AUX0_DETAIL_STAT_PHASE_SHIFT) & WRC_DIAGS_WDIAG_AUX0_DETAIL_STAT_PHASE_MASK;
wdiag_write( reg, v );
}
void wdiags_write_bitslide(int bitslide)
{
wdiag_write( WRC_DIAGS_WDIAG_BITSLIDE, bitslide );
}
void wdiags_write_ptp_deltas( int dtxm, int drxm, int dtxs, int drxs )
{
wdiag_write( WRC_DIAGS_WDIAG_DELTA_RX_M, drxm );
wdiag_write( WRC_DIAGS_WDIAG_DELTA_RX_S, drxs );
wdiag_write( WRC_DIAGS_WDIAG_DELTA_TX_M, dtxm );
wdiag_write( WRC_DIAGS_WDIAG_DELTA_TX_S, dtxs );
}
void wdiags_write_pll_diags( int hy, int my )
{
wdiag_write( WRC_DIAGS_WDIAG_SPLL_HY, hy );
wdiag_write( WRC_DIAGS_WDIAG_SPLL_MY, my );
}
include/board.h
View file @ 1794bdc6
......@@ -21,7 +21,9 @@
# include "boards/generic/board.h"
#elif defined(CONFIG_TARGET_WR_SWITCH)
# include "boards/wr-switch/board.h"
#elif defined(CONFIG_TARGET_AFCZ)
#elif defined(CONFIG_TARGET_AFCZ_V1)
# include "boards/afcz/board.h"
#elif defined(CONFIG_TARGET_AFCZ_V2)
# include "boards/afcz/board.h"
#elif defined(CONFIG_TARGET_ERTM14)
# include "boards/ertm14/board.h"
......
include/dev/syscon.h
View file @ 1794bdc6
......@@ -57,25 +57,6 @@ struct SYSCON_WB {
uint32_t DIAG_NW;
uint32_t DIAG_CR;
uint32_t DIAG_DAT;
uint32_t WDIAG_CTRL;
uint32_t WDIAG_SSTAT;
uint32_t WDIAG_PSTAT;
uint32_t WDIAG_PTPSTAT;
uint32_t WDIAG_ASTAT;
uint32_t WDIAG_TXFCNT;
uint32_t WDIAG_RXFCNT;
uint32_t WDIAG_SEC_MSB;
uint32_t WDIAG_SEC_LSB;
uint32_t WDIAG_NS;
uint32_t WDIAG_MU_MSB;
uint32_t WDIAG_MU_LSB;
uint32_t WDIAG_DMS_MSB;
uint32_t WDIAG_DMS_LSB;
uint32_t WDIAG_ASYM;
uint32_t WDIAG_CKO;
uint32_t WDIAG_SETP;
uint32_t WDIAG_UCNT;
uint32_t WDIAG_TEMP;
};
/* GPIO pins */
......@@ -128,18 +109,5 @@ int diag_write_word(uint32_t adr, uint32_t val);
void net_rst(void);
int wdiag_set_valid(int enable);
int wdiag_get_valid(void);
int wdiag_get_snapshot(void);
void wdiags_write_servo_state(int wr_mode, uint8_t servostate, uint64_t mu,
uint64_t dms, int32_t asym, int32_t cko,
int32_t setp, int32_t ucnt);
void wdiags_write_port_state(int link, int locked);
void wdiags_write_ptp_state(uint8_t ptpstate);
void wdiags_write_aux_state(uint32_t aux_states);
void wdiags_write_cnts(uint32_t tx, uint32_t rx);
void wdiags_write_time(uint64_t sec, uint32_t nsec);
void wdiags_write_temp(uint32_t temp);
#endif /* CONFIG_WR_NODE */
#endif
include/dev/wdiags.h 0 → 100644
View file @ 1794bdc6
/*
* This work is part of the White Rabbit project
*
* Copyright (C) 2011-2021 CERN (www.cern.ch)
* Author: Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
*
* Released according to the GNU GPL, version 2 or any later version.
*/
#ifndef __WDIAGS_H
#define __WDIAGS_H
#include <stdint.h>
int wdiag_set_valid(int enable);
int wdiag_get_valid(void);
int wdiag_get_snapshot(void);
void wdiags_write_servo_state(int wr_mode, uint8_t servostate, uint64_t mu,
uint64_t dms, int32_t asym, int32_t cko,
int32_t setp, int32_t ucnt, uint32_t restart_cnt, uint64_t up_timestamp );
void wdiags_write_port_state(int link, int locked);
void wdiags_write_ptp_state(uint8_t ptpstate);
void wdiags_write_aux_state(uint32_t aux_states);
void wdiags_write_cnts(uint32_t tx, uint32_t rx, uint32_t rx_errors);
void wdiags_write_time(uint64_t sec, uint32_t nsec);
void wdiags_write_temp(uint32_t temp);
void wdiags_write_aux_clock_details( int clk_id, uint32_t mode, uint32_t phase, int enabled, int ready );
int wdiags_init(void);
void wdiags_write_bitslide(int bitslide);
void wdiags_write_ptp_deltas( int dtxm, int drxm, int dtxs, int drxs );
void wdiags_set_base_address( void *base );
void wdiags_write_bitslide(int bitslide);
void wdiags_write_ptp_deltas( int dtxm, int drxm, int dtxs, int drxs );
void wdiags_write_pll_diags( int hy, int my );
#endif
include/hw/build_cheby.sh 0 → 100755
View file @ 1794bdc6
cheby --gen-c wrc_diags_regs.h -i wrc_diags_regs.cheby
\ No newline at end of file
include/hw/wrc_diags_regs.cheby 0 → 100644
View file @ 1794bdc6
This diff is collapsed.
include/hw/wrc_diags_regs.h
View file @ 1794bdc6
This diff is collapsed.
include/hw/wrc_syscon_regs.h
View file @ 1794bdc6
......@@ -3,7 +3,7 @@
* File : wrc_syscon_regs.h
* Author : auto-generated by wbgen2 from wrc_syscon_wb.wb
* Created : Mon Nov 27 13:37:56 2017
* Created : Sat Jun 19 00:29:20 2021
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrc_syscon_wb.wb
......@@ -208,77 +208,6 @@
#define SYSC_DIAG_CR_RW WBGEN2_GEN_MASK(31, 1)
/* definitions for register: User Diag: data to read/write */
/* definitions for register: WRPC Diag: ctrl */
/* definitions for field: WR DIAG data valid in reg: WRPC Diag: ctrl */
#define SYSC_WDIAG_CTRL_DATA_VALID WBGEN2_GEN_MASK(0, 1)
/* definitions for field: WR DIAG data snapshot in reg: WRPC Diag: ctrl */
#define SYSC_WDIAG_CTRL_DATA_SNAPSHOT WBGEN2_GEN_MASK(8, 1)
/* definitions for register: WRPC Diag: servo status */
/* definitions for field: WR valid in reg: WRPC Diag: servo status */
#define SYSC_WDIAG_SSTAT_WR_MODE WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Servo State in reg: WRPC Diag: servo status */
#define SYSC_WDIAG_SSTAT_SERVOSTATE_MASK WBGEN2_GEN_MASK(8, 4)
#define SYSC_WDIAG_SSTAT_SERVOSTATE_SHIFT 8
#define SYSC_WDIAG_SSTAT_SERVOSTATE_W(value) WBGEN2_GEN_WRITE(value, 8, 4)
#define SYSC_WDIAG_SSTAT_SERVOSTATE_R(reg) WBGEN2_GEN_READ(reg, 8, 4)
/* definitions for register: WRPC Diag: Port status */
/* definitions for field: Link Status in reg: WRPC Diag: Port status */
#define SYSC_WDIAG_PSTAT_LINK WBGEN2_GEN_MASK(0, 1)
/* definitions for field: PLL Locked in reg: WRPC Diag: Port status */
#define SYSC_WDIAG_PSTAT_LOCKED WBGEN2_GEN_MASK(1, 1)
/* definitions for register: WRPC Diag: PTP state */
/* definitions for field: PTP State in reg: WRPC Diag: PTP state */
#define SYSC_WDIAG_PTPSTAT_PTPSTATE_MASK WBGEN2_GEN_MASK(0, 8)
#define SYSC_WDIAG_PTPSTAT_PTPSTATE_SHIFT 0
#define SYSC_WDIAG_PTPSTAT_PTPSTATE_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
#define SYSC_WDIAG_PTPSTAT_PTPSTATE_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
/* definitions for register: WRPC Diag: AUX state */
/* definitions for field: AUX channel in reg: WRPC Diag: AUX state */
#define SYSC_WDIAG_ASTAT_AUX_MASK WBGEN2_GEN_MASK(0, 8)
#define SYSC_WDIAG_ASTAT_AUX_SHIFT 0
#define SYSC_WDIAG_ASTAT_AUX_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
#define SYSC_WDIAG_ASTAT_AUX_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
/* definitions for register: WRPC Diag: Tx PTP Frame cnts */
/* definitions for register: WRPC Diag: Rx PTP Frame cnts */
/* definitions for register: WRPC Diag:local time [msb of s] */
/* definitions for register: WRPC Diag: local time [lsb of s] */
/* definitions for register: WRPC Diag: local time [ns] */
/* definitions for register: WRPC Diag: Round trip (mu) [msb of ps] */
/* definitions for register: WRPC Diag: Round trip (mu) [lsb of ps] */
/* definitions for register: WRPC Diag: Master-slave delay (dms) [msb of ps] */
/* definitions for register: WRPC Diag: Master-slave delay (dms) [lsb of ps] */
/* definitions for register: WRPC Diag: Total link asymmetry [ps] */
/* definitions for register: WRPC Diag: Clock offset (cko) [ps] */
/* definitions for register: WRPC Diag: Phase setpoint (setp) [ps] */
/* definitions for register: WRPC Diag: Update counter (ucnt) */
/* definitions for register: WRPC Diag: Board temperature [C degree] */
/* [0x0]: REG Syscon reset register */
#define SYSC_REG_RSTR 0x00000000
/* [0x4]: REG GPIO Set/Readback Register */
......@@ -303,42 +232,4 @@
#define SYSC_REG_DIAG_CR 0x00000028
/* [0x2c]: REG User Diag: data to read/write */
#define SYSC_REG_DIAG_DAT 0x0000002c
/* [0x30]: REG WRPC Diag: ctrl */
#define SYSC_REG_WDIAG_CTRL 0x00000030
/* [0x34]: REG WRPC Diag: servo status */
#define SYSC_REG_WDIAG_SSTAT 0x00000034
/* [0x38]: REG WRPC Diag: Port status */
#define SYSC_REG_WDIAG_PSTAT 0x00000038
/* [0x3c]: REG WRPC Diag: PTP state */
#define SYSC_REG_WDIAG_PTPSTAT 0x0000003c
/* [0x40]: REG WRPC Diag: AUX state */
#define SYSC_REG_WDIAG_ASTAT 0x00000040
/* [0x44]: REG WRPC Diag: Tx PTP Frame cnts */
#define SYSC_REG_WDIAG_TXFCNT 0x00000044
/* [0x48]: REG WRPC Diag: Rx PTP Frame cnts */
#define SYSC_REG_WDIAG_RXFCNT 0x00000048
/* [0x4c]: REG WRPC Diag:local time [msb of s] */
#define SYSC_REG_WDIAG_SEC_MSB 0x0000004c
/* [0x50]: REG WRPC Diag: local time [lsb of s] */
#define SYSC_REG_WDIAG_SEC_LSB 0x00000050
/* [0x54]: REG WRPC Diag: local time [ns] */
#define SYSC_REG_WDIAG_NS 0x00000054
/* [0x58]: REG WRPC Diag: Round trip (mu) [msb of ps] */
#define SYSC_REG_WDIAG_MU_MSB 0x00000058
/* [0x5c]: REG WRPC Diag: Round trip (mu) [lsb of ps] */
#define SYSC_REG_WDIAG_MU_LSB 0x0000005c
/* [0x60]: REG WRPC Diag: Master-slave delay (dms) [msb of ps] */
#define SYSC_REG_WDIAG_DMS_MSB 0x00000060
/* [0x64]: REG WRPC Diag: Master-slave delay (dms) [lsb of ps] */
#define SYSC_REG_WDIAG_DMS_LSB 0x00000064
/* [0x68]: REG WRPC Diag: Total link asymmetry [ps] */
#define SYSC_REG_WDIAG_ASYM 0x00000068
/* [0x6c]: REG WRPC Diag: Clock offset (cko) [ps] */
#define SYSC_REG_WDIAG_CKO 0x0000006c
/* [0x70]: REG WRPC Diag: Phase setpoint (setp) [ps] */
#define SYSC_REG_WDIAG_SETP 0x00000070
/* [0x74]: REG WRPC Diag: Update counter (ucnt) */
#define SYSC_REG_WDIAG_UCNT 0x00000074
/* [0x78]: REG WRPC Diag: Board temperature [C degree] */
#define SYSC_REG_WDIAG_TEMP 0x00000078
#endif
libertm/display.c
View file @ 1794bdc6
#define __STDC_FORMAT_MACROS
#include <inttypes.h>
#include <math.h>
#include <stdio.h>
......@@ -97,7 +100,17 @@ void display_wrc_diags(struct ertm_wr_status *diags)
printf(fmt, "Phase setpoint (setp) [ps]", diags->WDIAG_SETP);
printf(fmt, "Update counter (ucnt)", diags->WDIAG_UCNT);
printf(fmt, "Board temperature [C degree]", diags->WDIAG_TEMP);
printf(fmt, "PHY Bitslide [bits]", diags->WDIAG_BITSLIDE);
printf(fmt, "PHY RX errors", diags->WDIAG_RX_ERR_CNT);
printf(fmt, "Servo uptime [msb of seconds]", diags->WDIAG_SERVO_UPTIME_MSB);
printf(fmt, "Servo uptime [lsb of seconds]", diags->WDIAG_SERVO_UPTIME_LSB);
printf(fmt, "Servo restart count", diags->WDIAG_SERVO_RESTART_COUNT);
printf(fmt, "Link Delay Model delta_Rx_M [ps]", diags->WDIAG_DELTA_RX_M);
printf(fmt, "Link Delay Model delta_Rx_S [ps]", diags->WDIAG_DELTA_RX_S);
printf(fmt, "Link Delay Model delta_Tx_M [ps]", diags->WDIAG_DELTA_TX_M);
printf(fmt, "Link Delay Model delta_Tx_S [ps]", diags->WDIAG_DELTA_TX_S);
printf(fmt, "SoftPLL Helper DAC value [0-65535]", diags->WDIAG_SPLL_HY);
printf(fmt, "SoftPLL Main DAC value [0-65535]", diags->WDIAG_SPLL_MY);
}
/* pulled from wrpc_diags.c */
......@@ -230,6 +243,7 @@ static void print_board_temp(uint32_t val)
void display_wrc_diags_cooked(struct ertm_wr_status *diags)
{
char fmt[] = "%-20s\t0x%08x\n";
char human[] = "%-20s\t0x%08x (%7d)\n";
printf(fmt, "Version register", diags->VER);
printf(fmt, "Ctrl", diags->CTRL);
......@@ -246,7 +260,18 @@ void display_wrc_diags_cooked(struct ertm_wr_status *diags)
print_clock_offset(diags->WDIAG_CKO);
print_phase_setpoint(diags->WDIAG_SETP);
print_update_counter(diags->WDIAG_UCNT);
print_board_temp(diags->WDIAG_TEMP);
print_board_temp(diags->WDIAG_TEMP);
printf(fmt, "PHY Bitslide [bits]", diags->WDIAG_BITSLIDE);
printf(fmt, "PHY RX errors", diags->WDIAG_RX_ERR_CNT);
printf(fmt, "Servo uptime [msb of seconds]", diags->WDIAG_SERVO_UPTIME_MSB);
printf(fmt, "Servo uptime [lsb of seconds]", diags->WDIAG_SERVO_UPTIME_LSB);
printf(fmt, "Servo restart count", diags->WDIAG_SERVO_RESTART_COUNT);
printf(fmt, "Link Delay Model delta_Rx_M [ps]", diags->WDIAG_DELTA_RX_M);
printf(fmt, "Link Delay Model delta_Rx_S [ps]", diags->WDIAG_DELTA_RX_S);
printf(fmt, "Link Delay Model delta_Tx_M [ps]", diags->WDIAG_DELTA_TX_M);
printf(fmt, "Link Delay Model delta_Tx_S [ps]", diags->WDIAG_DELTA_TX_S);
printf(human, "SoftPLL Helper DAC value [0-65535]", diags->WDIAG_SPLL_HY, diags->WDIAG_SPLL_HY);
printf(human, "SoftPLL Main DAC value [0-65535]", diags->WDIAG_SPLL_MY, diags->WDIAG_SPLL_MY);
}
static const char *source_name(int sync_source)
......
libertm/libertm.c
View file @ 1794bdc6
......@@ -123,27 +123,42 @@ static struct ertm_voltages voltages_defaults = {
};
struct ertm_wr_status wr_status_default = {
/* FIXME: copied, not #include'd, from wrc_diags_regs.h */
/* eventually replace by struct WRC_DIAGS_WB */
.VER = 0xdeadbabe, /* [0x0]: REG Version register */
.CTRL = 0, /* [0x4]: REG Ctrl */
.WDIAG_SSTAT = 0, /* [0x8]: REG WRPC Diag: servo status */
.WDIAG_PSTAT = 1, /* [0xc]: REG WRPC Diag: Port status */
.WDIAG_PTPSTAT = 3, /* [0x10]: REG WRPC Diag: PTP state */
.WDIAG_ASTAT = 0xa5, /* [0x14]: REG WRPC Diag: AUX state */
.WDIAG_TXFCNT = 0xa5, /* [0x18]: REG WRPC Diag: Tx PTP Frame cnts */
.WDIAG_RXFCNT = 0xa5, /* [0x1c]: REG WRPC Diag: Rx PTP Frame cnts */
.WDIAG_SEC_MSB = 0xa5, /* [0x20]: REG WRPC Diag:local time [msb of s] */
.WDIAG_SEC_LSB = 0xa5, /* [0x24]: REG WRPC Diag: local time [lsb of s] */
.WDIAG_NS = 0xa5, /* [0x28]: REG WRPC Diag: local time [ns] */
.WDIAG_MU_MSB = 0xa5, /* [0x2c]: REG WRPC Diag: Round trip (mu) [msb of ps] */
.WDIAG_MU_LSB = 0xa5, /* [0x30]: REG WRPC Diag: Round trip (mu) [lsb of ps] */
.WDIAG_DMS_MSB = 0xa5, /* [0x34]: REG WRPC Diag: Master-slave delay (dms) [msb of ps] */
.WDIAG_DMS_LSB = 0xa5, /* [0x38]: REG WRPC Diag: Master-slave delay (dms) [lsb of ps] */
.WDIAG_ASYM = 0xa5, /* [0x3c]: REG WRPC Diag: Total link asymmetry [ps] */
.WDIAG_CKO = 0xa5, /* [0x40]: REG WRPC Diag: Clock offset (cko) [ps] */
.WDIAG_SETP = 0xa5, /* [0x44]: REG WRPC Diag: Phase setpoint (setp) [ps] */
.WDIAG_UCNT = 0xa5, /* [0x48]: REG WRPC Diag: Update counter (ucnt) */
.WDIAG_TEMP = 0xa5, /* [0x4c]: REG WRPC Diag: Board temperature [C degree] */
/* eventually replace by struct wrc_diags */
.VER = 0xdeadbabe, /* [0x0]: REG Version register */
.CTRL = 0, /* [0x4]: REG Ctrl */
.WDIAG_SSTAT = 0, /* [0x8]: REG WRPC Diag: servo status */
.WDIAG_PSTAT = 1, /* [0xc]: REG WRPC Diag: Port status */
.WDIAG_PTPSTAT = 3, /* [0x10]: REG WRPC Diag: PTP state */
.WDIAG_ASTAT = 0xa5, /* [0x14]: REG WRPC Diag: AUX state */
.WDIAG_TXFCNT = 0xa5, /* [0x18]: REG WRPC Diag: Tx PTP Frame cnts */
.WDIAG_RXFCNT = 0xa5, /* [0x1c]: REG WRPC Diag: Rx PTP Frame cnts */
.WDIAG_SEC_MSB = 0xa5, /* [0x20]: REG WRPC Diag:local time [msb of s] */
.WDIAG_SEC_LSB = 0xa5, /* [0x24]: REG WRPC Diag: local time [lsb of s] */
.WDIAG_NS = 0xa5, /* [0x28]: REG WRPC Diag: local time [ns] */
.WDIAG_MU_MSB = 0xa5, /* [0x2c]: REG WRPC Diag: Round trip (mu) [msb of ps] */
.WDIAG_MU_LSB = 0xa5, /* [0x30]: REG WRPC Diag: Round trip (mu) [lsb of ps] */
.WDIAG_DMS_MSB = 0xa5, /* [0x34]: REG WRPC Diag: Master-slave delay (dms) [msb of ps] */
.WDIAG_DMS_LSB = 0xa5, /* [0x38]: REG WRPC Diag: Master-slave delay (dms) [lsb of ps] */
.WDIAG_ASYM = 0xa5, /* [0x3c]: REG WRPC Diag: Total link asymmetry [ps] */
.WDIAG_CKO = 0xa5, /* [0x40]: REG WRPC Diag: Clock offset (cko) [ps] */
.WDIAG_SETP = 0xa5, /* [0x44]: REG WRPC Diag: Phase setpoint (setp) [ps] */
.WDIAG_UCNT = 0xa5, /* [0x48]: REG WRPC Diag: Update counter (ucnt) */
.WDIAG_TEMP = 0xa5, /* [0x4c]: REG WRPC Diag: Board temperature [C degree] */
.WDIAG_AUX0_DETAIL_STAT = 0xa5,
.WDIAG_AUX1_DETAIL_STAT = 0xa5,
.WDIAG_AUX2_DETAIL_STAT = 0xa5,
.WDIAG_AUX3_DETAIL_STAT = 0xa5,
.WDIAG_RX_ERR_CNT = 0xa5,
.WDIAG_SERVO_UPTIME_MSB = 0xa5,
.WDIAG_SERVO_UPTIME_LSB = 0xa5,
.WDIAG_SERVO_RESTART_COUNT = 0xa5,
.WDIAG_BITSLIDE = 0xa5,
.WDIAG_DELTA_RX_M = 0xa5,
.WDIAG_DELTA_RX_S = 0xa5,
.WDIAG_DELTA_TX_M = 0xa5,
.WDIAG_DELTA_TX_S = 0xa5,
.WDIAG_SPLL_HY = 0xa5,
.WDIAG_SPLL_MY = 0xa5,
};
/* WARNING: mostly unused */
......@@ -433,7 +448,7 @@ void board_state_to_host_order(struct ertm14_board_state *board, struct ertm14_b
}
}
static void diags_to_host(struct WRC_DIAGS_WB *diags, struct WRC_DIAGS_WB *host)
static void diags_to_host(struct wrc_diags *diags, struct wrc_diags *host)
{
int i;
int ndiags = sizeof(*diags) / sizeof(uint32_t);
......@@ -458,12 +473,12 @@ int ertm_get_board_config(struct ertm_status *st, struct ertm14_board_state *bs)
return 0;
}
int ertm_get_wr_diags(struct ertm_status *st, struct WRC_DIAGS_WB *wrc_diags)
int ertm_get_wr_diags(struct ertm_status *st, struct wrc_diags *wrc_diags)
{
int res;
struct uart_link *link = &st->link;
struct WRC_DIAGS_WB d, *diags = &d;
struct wrc_diags d, *diags = &d;
res = ertm_proto_cycle(link, ertm14_get_wrc_diags, NULL, diags);
if (res < 0)
......@@ -1158,7 +1173,7 @@ int ertm_rf_nco_reset_enable(struct ertm_status *handle, int enable)
int ertm_wr_diags(struct ertm_status *handle, struct ertm_wr_status *status)
{
struct WRC_DIAGS_WB *s = (struct WRC_DIAGS_WB *)status;
struct wrc_diags *s = (struct wrc_diags *)status;
return ertm_get_wr_diags(handle, s);
}
......
libertm/libertm.h
View file @ 1794bdc6
......@@ -219,29 +219,45 @@ struct ertm_nco_status {
};
};
struct ertm_wr_status {
struct ertm_wr_status
{
/* FIXME: copied, not #include'd, from wrc_diags_regs.h */
/* this is an alias of struct WRC_DIAGS_WB */
uint32_t VER; /* [0x0]: REG Version register */
uint32_t CTRL; /* [0x4]: REG Ctrl */
uint32_t WDIAG_SSTAT; /* [0x8]: REG WRPC Diag: servo status */
uint32_t WDIAG_PSTAT; /* [0xc]: REG WRPC Diag: Port status */
uint32_t WDIAG_PTPSTAT; /* [0x10]: REG WRPC Diag: PTP state */
uint32_t WDIAG_ASTAT; /* [0x14]: REG WRPC Diag: AUX state */
uint32_t WDIAG_TXFCNT; /* [0x18]: REG WRPC Diag: Tx PTP Frame cnts */
uint32_t WDIAG_RXFCNT; /* [0x1c]: REG WRPC Diag: Rx PTP Frame cnts */
uint32_t WDIAG_SEC_MSB; /* [0x20]: REG WRPC Diag:local time [msb of s] */
uint32_t WDIAG_SEC_LSB; /* [0x24]: REG WRPC Diag: local time [lsb of s] */
uint32_t WDIAG_NS; /* [0x28]: REG WRPC Diag: local time [ns] */
uint32_t WDIAG_MU_MSB; /* [0x2c]: REG WRPC Diag: Round trip (mu) [msb of ps] */
uint32_t WDIAG_MU_LSB; /* [0x30]: REG WRPC Diag: Round trip (mu) [lsb of ps] */
uint32_t WDIAG_DMS_MSB; /* [0x34]: REG WRPC Diag: Master-slave delay (dms) [msb of ps] */
uint32_t WDIAG_DMS_LSB; /* [0x38]: REG WRPC Diag: Master-slave delay (dms) [lsb of ps] */
uint32_t WDIAG_ASYM; /* [0x3c]: REG WRPC Diag: Total link asymmetry [ps] */
uint32_t WDIAG_CKO; /* [0x40]: REG WRPC Diag: Clock offset (cko) [ps] */
uint32_t WDIAG_SETP; /* [0x44]: REG WRPC Diag: Phase setpoint (setp) [ps] */
uint32_t WDIAG_UCNT; /* [0x48]: REG WRPC Diag: Update counter (ucnt) */
uint32_t WDIAG_TEMP; /* [0x4c]: REG WRPC Diag: Board temperature [C degree] */
uint32_t VER; /* [0x0]: REG Version register */
uint32_t CTRL; /* [0x4]: REG Ctrl */
uint32_t WDIAG_SSTAT; /* [0x8]: REG WRPC Diag: servo status */
uint32_t WDIAG_PSTAT; /* [0xc]: REG WRPC Diag: Port status */
uint32_t WDIAG_PTPSTAT; /* [0x10]: REG WRPC Diag: PTP state */
uint32_t WDIAG_ASTAT; /* [0x14]: REG WRPC Diag: AUX state */
uint32_t WDIAG_TXFCNT; /* [0x18]: REG WRPC Diag: Tx PTP Frame cnts */
uint32_t WDIAG_RXFCNT; /* [0x1c]: REG WRPC Diag: Rx PTP Frame cnts */
uint32_t WDIAG_SEC_MSB; /* [0x20]: REG WRPC Diag:local time [msb of s] */
uint32_t WDIAG_SEC_LSB; /* [0x24]: REG WRPC Diag: local time [lsb of s] */
uint32_t WDIAG_NS; /* [0x28]: REG WRPC Diag: local time [ns] */
uint32_t WDIAG_MU_MSB; /* [0x2c]: REG WRPC Diag: Round trip (mu) [msb of ps] */
uint32_t WDIAG_MU_LSB; /* [0x30]: REG WRPC Diag: Round trip (mu) [lsb of ps] */
uint32_t WDIAG_DMS_MSB; /* [0x34]: REG WRPC Diag: Master-slave delay (dms) [msb of ps] */
uint32_t WDIAG_DMS_LSB; /* [0x38]: REG WRPC Diag: Master-slave delay (dms) [lsb of ps] */
uint32_t WDIAG_ASYM; /* [0x3c]: REG WRPC Diag: Total link asymmetry [ps] */
uint32_t WDIAG_CKO; /* [0x40]: REG WRPC Diag: Clock offset (cko) [ps] */
uint32_t WDIAG_SETP; /* [0x44]: REG WRPC Diag: Phase setpoint (setp) [ps] */
uint32_t WDIAG_UCNT; /* [0x48]: REG WRPC Diag: Update counter (ucnt) */
uint32_t WDIAG_TEMP; /* [0x4c]: REG WRPC Diag: Board temperature [C degree] */
uint32_t WDIAG_AUX0_DETAIL_STAT; /* [0x50]: REG (ro) WRPC Diag: Aux0 detailed clock status */
uint32_t WDIAG_AUX1_DETAIL_STAT; /* [0x54]: REG (ro) WRPC Diag: Aux1 detailed clock status */
uint32_t WDIAG_AUX2_DETAIL_STAT; /* [0x58]: REG (ro) WRPC Diag: Aux2 detailed clock status */
uint32_t WDIAG_AUX3_DETAIL_STAT; /* [0x5c]: REG (ro) WRPC Diag: Aux3 detailed clock status */
uint32_t WDIAG_RX_ERR_CNT; /* [0x60]: REG (ro) WRPC Diag: RX Error count */
uint32_t WDIAG_SERVO_UPTIME_MSB; /* [0x64]: REG (ro) WRPC Diag: Servo Up Timestamp (MSB) */
uint32_t WDIAG_SERVO_UPTIME_LSB; /* [0x68]: REG (ro) WRPC Diag: Servo Up Timestamp (LSB) */
uint32_t WDIAG_SERVO_RESTART_COUNT; /* [0x6c]: REG (ro) WRPC Diag: Servo restart count */
uint32_t WDIAG_BITSLIDE; /* [0x70]: REG (ro) WRPC Diag: Transceiver bitslide */
uint32_t WDIAG_DELTA_RX_M; /* [0x74]: REG (ro) WRPC Diag: delta_Rx_M parameter from the link delay model */
uint32_t WDIAG_DELTA_RX_S; /* [0x78]: REG (ro) WRPC Diag: delta_Rx_S parameter from the link delay model */
uint32_t WDIAG_DELTA_TX_M; /* [0x7c]: REG (ro) WRPC Diag: delta_Tx_M parameter from the link delay model */
uint32_t WDIAG_DELTA_TX_S; /* [0x80]: REG (ro) WRPC Diag: delta_Tx_S parameter from the link delay model */
uint32_t WDIAG_SPLL_HY; /* [0x84]: REG (ro) WRPC Diag: SoftPLL Helper DAC value (HY) */
uint32_t WDIAG_SPLL_MY; /* [0x88]: REG (ro) WRPC Diag: SoftPLL Main DAC value (MY) */
};
/* as a general rule, all methods in libertm return an integer exit
......
libertm/private.h
View file @ 1794bdc6
......@@ -14,6 +14,8 @@
#include "board-state.h"
#include "common-uart-link.h"
#include "hw/wrc_diags_regs.h"
struct ertm_state {
struct ertm_board_info board_info;
struct ertm14_board_state board_state;
......@@ -24,7 +26,7 @@ struct ertm_state {
struct ertm_nco_reset nco_reset;
union {
struct ertm_wr_status wr_status;
struct WRC_DIAGS_WB diags_wb;
struct wrc_diags diags_wb;
};
int ptp_enabled;
......
liblinux/extest/extest.c
View file @ 1794bdc6
......@@ -84,7 +84,7 @@ static void sighandler(int sig)
* we use sys_siglist[] instead of strsignal() to stay compatible
* with old versions of glibc
*/
printf("\nEXIT: Signal %s received\n", sys_siglist[sig]);
printf("\nEXIT: Signal %d received\n", sig);
free(_cmdlist);
if (user_sig_hndl)
user_sig_hndl();
......
monitor/monitor_ppsi.c
View file @ 1794bdc6
......@@ -20,6 +20,7 @@
#include <dev/onewire.h>
#include <dev/endpoint.h>
#include <dev/netif.h>
#include <dev/wdiags.h>
#include "sensors.h"
#include "wrc_ptp.h"
#include "hal_exports.h"
......@@ -336,7 +337,7 @@ uint32_t wrc_stats_last;
int wrc_log_stats(void)
{
struct hal_port_state state;
int tx, rx;
int tx, rx, rx_errors;
struct spll_aux_clock_status aux_stat;
uint64_t sec;
uint32_t nsec;
......@@ -368,7 +369,7 @@ int wrc_log_stats(void)
shw_pps_gen_get_time(&sec, &nsec);
wrpc_get_port_state(&state, NULL);
minic_get_stats(&tx, &rx, NULL);
minic_get_stats(&tx, &rx, &rx_errors);
pp_printf("lnk:%d rx:%d tx:%d ", state.state, rx, tx);
pp_printf("lock:%d ", state.locked ? 1 : 0);
pp_printf("ptp:%s ", wrc_ptp_state());
......@@ -436,8 +437,6 @@ int wrc_ptp_get_servo_state( void )
{
struct wr_servo_state *ss =
&((struct wr_data *)ppi->ext_data)->servo_state;
int32_t asym = (int32_t)(ss->picos_mu-2LL * ss->delta_ms);
int wr_mode = (ss->flags & WR_FLAG_VALID) ? 1 : 0;
return ss->state;
}
......@@ -450,7 +449,7 @@ int wrc_wr_diags(void)
{
struct hal_port_state ps;
static uint32_t last_jiffies;
int tx, rx;
int tx, rx, rx_errors;
uint64_t sec;
uint32_t nsec;
int n_out;
......@@ -477,8 +476,8 @@ int wrc_wr_diags(void)
wdiag_set_valid(0);
/* frame statistics */
minic_get_stats(&tx, &rx, NULL);
wdiags_write_cnts(tx,rx);
minic_get_stats(&tx, &rx, &rx_errors);
wdiags_write_cnts(tx,rx,rx_errors);
/* local time */
shw_pps_gen_get_time(&sec, &nsec);
......@@ -527,30 +526,65 @@ int wrc_wr_diags(void)
3: WR_SYNC_PHASE,
4: WR_TRACK_PHASE,
5: WR_WAIT_OFFSET_STABLE */
wdiags_write_servo_state(wr_mode, servostate, ss->picos_mu,
ss->delta_ms, asym, ss->offset,
ss->cur_setpoint,ss->update_count);
ss->cur_setpoint,ss->update_count, 0, 0); // fixme: add wdiags v2
wdiags_write_ptp_deltas( ss->delta_tx_m, ss->delta_rx_m, ss->delta_tx_s, ss->delta_rx_s );
}
/* auxiliar channels (if any) */
spll_get_num_channels(NULL, &n_out);
if (n_out > 8) n_out = 8; /* hardware limit. */
for(i = 0; i < n_out; i++) {
aux_stat |= (( SPLL_AUX_SLAVE_LOCKED | SPLL_AUX_MONITOR_READY ) & spll_get_aux_status(i).flags) << i;
}
wdiags_write_aux_state(aux_stat);
for(i = 0; i < n_out - 1; i++)
{
int mode;
int enabled;
int ready;
struct spll_aux_clock_status st = spll_get_aux_status( i );
if( st.mode == SPLL_AUX_MODE_SLAVE )
{
mode = 0;
enabled = st.flags & SPLL_AUX_SLAVE_ENABLED ? 1 : 0;
ready = st.flags & SPLL_AUX_SLAVE_LOCKED ? 1 : 0 ;
}
else
{
mode = 1;
enabled = st.flags & SPLL_AUX_MONITOR_ENABLED ? 1 : 0;
ready = st.flags & SPLL_AUX_MONITOR_READY ? 1 : 0 ;
}
wdiags_write_aux_clock_details( i, mode, st.phase, enabled, ready );
}
wdiags_write_bitslide( ep_get_bitslide(&wrc_endpoint_dev) );
/* temperature */
temp = wrc_temp_get("pcb");
wdiags_write_temp(temp);
wdiags_write_pll_diags( spll_get_dac(-1), spll_get_dac(0) ); // fixme: #defines for DAC IDs
/* **************** unlock data from reading by user ************** */
wdiag_set_valid(1);
return 1;
}
#if 0
/*
* this function can be used to factor out most of the stuff
* in wrc_wr_diags
......@@ -562,7 +596,7 @@ int wrc_wr_diags(void)
* do not write directly to syscon, but to an arbitrary address.
* That will clean the code here *enormously*
*/
int wrc_diags_dump(struct WRC_DIAGS_WB *buf)
int wrc_diags_dump(struct wrc_diags *buf)
{
struct hal_port_state ps;
int tx, rx;
......@@ -571,7 +605,7 @@ int wrc_diags_dump(struct WRC_DIAGS_WB *buf)
uint32_t aux_stat;
int i, temp, n_out;
buf->VER = 0x12345678;
buf->VER = 2;
buf->CTRL = 0xcafebabe;
/* frame statistics */
minic_get_stats(&tx, &rx, NULL);
......@@ -586,8 +620,8 @@ int wrc_diags_dump(struct WRC_DIAGS_WB *buf)
/* port state (from hal) */
wrpc_get_port_state(&ps, NULL);
buf->WDIAG_PSTAT = (ps.state ? SYSC_WDIAG_PSTAT_LINK : 0);
buf->WDIAG_PSTAT |= (ps.locked ? SYSC_WDIAG_PSTAT_LOCKED : 0);
buf->WDIAG_PSTAT = (ps.state ? WRC_DIAGS_WDIAG_PSTAT_LINK : 0);
buf->WDIAG_PSTAT |= (ps.locked ? WRC_DIAGS_WDIAG_PSTAT_LOCKED : 0);
/* port PTP State (from ppsi) */
buf->WDIAG_PTPSTAT = SYSC_WDIAG_PTPSTAT_PTPSTATE_W((uint8_t)ppi->state);
......@@ -602,7 +636,7 @@ int wrc_diags_dump(struct WRC_DIAGS_WB *buf)
uint64_t mu = ss->picos_mu;
uint64_t dms = ss->delta_ms;
buf->WDIAG_SSTAT = wr_mode ? SYSC_WDIAG_SSTAT_WR_MODE : 0;
buf->WDIAG_SSTAT = wr_mode ? WRC_DIAGS_WDIAG_SSTAT_WR_MODE : 0;
buf->WDIAG_SSTAT |= SYSC_WDIAG_SSTAT_SERVOSTATE_W(servostate);
buf->WDIAG_MU_MSB = 0xFFFFFFFF & (mu>>32);
buf->WDIAG_MU_LSB = 0xFFFFFFFF & mu;
......@@ -620,11 +654,15 @@ int wrc_diags_dump(struct WRC_DIAGS_WB *buf)
for(i = 0; i < n_out; i++) {
aux_stat |= (( SPLL_AUX_SLAVE_LOCKED | SPLL_AUX_MONITOR_READY ) & spll_get_aux_status(i).flags) << i;
}
buf->WDIAG_ASTAT = SYSC_WDIAG_ASTAT_AUX_W(aux_stat);
buf->WDIAG_ASTAT = WRC_DIAGS_WDIAG_ASTAT_AUX_W(aux_stat);
/* temperature */
temp = wrc_temp_get("pcb");
buf->WDIAG_TEMP = temp;
buf->WDIAG_BITSLIDE =
return 1;
}
#endif
softpll/softpll_ng.c
View file @ 1794bdc6
......@@ -297,6 +297,14 @@ void spll_very_init()
memset( (void *) &softpll, 0, sizeof(struct softpll_state ));
softpll.mode = SPLL_MODE_DISABLED;
uint32_t csr = SPLL->CSR;
spll_n_chan_ref = SPLL_CSR_N_REF_R(csr);
spll_n_chan_out = SPLL_CSR_N_OUT_R(csr);
if( spll_n_chan_out > 3 ) // fixme: bug in HDL?
spll_n_chan_out = 3;
}
void spll_init(int mode, int slave_ref_channel, int flags)
......@@ -672,10 +680,18 @@ static int spll_update_aux_clocks(void)
struct spll_aux_clock_status spll_get_aux_status(int channel )
{
struct spll_aux_clock_status rval;
rval.flags = 0;
rval.mode = 0;
rval.phase = 0;
if( channel < 0 || channel >= MAX_CHAN_AUX )
return rval;
int state = softpll.aux[channel].seq_state;
rval.mode = softpll.aux[channel].mode;
switch ( state )
{
case AUX_DISABLED:
......
softpll/softpll_ng.h
View file @ 1794bdc6
......@@ -56,6 +56,7 @@
struct spll_aux_clock_status
{
uint32_t flags;
int mode;
int phase;
};
......
tools/wrpc-diags.c
View file @ 1794bdc6
......@@ -13,14 +13,15 @@
#include <hw/wrc_diags_regs.h>
static struct mapping_desc *wrcdiag = NULL;
static int reg_version = -1;
static void unlock_diag(volatile struct WRC_DIAGS_WB *ptr)
static void unlock_diag(volatile struct wrc_diags *ptr)
{
//reset snapshot bit & keep valid bit as it is
ptr->CTRL &= iomemw32(wrcdiag->is_be, 0x1);
}
static int lock_diag(volatile struct WRC_DIAGS_WB *ptr)
static int lock_diag(volatile struct wrc_diags *ptr)
{
int loop = 10;
......@@ -64,7 +65,7 @@ static void print_port_status(uint32_t val)
};
int i, idx;
fprintf(stderr, "Port status:\t\t");
fprintf(stderr, "Port status:\t\t", val );
for (i = 0; i < nbits; ++i) {
idx = (val & (1 << i)) ? 1 : 0;
fprintf(stderr, "%s, ", pstat_str[i][idx]);
......@@ -120,6 +121,11 @@ static void print_rx_frame_count(uint32_t val)
fprintf(stderr, "RX frame count:\t\t%d\n", val);
}
static void print_rx_error_count(uint32_t val)
{
fprintf(stderr, "RX error count:\t\t%d\n", val);
}
static void print_local_time(uint32_t sec_msw, uint32_t sec_lsw, uint32_t ns)
{
uint64_t sec = (uint64_t)(sec_msw) << 32 | sec_lsw;
......@@ -166,6 +172,35 @@ static void print_board_temp(uint32_t val)
(int)((val & 0xffff) * 10 * 1000 >> 16));
}
static void print_aux_clock_status_single( int index, uint32_t r )
{
int mode = (r & WRC_DIAGS_WDIAG_AUX0_DETAIL_STAT_MODE_MASK) >> WRC_DIAGS_WDIAG_AUX0_DETAIL_STAT_MODE_SHIFT;
char *mode_str = (mode == 0 ? "slave" : "phase monitor");
int enabled = ( r & WRC_DIAGS_WDIAG_AUX0_DETAIL_STAT_ENABLED) ? 1 : 0;
int ready = ( r & WRC_DIAGS_WDIAG_AUX0_DETAIL_STAT_LOCKED) ? 1 : 0;
int phase = (r & WRC_DIAGS_WDIAG_AUX0_DETAIL_STAT_PHASE_MASK) >> WRC_DIAGS_WDIAG_AUX0_DETAIL_STAT_PHASE_SHIFT;
fprintf(stderr,"AUX%d: mode %s enabled %d locked %d phase %d ps\n", index, mode_str, enabled, ready, phase );
}
static void print_aux_clock_status( int is_be, volatile struct wrc_diags *d )
{
int i;
print_aux_clock_status_single( 0, iomemr32(is_be, d->WDIAG_AUX0_DETAIL_STAT) );
print_aux_clock_status_single( 1, iomemr32(is_be, d->WDIAG_AUX1_DETAIL_STAT) );
print_aux_clock_status_single( 2, iomemr32(is_be, d->WDIAG_AUX2_DETAIL_STAT) );
print_aux_clock_status_single( 3, iomemr32(is_be, d->WDIAG_AUX3_DETAIL_STAT) );
}
static void print_servo_info( int is_be, volatile struct wrc_diags *d )
{
}
enum wrcdiag_cmd_id{
WRCDIAG_CMD_DIAGS = CMD_USR,
WRCDIAG_CMD_SSTAT,
......@@ -187,8 +222,8 @@ enum wrcdiag_cmd_id{
static int read_diags(struct cmd_desc *cmdd, struct atom *atoms)
{
volatile struct WRC_DIAGS_WB *ptr =
(volatile struct WRC_DIAGS_WB *)wrcdiag->base;
volatile struct wrc_diags *ptr =
(volatile struct wrc_diags *)wrcdiag->base;
int res;
if (atoms == (struct atom *)VERBOSE_HELP) {
......@@ -204,12 +239,15 @@ static int read_diags(struct cmd_desc *cmdd, struct atom *atoms)
switch (cmdd->id) {
case WRCDIAG_CMD_DIAGS:
printf("Diag registers layout version: %d\n", reg_version );
print_servo_status(iomemr32(wrcdiag->is_be, ptr->WDIAG_SSTAT));
print_port_status(iomemr32(wrcdiag->is_be, ptr->WDIAG_PSTAT));
print_ptp_state(iomemr32(wrcdiag->is_be, ptr->WDIAG_PTPSTAT));
print_aux_state(iomemr32(wrcdiag->is_be, ptr->WDIAG_ASTAT));
print_tx_frame_count(iomemr32(wrcdiag->is_be, ptr->WDIAG_TXFCNT));
print_rx_frame_count(iomemr32(wrcdiag->is_be, ptr->WDIAG_RXFCNT));
if( reg_version >= 2 )
print_rx_error_count(iomemr32(wrcdiag->is_be, ptr->WDIAG_RX_ERR_CNT));
print_local_time(iomemr32(wrcdiag->is_be, ptr->WDIAG_SEC_MSB),
iomemr32(wrcdiag->is_be, ptr->WDIAG_SEC_LSB),
iomemr32(wrcdiag->is_be, ptr->WDIAG_NS));
......@@ -224,6 +262,13 @@ static int read_diags(struct cmd_desc *cmdd, struct atom *atoms)
print_phase_setpoint(iomemr32(wrcdiag->is_be, ptr->WDIAG_SETP));
print_update_counter(iomemr32(wrcdiag->is_be, ptr->WDIAG_UCNT));
print_board_temp(iomemr32(wrcdiag->is_be, ptr->WDIAG_TEMP));
if(reg_version >= 2)
{
print_aux_clock_status( wrcdiag->is_be, ptr );
print_servo_info( wrcdiag->is_be, ptr );
}
break;
case WRCDIAG_CMD_SSTAT:
print_servo_status(iomemr32(wrcdiag->is_be, ptr->WDIAG_SSTAT));
......@@ -299,8 +344,8 @@ static void wrcdiag_help(char *prog)
static void sig_hndl()
{
volatile struct WRC_DIAGS_WB *ptr =
(volatile struct WRC_DIAGS_WB *)wrcdiag->base;
volatile struct wrc_diags *ptr =
(volatile struct wrc_diags *)wrcdiag->base;
// Signal occured: free resource and exit
fprintf(stderr, "Handle signal: free resource and exit.\n");
......@@ -344,15 +389,18 @@ struct cmd_desc wrcdiag_cmd[WRCDIAG_CMD_NB + 1] = {
{0, },
};
static int verify_reg_version()
{
volatile struct WRC_DIAGS_WB *ptr =
(volatile struct WRC_DIAGS_WB *)wrcdiag->base;
volatile struct wrc_diags *ptr =
(volatile struct wrc_diags *)wrcdiag->base;
uint32_t ver = 0;
ver = iomemr32(wrcdiag->is_be, ptr->VER);
fprintf(stderr, "Wishbone register version: in FPGA = 0x%x |"
" in SW = 0x%x\n", ver, WBGEN2_WRC_DIAGS_VERSION);
if(ver != WBGEN2_WRC_DIAGS_VERSION)
fprintf(stderr, "Wishbone register version: in FPGA = 0x%x\n", ver);
reg_version = ver;
if(ver != 1 && ver != 2)
return -1;
else
return 0;
......@@ -369,7 +417,7 @@ int main(int argc, char *argv[])
return -1;
}
wrcdiag = dev_map(map_args, sizeof(struct WRC_DIAGS_WB));
wrcdiag = dev_map(map_args, sizeof(struct wrc_diags));
if (!wrcdiag) {
fprintf(stderr, "%s: wrcdiag mmap() failed: %s\n", argv[0],
strerror(errno));
......
wrc_main.c
View file @ 1794bdc6
......@@ -33,6 +33,7 @@
#include <dev/rxts_calibrator.h>
#include <dev/flash.h>
#include <dev/gpio.h>
#include <dev/wdiags.h>
#include <wrc_ptp.h>
#include <system_checks.h>
......@@ -82,6 +83,8 @@ static void wrc_initialize(void)
wrc_board_early_init();
wdiags_init();
pp_printf("WR Core: starting up...\n");
get_hw_name(wrc_hw_name);
......
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