test build for risc-v

10ce9590 · Tomasz Wlostowski · e5b353e7 · 10ce9590 · 10ce9590 · 10ce9590
Commit 10ce9590 authored Feb 02, 2021 by Tomasz Wlostowski
10 changed files
--- a/Makefile
+++ b/Makefile
 # Tomasz Wlostowski for CERN, 2011,2012
 -include $(CURDIR)/.config

-CROSS_COMPILE ?= lm32-elf-
+CROSS_COMPILE ?= /home/twl/gcc-riscv/bin/riscv32-elf-

 ifdef CONFIG_HOST_PROCESS
  CROSS_COMPILE =
@@ -28,7 +28,7 @@ PPSI = ppsi
 # list of file extensions to be copied for MAKEALL script
 MAKEALL_COPY_LIST=.bin .elf

-cflags-arch = -march=rv32im -mabi=ilp32 -msoft-float
+cflags-arch = -march=rv32imc -mabi=ilp32
 USER_CFLAGS = $(cflags-arch)
 #PPSI_O_LDFLAGS = -melf32lriscv 
 #-mabi=ilp32
@@ -36,12 +36,12 @@ USER_CFLAGS = $(cflags-arch)
 CFLAGS += $(cflags-arch)

 # we miss CONFIG_ARCH_LM32 as we have no other archs by now
-obj-$(CONFIG_LM32) = arch/lm32/crt0.o arch/lm32/irq.o
-LDS-$(CONFIG_WR_NODE)   = arch/lm32/ram.ld
-LDS-$(CONFIG_TARGET_WR_SWITCH) = arch/lm32/ram-wrs.ld
+obj-$(CONFIG_LM32) = 
+LDS-$(CONFIG_WR_NODE)   = arch/risc-v/ram.ld
+LDS-$(CONFIG_TARGET_WR_SWITCH) = arch/risc-v/ram-wrs.ld
 LDS-$(CONFIG_HOST_PROCESS) =

-obj-$(CONFIG_WR_NODE)   += wrc_main.o
+obj-$(CONFIG_WR_NODE)   += arch/risc-v/crt0.o arch/risc-v/irq.o wrc_main.o
 obj-$(CONFIG_WR_NODE_SIM) += wrc_main_sim.o
 obj-$(CONFIG_TARGET_WR_SWITCH) += ipc/minipc-mem-server.o ipc/rt_ipc.o

@@ -123,7 +123,7 @@ CFLAGS = $(cflags-y) -Wall -Wstrict-prototypes \
 ASFLAGS = -I.

 LDFLAGS = $(ldflags-y) \
-	-Wl,--gc-sections -Os -lgcc -lc
+	-march=rv32imc -mabi=ilp32 -Wl,--gc-sections -Os -lgcc -lc 

 WRC-O-FLAGS-$(CONFIG_LM32) = --gc-sections -e _start

@@ -238,6 +238,10 @@ distclean: clean
 %.o:		%.c
 	${CC} $(CFLAGS) $(PTPD_CFLAGS) $(INCLUDE_DIR) $(LIB_DIR) -c $*.c -o $@

+%.o:		%.S
+	${CC}   -march=rv32imc -mabi=ilp32 -c $*.S -o $@
+
+
 liblinux:
 	$(MAKE) -C liblinux CC=cc


--- a/arch/risc-v/crt0.S
+++ b/arch/risc-v/crt0.S
+
+  .section    .boot, "ax", @progbits
+
+.global _start
+_start:
+    j _entry
+
+.org 0x8
+
+.extern trap_entry
+_exception_entry:
+  j trap_entry
+
+
+
+_entry:
+
+  la      gp, _gp                 # Initialize global pointer
+  la      sp, _fstack
+
+  la t0, _fexception_stack
+  csrrw t0, mscratch, t0
+
+# clear the bss segment
+  la  t0, _fbss
+  la  t1, _end
+1:
+#ifdef __riscv64
+  sd  zero,0(t0)
+  addi  t0, t0, 8
+#else
+  sw  zero,0(t0)
+  addi  t0, t0, 4
+#endif
+  bltu  t0, t1, 1b
+
+  call    main
--- a/arch/risc-v/emulate.c
+++ b/arch/risc-v/emulate.c
+#include <stdint.h>
+
+struct rv_trap_context {
+    uint32_t r[32];
+    uint32_t mstatus;
+    uint32_t mepc;
+    uint32_t mbadaddr;
+    uint32_t mcause;
+};
+
+void undefined_insn_handler( struct rv_trap_context *ctx )
+{
+    uint32_t insn = *(volatile uint32_t *)( ctx->mepc );
+
+    ctx->r[0] = 0;
+
+    uint32_t rs1 = ctx->r[(insn >> 15) & 0x1f];
+    uint32_t rs2 = ctx->r[(insn >> 20) & 0x1f];
+    uint32_t rdi = (insn >> 7) & 0x1f;
+
+    // we support MUL natively
+    if ( (insn & 0xfe00707f) == 0x2001033 ) // MULH
+        ctx->r[rdi] = ( (int64_t)(int32_t)rs1 * (int64_t)(int32_t) rs2) >> 32;
+    else if ( (insn & 0xfe00707f) == 0x2002033 ) // MULHSU
+        ctx->r[rdi] = ((int64_t)(int32_t)rs1 * (uint64_t) rs2) >> 32;
+    else if ( (insn & 0xfe00707f) == 0x2003033 ) // MULHU
+        ctx->r[rdi] = ((uint64_t) rs1 * (uint64_t) rs2) >> 32;
+    else if ( (insn & 0xfe00707f) == 0x2004033 ) // DIV
+        ctx->r[rdi] = (int32_t)rs1 / (int32_t) rs2;
+    else if ( (insn & 0xfe00707f) == 0x2005033 ) // DIVU
+        ctx->r[rdi] = (uint32_t)rs1 / (uint32_t) rs2;
+    else if ( (insn & 0xfe00707f) == 0x2006033 ) // REM
+        ctx->r[rdi] = (int32_t)rs1 % (int32_t) rs2;
+    else if ( (insn & 0xfe00707f) == 0x2007033 ) // REMU
+        ctx->r[rdi] = (uint32_t)rs1 % (uint32_t) rs2;
+
+    ctx->mepc += 4;
+
+    asm volatile ("csrc mip, 0x4"); // clear exception
+}
\ No newline at end of file
--- a/arch/risc-v/encoding.h
+++ b/arch/risc-v/encoding.h
+// See LICENSE for license details.
+
+#ifndef RISCV_CSR_ENCODING_H
+#define RISCV_CSR_ENCODING_H
+
+#define CSR_ID_CYCLESH 0xc80
+#define CSR_ID_CYCLESL 0xc00
+#define CSR_ID_TIMEH 0xc81
+#define CSR_ID_TIMEL 0xc01
+#define CSR_ID_MSCRATCH 0x340
+#define CSR_ID_MEPC 0x341
+#define CSR_ID_MSTATUS 0x300
+#define CSR_ID_MCAUSE 0x342
+#define CSR_ID_MIP 0x344
+#define CSR_ID_MIE 0x304
+
+#ifdef __GNUC__
+
+#define rv_read_csr(reg) ({ unsigned long __tmp; \
+  asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \
+  __tmp; })
+
+#define rv_write_csr(reg, val) \
+  asm volatile ("csrw " #reg ", %0" :: "r"(val))
+
+#define rv_swap_csr(reg, val) ({ long __tmp; \
+  asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \
+  __tmp; })
+
+#define rv_set_csr(reg, bit) ({ unsigned long __tmp; \
+  if (__builtin_constant_p(bit) && (bit) < 32) \
+    asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
+  else \
+    asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
+  __tmp; })
+
+#define rv_clear_csr(reg, bit) ({ unsigned long __tmp; \
+  if (__builtin_constant_p(bit) && (bit) < 32) \
+    asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
+  else \
+    asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
+  __tmp; })
+
+#define rv_rdtime() rv_read_csr(time)
+#define rv_rdcycle() rv_read_csr(cycle)
+
+#endif
+
+#endif
--- a/arch/risc-v/irq.S
+++ b/arch/risc-v/irq.S
+/*
+  RISC-V / RV32 interrupt support code
+  Based on the RISC-V proxy kernel
+*/
+
+.section .text
+
+.global trap_entry
+trap_entry:
+ 	csrrw	sp,mscratch,sp
+ 	addi	sp,sp,-320
+ 	sw	ra,4(sp)
+ 	sw	gp,12(sp)
+ 	sw	tp,16(sp)
+ 	sw	t0,20(sp)
+ 	sw	t1,24(sp)
+ 	sw	t2,28(sp)
+ 	sw	s0,32(sp)
+ 	sw	s1,36(sp)
+ 	sw	a0,40(sp)
+ 	sw	a1,44(sp)
+ 	sw	a2,48(sp)
+ 	sw	a3,52(sp)
+ 	sw	a4,56(sp)
+ 	sw	a5,60(sp)
+ 	sw	a6,64(sp)
+ 	sw	a7,68(sp)
+ 	sw	s2,72(sp)
+ 	sw	s3,76(sp)
+ 	sw	s4,80(sp)
+ 	sw	s5,84(sp)
+ 	sw	s6,88(sp)
+ 	sw	s7,92(sp)
+ 	sw	s8,96(sp)
+ 	sw	s9,100(sp)
+ 	sw	s10,104(sp)
+ 	sw	s11,108(sp)
+ 	sw	t3,112(sp)
+ 	sw	t4,116(sp)
+ 	sw	t5,120(sp)
+ 	sw	t6,124(sp)
+ 	csrr	t0,mscratch
+ 	csrr	s0,mstatus
+ 	csrr	t1,mepc
+ 	csrr	t2,mbadaddr
+ 	csrr	t3,mcause
+ 	sw	t0,8(sp)
+ 	sw	s0,128(sp)
+ 	sw	t1,132(sp)
+ 	sw	t2,136(sp)
+ 	sw	t3,140(sp)
+ 	li	t0,-1
+ 	sw	t0,144(sp)
+ 	mv	a0,sp
+
+  la t0, jump_table
+  sll t3, t3, 2
+  add t0, t0, t3
+  lw t0, 0(t0)
+  la ra, jump_table_return
+  jr t0
+
+jump_table:
+  .word undefined_handler
+  .word undefined_handler
+  .word undefined_insn_handler
+  .word undefined_handler
+  .word undefined_handler
+  .word undefined_handler
+  .word undefined_handler
+  .word undefined_handler
+  .word undefined_handler
+  .word undefined_handler
+  .word undefined_handler
+  .word undefined_handler
+  .word undefined_handler
+  .word undefined_handler
+  .word undefined_handler
+  .word undefined_handler
+
+jump_table_return:
+
+  mv  a0,sp
+
+ 	lw	t1,128(a0)
+ 	lw	t2,132(a0)
+ 	addi	sp,sp,320
+ 	csrw	mscratch,sp
+ 	csrw	mepc,t2
+ 	lw	ra,4(a0)
+ 	lw	sp,8(a0)
+ 	lw	gp,12(a0)
+ 	lw	tp,16(a0)
+ 	lw	t0,20(a0)
+ 	lw	t1,24(a0)
+ 	lw	t2,28(a0)
+ 	lw	s0,32(a0)
+ 	lw	s1,36(a0)
+ 	lw	a1,44(a0)
+ 	lw	a2,48(a0)
+ 	lw	a3,52(a0)
+ 	lw	a4,56(a0)
+ 	lw	a5,60(a0)
+ 	lw	a6,64(a0)
+ 	lw	a7,68(a0)
+ 	lw	s2,72(a0)
+ 	lw	s3,76(a0)
+ 	lw	s4,80(a0)
+ 	lw	s5,84(a0)
+ 	lw	s6,88(a0)
+ 	lw	s7,92(a0)
+ 	lw	s8,96(a0)
+ 	lw	s9,100(a0)
+ 	lw	s10,104(a0)
+ 	lw	s11,108(a0)
+ 	lw	t3,112(a0)
+ 	lw	t4,116(a0)
+ 	lw	t5,120(a0)
+ 	lw	t6,124(a0)
+ 	lw	a0,40(a0)
+ 	sret
+
+.weak undefined_handler
+undefined_handler:
+	 j undefined_handler
+
+.weak undefined_insn_handler
+undefined_insn_handler:
+  j undefined_insn_handler
--- a/arch/risc-v/ram.ld
+++ b/arch/risc-v/ram.ld
+OUTPUT_FORMAT("elf32-littleriscv")
+ENTRY(_start)
+MEMORY
+{
+    ram :
+ ORIGIN = 0x00000000,
+ LENGTH = 196608 - 2048
+    stack :
+ ORIGIN = 196608 - 2048,
+ LENGTH = 2048
+}
+SECTIONS
+{
+  . = 0;
+  _ftext = .;
+  PROVIDE( eprol = . );
+  .text :
+  {
+    *(.boot)
+    *(.text)
+    *(.text.*)
+    *(.gnu.linkonce.t.*)
+  } > ram
+  .init :
+  {
+    KEEP( *(.init) )
+  } > ram
+  .fini :
+  {
+    KEEP( *(.fini) )
+  } > ram
+  .rodata :
+  {
+    *(.rdata)
+    *(.rodata)
+    *(.rodata.*)
+    *(.gnu.linkonce.r.*)
+  } > ram
+  PROVIDE( etext = . );
+  _etext = .;
+  . = ALIGN(16);
+   _fdata = .;
+  .data :
+  {
+    *(.data)
+    *(.data.*)
+    *(.gnu.linkonce.d.*)
+  } > ram
+  PROVIDE( edata = . );
+  _edata = .;
+  . = ALIGN(16);
+  _gp = . + 0x800;
+  .sdata :
+  {
+    *(.sdata)
+    *(.sdata.*)
+    *(.srodata.*)
+    *(.gnu.linkonce.s.*)
+  } > ram
+  . = ALIGN(8);
+  _fbss = .;
+  .sbss :
+  {
+    *(.sbss)
+    *(.sbss.*)
+    *(.gnu.linkonce.sb.*)
+  } > ram
+  . = .;
+  _bss_start = .;
+  .bss :
+  {
+    *(.bss)
+    *(.bss.*)
+    *(.gnu.linkonce.b.*)
+    *(COMMON)
+  } > ram2
+ PROVIDE(_endram = ORIGIN(stack));
+ PROVIDE(_fstack = ORIGIN(stack) + LENGTH(stack) - 0x400);
+  PROVIDE(_fexception_stack = ORIGIN(stack) + LENGTH(stack) - 0x4);
+  PROVIDE(_end = .);
+}
--- a/arch/risc-v/ram.ld.S
+++ b/arch/risc-v/ram.ld.S
+OUTPUT_FORMAT("elf32-littleriscv")
+ENTRY(_start)
+
+
+MEMORY
+{
+    ram :
+	ORIGIN = 0x00000000,
+	LENGTH = CONFIG_RAMSIZE - CONFIG_STACKSIZE
+    stack :
+	ORIGIN = CONFIG_RAMSIZE - CONFIG_STACKSIZE,
+	LENGTH = CONFIG_STACKSIZE
+}
+
+SECTIONS
+{
+
+  /*--------------------------------------------------------------------*/
+  /* Code and read-only segment                                         */
+  /*--------------------------------------------------------------------*/
+
+  /* Begining of code and text segment */
+  . = 0;
+  _ftext = .;
+  PROVIDE( eprol = . );
+
+  /* text: Program code section */
+  .text :
+  {
+    *(.boot)
+    *(.text)
+    *(.text.*)
+    *(.gnu.linkonce.t.*)
+  } > ram
+
+  /* init: Code to execute before main (called by crt0.S) */
+  .init :
+  {
+    KEEP( *(.init) )
+  } > ram
+
+  /* fini: Code to execute after main (called by crt0.S) */
+  .fini :
+  {
+    KEEP( *(.fini) )
+  } > ram
+
+  /* rodata: Read-only data */
+  .rodata :
+  {
+    *(.rdata)
+    *(.rodata)
+    *(.rodata.*)
+    *(.gnu.linkonce.r.*)
+  } > ram
+
+  /* End of code and read-only segment */
+  PROVIDE( etext = . );
+  _etext = .;
+
+  /*--------------------------------------------------------------------*/
+  /* Global constructor/destructor segement                             */
+  /*--------------------------------------------------------------------*/
+  /* The .ctors/.dtors sections are special sections which contain a
+     list of constructor/destructor function pointers. crtbegin.o
+     includes code in a .init section which goes through the .ctors list
+     and calls each constuctor. crtend.o includes code in a .fini
+     section which goes through the .dtors list and calls each
+     destructor. crtbegin.o includes a special null pointer in its own
+     .ctors/.dtors sections which acts as a start indicator for those
+     lists. crtend.o also includes a special null pointer in its own
+     .ctors/.dtors sections which acts as an end indictor. The linker
+     commands below are setup so that crtbegin.o's .ctors/.dtors
+     sections are always first and crtend.o's .ctors/.dtors sections are
+     always last. This is the only way the list of functions will have
+     the begin and end indicators in the right place. */
+
+  /* ctors : Array of global constructor function pointers */
+
+  /*--------------------------------------------------------------------*/
+  /* Initialized data segment                                           */
+  /*--------------------------------------------------------------------*/
+
+  /* Start of initialized data segment */
+  . = ALIGN(16);
+   _fdata = .;
+
+  /* data: Writable data */
+  .data :
+  {
+    *(.data)
+    *(.data.*)
+    *(.gnu.linkonce.d.*)
+  } > ram
+
+  /* End of initialized data segment */
+  PROVIDE( edata = . );
+  _edata = .;
+
+  /* Have _gp point to middle of sdata/sbss to maximize displacement range */
+  . = ALIGN(16);
+  _gp = . + 0x800;
+
+  /* Writable small data segment */
+  .sdata :
+  {
+    *(.sdata)
+    *(.sdata.*)
+    *(.srodata.*)
+    *(.gnu.linkonce.s.*)
+  } > ram
+
+  /*--------------------------------------------------------------------*/
+  /* Uninitialized data segment                                         */
+  /*--------------------------------------------------------------------*/
+
+  /* Start of uninitialized data segment */
+  . = ALIGN(8);
+  _fbss = .;
+
+  /* Writable uninitialized small data segment */
+  .sbss :
+  {
+    *(.sbss)
+    *(.sbss.*)
+    *(.gnu.linkonce.sb.*)
+  } > ram
+
+  /* bss: Uninitialized writeable data section */
+  . = .;
+  _bss_start = .;
+  .bss :
+  {
+    *(.bss)
+    *(.bss.*)
+    *(.gnu.linkonce.b.*)
+    *(COMMON)
+  } > ram2
+
+  /* End of RAM for checking stack overflows */
+	PROVIDE(_endram = ORIGIN(stack));
+
+	/* First location in stack is highest address in STACK */
+	PROVIDE(_fstack = ORIGIN(stack) + LENGTH(stack) - 0x400);
+  PROVIDE(_fexception_stack = ORIGIN(stack) + LENGTH(stack) - 0x4);
+  PROVIDE(_end = .);
+
+}
--- a/ppsi @ 317250f2
+++ b/ppsi @ 317250f2
-Subproject commit cb8c90b7447b36398dcd8d00e0a4ab6eaf334bdc
+Subproject commit 317250f276692ea33473cbabe62c30b52229982b
--- a/sdb-lib/Makefile
+++ b/sdb-lib/Makefile
@@ -19,7 +19,7 @@ OBJDUMP         = $(CROSS_COMPILE)objdump
 # calculate endianness at compile time
 ENDIAN := $(shell ./check-endian $(CC))

-CFLAGS = -Wall -ggdb -O2
+CFLAGS = -Wall -ggdb -O2  -march=rv32imc -mabi=ilp32
 CFLAGS += -I../include/linux -I../include # for <sdb.h>
 CFLAGS += -ffunction-sections -fdata-sections
 CFLAGS += -Wno-pointer-sign

--- a/wrc_main.c
+++ b/wrc_main.c
@@ -322,6 +322,13 @@ static void create_tasks(void)
 #endif
 }

+uint32_t uptime_sec;
+
+
+void enable_irq() {};
+void disable_irq() {};
+
+
 int main(void) __attribute__ ((weak));
 int main(void)
 {