wrpc-diags.c 10.4 KB
Newer Older
1 2 3 4 5 6 7 8
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <inttypes.h>
#include <unistd.h>
#include <getopt.h>
#include <errno.h>
#include <time.h>
9

10 11 12 13 14 15 16 17 18
#include <libdevmap.h>
#include <extest.h>

#include <hw/wrc_diags_regs.h>

static struct mapping_desc *wrcdiag = NULL;

static void unlock_diag(volatile struct WRC_DIAGS_WB *ptr)
{
19 20
	//reset snapshot bit & keep valid bit as it is
	ptr->CTRL &= iomemw32(wrcdiag->is_be, 0x1);
21 22 23 24
}

static int lock_diag(volatile struct WRC_DIAGS_WB *ptr)
{
25
	int loop = 10;
26 27

	//snapshot diag ( just raise snapshot bit)
28
	ptr->CTRL |= iomemw32(wrcdiag->is_be, WRC_DIAGS_CTRL_DATA_SNAPSHOT);
29 30
	//wait max 10ms that valid bit becomes true.
	do {
31 32
		if (ptr->CTRL & iomemw32(wrcdiag->is_be,
					 WRC_DIAGS_CTRL_DATA_VALID))
33 34 35 36
			return 0;
		usleep(1000);
		--loop;
	} while(loop);
37 38
	fprintf(stderr, "timeout(10ms) expired while waiting for the valid bit "
		"for snapshot\n");
39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107
	return 1;
}

static void print_servo_status(uint32_t val)
{
	static char *sstat_str[] = {
		"Not initialized",
		"Sync ns",
		"Sync TAI",
		"Sync phase",
		"Track phase",
		"Wait offset stable",
	};

	fprintf(stderr, "servo status:\t\t%s\n",
		sstat_str[val >> WRC_DIAGS_WDIAG_SSTAT_SERVOSTATE_SHIFT]);
}

static void print_port_status(uint32_t val)
{
	static int nbits = 2;
	static char *pstat_str[][2] = {
		//bit = 0     	 	bit = 1
		{"Link down", 		"Link up",},
		{"PLL not locked",	"PLL locked",},
	};
	int i, idx;

	fprintf(stderr, "Port status:\t\t");
	for (i = 0; i < nbits; ++i) {
		idx = (val & (1 << i)) ? 1 : 0;
		fprintf(stderr, "%s, ", pstat_str[i][idx]);
	}
	fprintf(stderr, "\n");
}

static void print_ptp_state(uint32_t val)
{
	static char *ptpstat_str[] = {
		"None",
		"PPS initializing",
		"PPS faulty",
		"disabled",
		"PPS listening",
		"PPS pre-master",
		"PPS master",
		"PPS passive",
		"PPS uncalibrated",
		"PPS slave",
	};

	fprintf(stderr, "PTP state:\t\t");
	if (val <= 9)
		fprintf(stderr, "%s", ptpstat_str[val]);
	else if (val >= 100 && val <= 116)
		fprintf(stderr, "WR STATES(see ppsi/ieee1588_types.h): %d", val);
	else
		fprintf(stderr, "Unknown");
	fprintf(stderr, "\n");
}

static void print_aux_state(uint32_t val)
{
	int nch = 8; //should be retrieved from a register
	int i;

	fprintf(stderr, "Aux state:\t\t");
	for (i = 0; i < nch; i++) {
		if (val & (1 << i))
108
			fprintf(stderr, "ch%d:enabled ", i);
109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200
	}
	fprintf(stderr, "\n");
}

static void print_tx_frame_count(uint32_t val)
{
	fprintf(stderr, "TX frame count:\t\t%d\n", val);
}

static void print_rx_frame_count(uint32_t val)
{
	fprintf(stderr, "RX frame count:\t\t%d\n", val);
}

static void print_local_time(uint32_t sec_msw, uint32_t sec_lsw, uint32_t ns)
{
	uint64_t sec = (uint64_t)(sec_msw) << 32 | sec_lsw;
//	fprintf(stderr, "TAI time:\t\t %" PRIu64 "sec %d nsec\n",
//		sec, ns);
	fprintf(stderr, "TAI time:\t\t%s", ctime((time_t *)&sec));
}

static void print_roundtrip_time(uint32_t msw, uint32_t lsw)
{
	uint64_t val = (uint64_t)(msw) << 32 | lsw;
	fprintf(stderr, "Round trip time:\t%" PRIu64 " ps\n", val);
}

static void print_master_slave_delay(uint32_t msw, uint32_t lsw)
{
	uint64_t val = (uint64_t)(msw) << 32 | lsw;
	fprintf(stderr, "Master slave delay:\t%" PRIu64 " ps\n", val);
}

static void print_link_asym(uint32_t val)
{
	fprintf(stderr, "Total Link asymmetry:\t%d ps\n", val);
}

static void print_clock_offset(uint32_t val)
{
	fprintf(stderr, "Clock offset:\t\t%d ps\n", val);
}

static void print_phase_setpoint(uint32_t val)
{
	fprintf(stderr, "Phase setpoint:\t\t%d ps\n", val);
}

static void print_update_counter(uint32_t val)
{
	fprintf(stderr, "Update counter:\t\t%d\n", val);
}

static void print_board_temp(uint32_t val)
{
	 fprintf(stderr, "temp:\t\t\t%d.%04d C\n", val >> 16,
	 	   (int)((val & 0xffff) * 10 * 1000 >> 16));
}

enum wrcdiag_cmd_id{
	WRCDIAG_CMD_DIAGS = CMD_USR,
	WRCDIAG_CMD_SSTAT,
	WRCDIAG_CMD_PTPSTAT,
	WRCDIAG_CMD_PSTAT,
	WRCDIAG_CMD_ASTAT,
	WRCDIAG_CMD_TXFCNT,
	WRCDIAG_CMD_RXFCNT,
	WRCDIAG_CMD_LTIME,
	WRCDIAG_CMD_RTTIME,
	WRCDIAG_CMD_MSTRSLAVEDELAY,
	WRCDIAG_CMD_LINKASYM,
	WRCDIAG_CMD_CKOFFSET,
	WRCDIAG_CMD_PHASESETPOINT,
	WRCDIAG_CMD_UPDATECNT,
	WRCDIAG_CMD_TEMP,
	WRCDIAG_CMD_LAST,
};

static int read_diags(struct cmd_desc *cmdd, struct atom *atoms)
{
	volatile struct WRC_DIAGS_WB *ptr =
		(volatile struct WRC_DIAGS_WB *)wrcdiag->base;
	int res;

	if (atoms == (struct atom *)VERBOSE_HELP) {
		printf("%s - %s\n", cmdd->name, cmdd->help);
		return 1;
	}

	res = lock_diag(ptr);
	if (res) {
201 202
		fprintf(stderr, "Cmd is not executed\n");
		return 1;
203 204 205 206
	}

	switch (cmdd->id) {
	case WRCDIAG_CMD_DIAGS:
207 208 209
		print_servo_status(iomemr32(wrcdiag->is_be, ptr->WDIAG_SSTAT));
		print_port_status(iomemr32(wrcdiag->is_be, ptr->WDIAG_PSTAT));
		print_ptp_state(iomemr32(wrcdiag->is_be, ptr->WDIAG_PTPSTAT));
210
		print_aux_state(iomemr32(wrcdiag->is_be, ptr->WDIAG_ASTAT));
211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226
		print_tx_frame_count(iomemr32(wrcdiag->is_be, ptr->WDIAG_TXFCNT));
		print_rx_frame_count(iomemr32(wrcdiag->is_be, ptr->WDIAG_RXFCNT));
		print_local_time(iomemr32(wrcdiag->is_be, ptr->WDIAG_SEC_MSB),
				 iomemr32(wrcdiag->is_be, ptr->WDIAG_SEC_LSB),
				 iomemr32(wrcdiag->is_be, ptr->WDIAG_NS));
		print_roundtrip_time(iomemr32(wrcdiag->is_be, ptr->WDIAG_MU_MSB),
				     iomemr32(wrcdiag->is_be, ptr->WDIAG_MU_LSB));
		print_master_slave_delay(iomemr32(wrcdiag->is_be,
						  ptr->WDIAG_DMS_MSB),
					 iomemr32(wrcdiag->is_be,
					 	  ptr->WDIAG_DMS_LSB));
		print_link_asym(iomemr32(wrcdiag->is_be, ptr->WDIAG_ASYM));
		print_clock_offset(iomemr32(wrcdiag->is_be, ptr->WDIAG_CKO));
		print_phase_setpoint(iomemr32(wrcdiag->is_be, ptr->WDIAG_SETP));
		print_update_counter(iomemr32(wrcdiag->is_be, ptr->WDIAG_UCNT));
		print_board_temp(iomemr32(wrcdiag->is_be, ptr->WDIAG_TEMP));
227 228
		break;
	case WRCDIAG_CMD_SSTAT:
229
		print_servo_status(iomemr32(wrcdiag->is_be, ptr->WDIAG_SSTAT));
230 231
		break;
	case WRCDIAG_CMD_PSTAT:
232
		print_port_status(iomemr32(wrcdiag->is_be, ptr->WDIAG_PSTAT));
233 234
		break;
	case WRCDIAG_CMD_PTPSTAT:
235
		print_ptp_state(iomemr32(wrcdiag->is_be, ptr->WDIAG_PTPSTAT));
236 237
		break;
	case WRCDIAG_CMD_ASTAT:
238
		print_aux_state(iomemr32(wrcdiag->is_be, ptr->WDIAG_ASTAT));
239 240
		break;
	case WRCDIAG_CMD_TXFCNT:
241 242
		print_tx_frame_count(iomemr32(wrcdiag->is_be,
					      ptr->WDIAG_TXFCNT));
243 244
		break;
	case WRCDIAG_CMD_RXFCNT:
245 246
		print_rx_frame_count(iomemr32(wrcdiag->is_be,
					      ptr->WDIAG_RXFCNT));
247 248
		break;
	case WRCDIAG_CMD_LTIME:
249 250 251
		print_local_time(iomemr32(wrcdiag->is_be, ptr->WDIAG_SEC_MSB),
				 iomemr32(wrcdiag->is_be, ptr->WDIAG_SEC_LSB),
				 iomemr32(wrcdiag->is_be, ptr->WDIAG_NS));
252 253
		break;
	case WRCDIAG_CMD_RTTIME:
254 255 256 257
		print_roundtrip_time(iomemr32(wrcdiag->is_be,
					      ptr->WDIAG_MU_MSB),
			             iomemr32(wrcdiag->is_be,
				     	      ptr->WDIAG_MU_LSB));
258 259
		break;
	case WRCDIAG_CMD_MSTRSLAVEDELAY:
260 261 262 263
		print_master_slave_delay(iomemr32(wrcdiag->is_be,
						  ptr->WDIAG_DMS_MSB),
			                 iomemr32(wrcdiag->is_be,
					   	  ptr->WDIAG_DMS_LSB));
264 265
		break;
	case WRCDIAG_CMD_LINKASYM:
266
		print_link_asym(iomemr32(wrcdiag->is_be, ptr->WDIAG_ASYM));
267 268
		break;
	case WRCDIAG_CMD_CKOFFSET:
269
		print_clock_offset(iomemr32(wrcdiag->is_be, ptr->WDIAG_CKO));
270 271
		break;
	case WRCDIAG_CMD_PHASESETPOINT:
272
		print_phase_setpoint(iomemr32(wrcdiag->is_be, ptr->WDIAG_SETP));
273 274
		break;
	case WRCDIAG_CMD_UPDATECNT:
275
		print_update_counter(iomemr32(wrcdiag->is_be, ptr->WDIAG_UCNT));
276 277
		break;
	case WRCDIAG_CMD_TEMP:
278
		print_board_temp(iomemr32(wrcdiag->is_be, ptr->WDIAG_TEMP));
279 280 281 282 283 284 285 286
		break;
	}

	unlock_diag(ptr);

	return 1;
}

287 288 289 290 291 292
void print_version(void)
{
	fprintf(stderr, "Built in wrpc-sw repo ver:%s, by %s on %s %s\n",
		__GIT_VER__, __GIT_USR__, __TIME__, __DATE__);
}

293 294 295 296
static void wrcdiag_help(char *prog)
{
	fprintf(stderr, "%s [options]\n", prog);
	fprintf(stderr, "%s\n", dev_mapping_help());
297
	print_version();
298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346
}

static void sig_hndl()
{
	volatile struct WRC_DIAGS_WB *ptr =
		(volatile struct WRC_DIAGS_WB *)wrcdiag->base;

	// Signal occured: free resource and exit
	fprintf(stderr, "Handle signal: free resource and exit.\n");
	unlock_diag(ptr); // clean snapshot
	dev_unmap(wrcdiag);
	exit(1);
}

#define WRCDIAG_CMD_NB WRCDIAG_CMD_LAST - CMD_USR
struct cmd_desc wrcdiag_cmd[WRCDIAG_CMD_NB + 1] = {
	{ 1, WRCDIAG_CMD_DIAGS, "diags", "show all wrc diags",
	  "", 0, read_diags},
	{ 1, WRCDIAG_CMD_SSTAT, "sstat",
	  "get servo status", "", 0, read_diags},
	{ 1, WRCDIAG_CMD_PTPSTAT, "ptpstat",
	  "get PTP state", "", 0, read_diags},
	{ 1, WRCDIAG_CMD_PSTAT, "pstat",
	  "get port status", "", 0, read_diags},
	{ 1, WRCDIAG_CMD_ASTAT, "astat",
	  "get auxiliare state", "", 1, read_diags},
	{ 1, WRCDIAG_CMD_TXFCNT, "txfcnt",
	  "get TX PTP frame count", "", 1, read_diags},
	{ 1, WRCDIAG_CMD_RXFCNT, "rxfcnt",
	  "get RX frame count", "", 1, read_diags},
	{ 1, WRCDIAG_CMD_LTIME, "ltime",
	  "Local Time expressed in sec since epoch", "", 1, read_diags},
	{ 1, WRCDIAG_CMD_RTTIME, "rttime",
	  "Round trip time in picoseconds", "", 1, read_diags},
	{ 1, WRCDIAG_CMD_MSTRSLAVEDELAY, "msdelay",
	  "Master slave link delay in picoseconds", "", 1, read_diags},
	{ 1, WRCDIAG_CMD_LINKASYM, "asym",
	  "Total link asymmetry in picoseonds", "", 1, read_diags},
	{ 1, WRCDIAG_CMD_CKOFFSET, "cko",
	  "Clock offset in picoseonds", "", 1, read_diags},
	{ 1, WRCDIAG_CMD_PHASESETPOINT, "setp",
	  "Current slave's clock phase shift value", "", 1, read_diags},
	{ 1, WRCDIAG_CMD_UPDATECNT, "ucnt",
	  "Update counter", "", 1, read_diags},
	{ 1, WRCDIAG_CMD_TEMP, "temp",
	  "get board temperature", "", 1, read_diags},
	{0, },
};

347 348 349 350 351 352 353 354 355 356 357 358 359 360
static int verify_reg_version()
{
	volatile struct WRC_DIAGS_WB *ptr =
		(volatile struct WRC_DIAGS_WB *)wrcdiag->base;
	uint32_t ver = 0;
	ver = iomemr32(wrcdiag->is_be, ptr->VER);
	fprintf(stderr, "Wishbone register version: in FPGA = 0x%x |"
		" in SW = 0x%x\n", ver, WBGEN2_WRC_DIAGS_VERSION);
	if(ver != WBGEN2_WRC_DIAGS_VERSION)
		return -1;
	else
		return 0;
}

361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379
int main(int argc, char *argv[])
{
	int ret;
	struct mapping_args *map_args;

	map_args = dev_parse_mapping_args(argc, argv);
	if (!map_args) {
		wrcdiag_help(argv[0]);
		return -1;
	}

	wrcdiag = dev_map(map_args, sizeof(struct WRC_DIAGS_WB));
	if (!wrcdiag) {
		fprintf(stderr, "%s: wrcdiag mmap() failed: %s\n", argv[0],
			strerror(errno));
		free(map_args);
		return -1;
	}

380 381 382 383 384 385 386
	ret = verify_reg_version();
	if (ret) {
		fprintf(stderr, "Register version in FPGA and SW does not match\n");
		dev_unmap(wrcdiag);
		return -1;
	}
	
387 388 389 390 391 392 393 394 395 396 397 398
	ret = extest_register_user_cmd(wrcdiag_cmd, WRCDIAG_CMD_NB);
	if (ret) {
		dev_unmap(wrcdiag);
		return -1;
	}

	/* execute command loop */
	ret = extest_run("wrcdiag", sig_hndl);

	dev_unmap(wrcdiag);
	return (ret) ? -1 : 0;
}