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White Rabbit Network Robustness
Commit e8d940f4 authored by bradomyn's avatar bradomyn
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fixed the indetation, between vim, ise and modelsim everything was messy

parent a80789ab
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hdl/linear_block_code/sim/linear_block_decoder_tb.vhd
View file @ e8d940f4
......@@ -7,19 +7,19 @@ use ieee.std_logic_unsigned.all;
-- The word, "word" is reserved for encoded data 24 bits
-- The word. "data" is reserved for non-encoded data 12 btis
entity linear_block_decoder_tb is
end linear_block_decoder_tb;
end linear_block_decoder_tb;
architecture behavioral of linear_block_decoder_tb is
signal clk : std_logic:= '0';
signal reset : std_logic:= '1';
signal data_in : std_logic_vector(23 downto 0);
signal decoded_out : std_logic_vector(11 downto 0):=(others =>'0');
signal errorDecoded_out: std_logic:= '0';
constant period : time := 8 ns;
component linear_block_decoder
port(
clk: in std_logic;
......@@ -33,13 +33,13 @@ architecture behavioral of linear_block_decoder_tb is
begin
decoder_tb : linear_block_decoder
port map(
port map(
clk => clk,
reset => reset,
data_in => data_in,
decoded_out => decoded_out,
errorDecoded_out => errorDecoded_out);
clk_proc : process
begin
clk <= '0';
......@@ -57,7 +57,7 @@ begin
-- error checks state machine till step 4, three bit error
data_in <= to_stdlogicvector(x"54524a");
wait for period*8;
------------------------------------------------------------------
------------------------------------------------------------------
reset <= '1';
data_in <= (others=>'0');
wait for period;
......@@ -65,7 +65,7 @@ begin
-- error checks state machine till fail, four bit error
data_in <= to_stdlogicvector(x"54d24a");
wait for period*8;
---------------------------------------------------------------
---------------------------------------------------------------
reset <= '1';
data_in <= (others=>'0');
wait for period;
......@@ -132,7 +132,7 @@ begin
end process;
end process;
......
hdl/linear_block_code/sim/linear_block_enc_performance.vhd
View file @ e8d940f4
......@@ -4,11 +4,11 @@ use ieee.std_logic_arith.all;
entity linear_block_performance is
end linear_block_performance;
end linear_block_performance;
architecture behaviour of linear_block_performance is
signal clk :std_logic := '0';
signal data :std_logic_vector (11 downto 0) := (others => '0');
signal word :std_logic_vector (23 downto 0) := (others => '0');
......@@ -28,83 +28,83 @@ architecture behaviour of linear_block_performance is
clk : in std_logic;
data_in: in std_logic_vector(11 downto 0);
encoded_out:out std_logic_vector(23 downto 0)
);
);
end component;
begin
encoder_1: linear_block_enc
port map(
clk => clk,
data_in => data_1,
encoded_out => word_1
);
port map(
clk => clk,
data_in => data_1,
encoded_out => word_1
);
encoder_2: linear_block_enc
port map(
clk => clk,
data_in => data_2,
encoded_out => word_2
);
port map(
clk => clk,
data_in => data_2,
encoded_out => word_2
);
encoder_3: linear_block_enc
port map(
clk => clk,
data_in => data_3,
encoded_out => word_3
);
port map(
clk => clk,
data_in => data_3,
encoded_out => word_3
);
encoder_4: linear_block_enc
port map(
clk => clk,
data_in => data_4,
encoded_out => word_4
);
port map(
clk => clk,
data_in => data_4,
encoded_out => word_4
);
encoder_5: linear_block_enc
port map(
clk => clk,
data_in => data_5,
encoded_out => word_5
);
clk_proc: process
begin
port map(
clk => clk,
data_in => data_5,
encoded_out => word_5
);
clk_proc: process
begin
clk <= '1';
wait for PERIOD/2;
clk <= '0';
wait for PERIOD/2;
end process;
end process;
data_proc: process(clk)
begin
data_proc: process(clk)
begin
if(count < lengthframe) then
data_1 <= to_stdlogicvector(x"111");
data_2 <= to_stdlogicvector(x"111");
data_3 <= to_stdlogicvector(x"111");
data_4 <= to_stdlogicvector(x"111");
data_5 <= to_stdlogicvector(x"111");
count := count + (numEncoder*sizeword);
data_1 <= to_stdlogicvector(x"111");
data_2 <= to_stdlogicvector(x"111");
data_3 <= to_stdlogicvector(x"111");
data_4 <= to_stdlogicvector(x"111");
data_5 <= to_stdlogicvector(x"111");
count := count + (numEncoder*sizeword);
else
data_1 <= zeros(11 downto 0);
data_2 <= zeros(11 downto 0);
data_3 <= zeros(11 downto 0);
data_4 <= zeros(11 downto 0);
data_5 <= zeros(11 downto 0);
data_1 <= zeros(11 downto 0);
data_2 <= zeros(11 downto 0);
data_3 <= zeros(11 downto 0);
data_4 <= zeros(11 downto 0);
data_5 <= zeros(11 downto 0);
end if;
end process;
frame_proc: process(clk)
variable count1:integer :=0;
begin
end process;
frame_proc: process(clk)
variable count1:integer :=0;
begin
if(count1 < 12000) then
frame(count*2-1 downto (count*2 - (numEncoder*sizeword))) <=
word_5 & word_4 & word_3 & word_2 & word_1;
count1 := count1+120;
else
frame(count*2-1 downto (count*2 - (numEncoder*sizeword))) <=
zeros & zeros & zeros & zeros & zeros;
frame(count*2-1 downto (count*2 - (numEncoder*sizeword))) <=
word_5 & word_4 & word_3 & word_2 & word_1;
count1 := count1+120;
else
frame(count*2-1 downto (count*2 - (numEncoder*sizeword))) <=
zeros & zeros & zeros & zeros & zeros;
end if;
end process;
end process;
end;
......
hdl/linear_block_code/sim/linear_block_enc_testb.vhd
View file @ e8d940f4
......@@ -4,11 +4,11 @@ use ieee.std_logic_arith.all;
entity linear_block_testb is
end linear_block_testb;
end linear_block_testb;
architecture behaviour of linear_block_testb is
signal clk :std_logic := '0';
signal data :std_logic_vector (11 downto 0) := (others => '0');
signal word :std_logic_vector (23 downto 0) := (others => '0');
......@@ -20,33 +20,33 @@ architecture behaviour of linear_block_testb is
clk : in std_logic;
data_in: in std_logic_vector(11 downto 0);
encoded_out:out std_logic_vector(23 downto 0)
);
);
end component;
begin
encoder: linear_block_enc
port map(
clk => clk,
data_in => data,
encoded_out => word
);
clk_proc: process
begin
port map(
clk => clk,
data_in => data,
encoded_out => word
);
clk_proc: process
begin
clk <= '1';
wait for PERIOD/2;
clk <= '0';
wait for PERIOD/2;
end process;
end process;
data_proc: process
begin
data_proc: process
begin
wait for 16 ns;
data <= to_stdlogicvector(x"111");
wait;
end process;
end process;
end;
......
hdl/linear_block_code/syn/linear_block_decoder.vhd
View file @ e8d940f4
......@@ -51,7 +51,7 @@ entity linear_block_decoder is
data_in: in word_vector;
decoded_out: out data_vector;
errorDecoded_out:out std_logic;
succeedDeco_out:out std_logic
succeedDeco_out:out std_logic
);
end linear_block_decoder;
......@@ -65,123 +65,123 @@ architecture behavioral of linear_block_decoder is
type fms is (idle,step1,step2,step2_bis,step3,step4,step4_bis,deco,fail);
signal deco_state: fms;
signal errorDecoded: std_logic;
signal succeedDeco : std_logic;
signal errorVal : errorValset;
signal syndCal : syndCalset;
signal syndxBCal : syndxBCalset;
signal succeedDeco : std_logic;
signal errorVal : errorValset;
signal syndCal : syndCalset;
signal syndxBCal : syndxBCalset;
begin
--============================================================================
--! Process deco_logic
--! @brief logic of the decoder, following the state machine defined in [1]
--============================================================================
--============================================================================
--! Process deco_logic
--! @brief logic of the decoder, following the state machine defined in [1]
--============================================================================
deco_logic: process(clk,reset)
variable syndCalTemp : syndCalset;
variable syndxBCalTemp : syndxBCalset;
variable errorValTemp : errorValset;
variable syndCalTemp : syndCalset;
variable syndxBCalTemp : syndxBCalset;
variable errorValTemp : errorValset;
begin
if(clk'event and clk='1') then
if (reset = '1') then
deco_state <= idle;
syndCal <= ((others=>'0'),0);
errorVal <= ((others=>'0'),0);
syndxBCal <= ((others=>'0'),0);
vector_fixed <= (others=>'0');
errorDecoded <= '0';
succeedDeco <= '0';
else
case deco_state is
when idle =>
if (data_in /= zeros24) then
deco_state <= step1;
else
deco_state <= idle;
end if;
when step1 =>
syndCalTemp := syndromeCal(data_in);
syndCal <= syndCalTemp;
if (syndCalTemp.hammingW<=3) then
deco_state <= deco;
vector_fixed <= (syndCalTemp.synd&zeros12) xor data_in;
else
vector_fixed <= zeros24;
deco_state <= step2;
end if;
when step2 =>
-- calc error vectors
errorValTemp := errorVectorCal(syndCal.synd);
errorVal <= errorValTemp;
deco_state <= step2_bis;
when step2_bis =>
if(errorVal.hammingW <= 2) then
vector_fixed <= errorVal.errorVector xor data_in;
deco_state <= deco;
else
vector_fixed <= zeros24;
deco_state <= step3;
end if;
when step3 =>
-- syndromexB and hammingW(syndromeB)
syndxBCalTemp := syndromexBCal(syndCal.synd);
syndxBCal <= syndxBCalTemp;
if (syndxBCalTemp.hammingW<=3) then
vector_fixed <= (zeros12&syndxBCalTemp.syndxB) xor
data_in;
deco_state <= deco;
else
vector_fixed <= zeros24;
deco_state <= step4;
end if;
when step4 =>
if(clk'event and clk='1') then
if (reset = '1') then
deco_state <= idle;
syndCal <= ((others=>'0'),0);
errorVal <= ((others=>'0'),0);
syndxBCal <= ((others=>'0'),0);
vector_fixed <= (others=>'0');
errorDecoded <= '0';
succeedDeco <= '0';
else
case deco_state is
when idle =>
if (data_in /= zeros24) then
deco_state <= step1;
else
deco_state <= idle;
end if;
when step1 =>
syndCalTemp := syndromeCal(data_in);
syndCal <= syndCalTemp;
if (syndCalTemp.hammingW<=3) then
deco_state <= deco;
vector_fixed <= (syndCalTemp.synd&zeros12) xor data_in;
else
vector_fixed <= zeros24;
deco_state <= step2;
end if;
when step2 =>
-- calc error vectors
errorValTemp := errorVectorCal(syndCal.synd);
errorVal <= errorValTemp;
deco_state <= step2_bis;
when step2_bis =>
if(errorVal.hammingW <= 2) then
vector_fixed <= errorVal.errorVector xor data_in;
deco_state <= deco;
else
vector_fixed <= zeros24;
deco_state <= step3;
end if;
when step3 =>
-- syndromexB and hammingW(syndromeB)
syndxBCalTemp := syndromexBCal(syndCal.synd);
syndxBCal <= syndxBCalTemp;
if (syndxBCalTemp.hammingW<=3) then
vector_fixed <= (zeros12&syndxBCalTemp.syndxB) xor
data_in;
deco_state <= deco;
else
vector_fixed <= zeros24;
deco_state <= step4;
end if;
when step4 =>
-- (Beta*B+rowi) and hammingW
errorValTemp := errorVectorxBCal(syndxBCal.syndxB);
errorVal <= errorValTemp;
deco_state <= step4_bis;
when step4_bis =>
if (errorVal.hammingW <= 2) then
deco_state <= deco;
vector_fixed <= errorVal.errorVector xor
data_in;
else
vector_fixed <= zeros24;
deco_state <= fail;
end if;
when deco =>
deco_state <= idle;
errorDecoded <= '0';
succeedDeco <= '1';
when fail =>
deco_state <= idle;
errorDecoded <= '1';
succeedDeco <= '0';
when others =>
syndCal <= ((others=>'0'),0);
syndxBCal <= ((others=>'0'),0);
vector_fixed <= zeros24;
-- errorVal <= ((others=>'0'),0);
syndCalTemp := ((others=>'0'),0);
end case;
end if;
end if;
end process;
-- output
decoded_out <= vector_fixed(23 downto 12);
succeedDeco_out <= succeedDeco;
errorValTemp := errorVectorxBCal(syndxBCal.syndxB);
errorVal <= errorValTemp;
deco_state <= step4_bis;
when step4_bis =>
if (errorVal.hammingW <= 2) then
deco_state <= deco;
vector_fixed <= errorVal.errorVector xor
data_in;
else
vector_fixed <= zeros24;
deco_state <= fail;
end if;
when deco =>
deco_state <= idle;
errorDecoded <= '0';
succeedDeco <= '1';
when fail =>
deco_state <= idle;
errorDecoded <= '1';
succeedDeco <= '0';
when others =>
syndCal <= ((others=>'0'),0);
syndxBCal <= ((others=>'0'),0);
vector_fixed <= zeros24;
-- errorVal <= ((others=>'0'),0);
syndCalTemp := ((others=>'0'),0);
end case;
end if;
end if;
end process;
-- output
decoded_out <= vector_fixed(23 downto 12);
succeedDeco_out <= succeedDeco;
errorDecoded_out <= errorDecoded;
end behavioral;
hdl/linear_block_code/syn/linear_block_encoder.vhd
View file @ e8d940f4
......@@ -33,58 +33,58 @@ use work.linear_block_package.all;
entity linear_block_enc is
port ( clk : in std_logic;
port ( clk : in std_logic;
data_in : in data_vector;
encoded_out : out word_vecor
);
encoded_out : out word_vecor
);
end linear_block_enc;
architecture Behavioral of linear_block_enc is
signal check_bits : data_vector:=(others =>'0');
-- b matrix
-- 555 1 0 1 0 1 0 1 0 1 0 1 0
---------------------------------------------------
-- 11 0 1 2 3 4 5 6 7 8 9 10
-- 10 1 5 6 7 9 10 11
-- 9 0 2 6 7 8 10 11
-- 8 0 1 3 7 8 9 11
-- 7 1 2 4 8 9 10 11
-- 6 0 2 3 5 9 10 11
-- 5 0 1 3 4 6 10 11
-- 4 0 1 2 4 5 7 11
-- 3 1 2 3 5 6 8 11
-- 2 2 3 4 6 7 9 11
-- 1 3 4 5 7 8 10 11
-- 0 0 4 5 6 8 9 11
begin
process(data_in,clk)
begin
if(clk'event and clk='1') then -- parity bits c * b
check_bits(11) <= data_in(0) xor data_in(1) xor data_in(2) xor data_in(3) xor data_in(4) xor data_in(5) xor data_in(6)
xor data_in(7) xor data_in(8) xor data_in(9) xor data_in(10);
check_bits(10) <= data_in(1) xor data_in(5) xor data_in(6) xor data_in(7) xor data_in(9) xor data_in(10) xor data_in(11);
check_bits(9) <= data_in(0) xor data_in(2) xor data_in(6) xor data_in(7) xor data_in(8) xor data_in(10) xor data_in(11);
check_bits(8) <= data_in(0) xor data_in(1) xor data_in(3) xor data_in(7) xor data_in(8) xor data_in(9) xor data_in(11);
check_bits(7) <= data_in(1) xor data_in(2) xor data_in(4) xor data_in(8) xor data_in(9) xor data_in(10) xor data_in(11);
check_bits(6) <= data_in(0) xor data_in(2) xor data_in(3) xor data_in(5) xor data_in(9) xor data_in(10) xor data_in(11);
check_bits(5) <= data_in(0) xor data_in(1) xor data_in(3) xor data_in(4) xor data_in(6) xor data_in(10) xor data_in(11);
check_bits(4) <= data_in(0) xor data_in(1) xor data_in(2) xor data_in(4) xor data_in(5) xor data_in(7) xor data_in(11);
check_bits(3) <= data_in(1) xor data_in(2) xor data_in(3) xor data_in(5) xor data_in(6) xor data_in(8) xor data_in(11);
check_bits(2) <= data_in(2) xor data_in(3) xor data_in(4) xor data_in(6) xor data_in(7) xor data_in(9) xor data_in(11);
check_bits(1) <= data_in(3) xor data_in(4) xor data_in(5) xor data_in(7) xor data_in(8) xor data_in(10) xor data_in(11);
check_bits(0) <= data_in(0) xor data_in(4) xor data_in(5) xor data_in(6) xor data_in(8) xor data_in(9) xor data_in(11);
end if;
end process;
signal check_bits : data_vector:=(others =>'0');
-- b matrix
-- 555 1 0 1 0 1 0 1 0 1 0 1 0
---------------------------------------------------
-- 11 0 1 2 3 4 5 6 7 8 9 10
-- 10 1 5 6 7 9 10 11
-- 9 0 2 6 7 8 10 11
-- 8 0 1 3 7 8 9 11
-- 7 1 2 4 8 9 10 11
-- 6 0 2 3 5 9 10 11
-- 5 0 1 3 4 6 10 11
-- 4 0 1 2 4 5 7 11
-- 3 1 2 3 5 6 8 11
-- 2 2 3 4 6 7 9 11
-- 1 3 4 5 7 8 10 11
-- 0 0 4 5 6 8 9 11
begin
process(data_in,clk)
begin
if(clk'event and clk='1') then -- parity bits c * b
check_bits(11) <= data_in(0) xor data_in(1) xor data_in(2) xor data_in(3) xor data_in(4) xor data_in(5) xor data_in(6)
xor data_in(7) xor data_in(8) xor data_in(9) xor data_in(10);
check_bits(10) <= data_in(1) xor data_in(5) xor data_in(6) xor data_in(7) xor data_in(9) xor data_in(10) xor data_in(11);
check_bits(9) <= data_in(0) xor data_in(2) xor data_in(6) xor data_in(7) xor data_in(8) xor data_in(10) xor data_in(11);
check_bits(8) <= data_in(0) xor data_in(1) xor data_in(3) xor data_in(7) xor data_in(8) xor data_in(9) xor data_in(11);
check_bits(7) <= data_in(1) xor data_in(2) xor data_in(4) xor data_in(8) xor data_in(9) xor data_in(10) xor data_in(11);
check_bits(6) <= data_in(0) xor data_in(2) xor data_in(3) xor data_in(5) xor data_in(9) xor data_in(10) xor data_in(11);
check_bits(5) <= data_in(0) xor data_in(1) xor data_in(3) xor data_in(4) xor data_in(6) xor data_in(10) xor data_in(11);
check_bits(4) <= data_in(0) xor data_in(1) xor data_in(2) xor data_in(4) xor data_in(5) xor data_in(7) xor data_in(11);
check_bits(3) <= data_in(1) xor data_in(2) xor data_in(3) xor data_in(5) xor data_in(6) xor data_in(8) xor data_in(11);
check_bits(2) <= data_in(2) xor data_in(3) xor data_in(4) xor data_in(6) xor data_in(7) xor data_in(9) xor data_in(11);
check_bits(1) <= data_in(3) xor data_in(4) xor data_in(5) xor data_in(7) xor data_in(8) xor data_in(10) xor data_in(11);
check_bits(0) <= data_in(0) xor data_in(4) xor data_in(5) xor data_in(6) xor data_in(8) xor data_in(9) xor data_in(11);
end if;
end process;
encoded_out <= data_in & check_bits; -- c = [data,check_bits]
end Behavioral;
hdl/linear_block_code/syn/tmp/linear_block_decoder.vhd 0 → 100644
View file @ e8d940f4
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.linear_block_package.all;
-- The word, "word" is reserved for encoded data 24 bits
-- The word. "data" is reserved for non-encoded data 12 btis
entity linear_block_decoder is
port(
clk: in std_logic;
reset: in std_logic;
data_in: in word_vector;
decoded_out: out data_vector;
errorDecoded_out:out std_logic
);
end linear_block_decoder;
architecture behavioral of linear_block_decoder is
signal syndrome: word_vector :=(others =>'0');
signal errorVector: data_vector :=(others =>'0');
signal sindromexB: data_vector :=(others =>'0');
signal hammingW: integer := 0;
-- fms contral signals
type fms is (idle,step1,step2,step3,step4,deco,fail);
signal deco_state: fms;
signal deco_next : fms;
-- output control signals
signal decoded_buf : data_vector :=(others=>'0');
signal decoded_buf_next: data_vector :=(others=>'0');
-- error when it is not possible to decode
signal errorDecoded: std_logic:='0';
begin
-- decoder finite state machie
deco_fms: process(clk)
begin
if (reset='1') then
deco_state <= idle;
errorDecoded <= '0';
elsif(clk'event and clk='1') then
deco_state <= deco_next;
end if;
end process;
-- decoded output
deco_buffer: process(clk)
begin
if(reset='1') then
decoded_buf <= zeros12;
elsif(clk'event and clk='1') then
decoded_buf <= decoded_buf_next;
end if;
end process;
-- decoder logic
deco_logic: process(deco_state,data_in)
begin
case deco_state is
when idle =>
if (data_in /= zeros24) then
deco_next <= step1;
else
deco_next <= idle;
end if;
when step1 =>
-- calc syndrome and hamming(syndrome)
if (hammingW<=3) then
deco_next <= deco;
else
deco_next <= step2;
end if;
when step2 =>
-- calc error and hammingW(error)
if (hammingW<=2) then
deco_next <= deco;
else
deco_next <= step3;
end if;
when step3 =>
-- syndromexB and hammingW(syndromeB)
if (hammingW<=3) then
deco_next <= deco;
else
deco_next <= step4;
end if;
when step4 =>
-- (Beta*B+rowi) and hammingW
if (hammingW <= 3) then
deco_next <= deco;
else
deco_next <= fail;
end if;
when deco =>
deco_next <= idle;
when fail =>
deco_next <= idle;
end case;
end process;
-- output logic
output_logic: process(deco_state)
begin
decoded_buf_next <= zeros12;
case deco_next is
when idle =>
when step1 =>
when step2 =>
when step3 =>
when step4 =>
when deco =>
--decoded_buf_next <=
errorDecoded <= '0'; -- no error
when fail =>
decoded_buf_next <= zeros12;
errorDecoded <= '1';
end case;
end process;
-- output
decoded_out <= decoded_buf;
end behavioral;
hdl/linear_block_code/syn/tmp/linear_block_encoder.vhd 0 → 100644
View file @ e8d940f4
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity linear_block_enc is
port ( clk : in std_logic;
data_in : in std_logic_vector(11 downto 0);
encoded_out : out std_logic_vector(23 downto 0)
);
end linear_block_enc;
architecture Behavioral of linear_block_enc is
signal check_bits : std_logic_vector(11 downto 0):=(others =>'0');
-- b matrix
-- 555 1 0 1 0 1 0 1 0 1 0 1 0
---------------------------------------------------
-- 11 0 1 2 3 4 5 6 7 8 9 10
-- 10 1 5 6 7 9 10 11
-- 9 0 2 6 7 8 10 11
-- 8 0 1 3 7 8 9 11
-- 7 1 2 4 8 9 10 11
-- 6 0 2 3 5 9 10 11
-- 5 0 1 3 4 6 10 11
-- 4 0 1 2 4 5 7 11
-- 3 1 2 3 5 6 8 11
-- 2 2 3 4 6 7 9 11
-- 1 3 4 5 7 8 10 11
-- 0 0 4 5 6 8 9 11
begin
process(data_in,clk)
begin
if(clk'event and clk='1') then -- parity bits c * b
check_bits(11) <= data_in(0) xor data_in(1) xor data_in(2) xor data_in(3) xor data_in(4) xor data_in(5) xor data_in(6)
xor data_in(7) xor data_in(8) xor data_in(9) xor data_in(10);
check_bits(10) <= data_in(1) xor data_in(5) xor data_in(6) xor data_in(7) xor data_in(9) xor data_in(10) xor data_in(11);
check_bits(9) <= data_in(0) xor data_in(2) xor data_in(6) xor data_in(7) xor data_in(8) xor data_in(10) xor data_in(11);
check_bits(8) <= data_in(0) xor data_in(1) xor data_in(3) xor data_in(7) xor data_in(8) xor data_in(9) xor data_in(11);
check_bits(7) <= data_in(1) xor data_in(2) xor data_in(4) xor data_in(8) xor data_in(9) xor data_in(10) xor data_in(11);
check_bits(6) <= data_in(0) xor data_in(2) xor data_in(3) xor data_in(5) xor data_in(9) xor data_in(10) xor data_in(11);
check_bits(5) <= data_in(0) xor data_in(1) xor data_in(3) xor data_in(4) xor data_in(6) xor data_in(10) xor data_in(11);
check_bits(4) <= data_in(0) xor data_in(1) xor data_in(2) xor data_in(4) xor data_in(5) xor data_in(7) xor data_in(11);
check_bits(3) <= data_in(1) xor data_in(2) xor data_in(3) xor data_in(5) xor data_in(6) xor data_in(8) xor data_in(11);
check_bits(2) <= data_in(2) xor data_in(3) xor data_in(4) xor data_in(6) xor data_in(7) xor data_in(9) xor data_in(11);
check_bits(1) <= data_in(3) xor data_in(4) xor data_in(5) xor data_in(7) xor data_in(8) xor data_in(10) xor data_in(11);
check_bits(0) <= data_in(0) xor data_in(4) xor data_in(5) xor data_in(6) xor data_in(8) xor data_in(9) xor data_in(11);
end if;
end process;
encoded_out <= data_in & check_bits; -- c = [data,check_bits]
end Behavioral;
hdl/linear_block_code/syn/tmp/linear_block_package.vhd 0 → 100644
View file @ e8d940f4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package linear_block_package is
constant word_width : integer := 24;
constant data_width : integer := 12;
subtype data_vector is std_logic_vector(data_width-1 downto 0);
subtype word_vector is std_logic_vector(word_width-1 downto 0);
-- subtype fsm is std_logic_vector(2 downto 0);
constant zeros12 : data_vector :=(others=>'0');
constant zeros24 : word_vector :=(others=>'0');
type matrix is array (natural range <>) of data_vector;
-- compile with -87 support for VHDL 1987
constant bMatrix : matrix := (to_stdlogicvector(x"7ff"),to_stdlogicvector(x"ee2"),
to_stdlogicvector(x"dc5"),to_stdlogicvector(x"b8b"),
to_stdlogicvector(x"f16"),to_stdlogicvector(x"e2d"),
to_stdlogicvector(x"c5b"),to_stdlogicvector(x"8b7"),
to_stdlogicvector(x"96e"),to_stdlogicvector(x"adc"),
to_stdlogicvector(x"db8"),to_stdlogicvector(x"b71"));
-- calculates the step 1 of the algorithm
-- calc syndrome and hamming(syndrome)
procedure syndromeCal( signal word :in word_vector;
signal hammingW :out integer);
end linear_block_package;
package body linear_block_package is
-- calculates the step 1 of the algorithm
-- calc syndrome and hamming(syndrome)
procedure syndromeCal( signal word :in word_vector;
signal hammingW :out integer) is
begin
end syndromeCal;
end linear_block_package;
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