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-- Title          : Wishbone slave core for sFlow port
---------------------------------------------------------------------------------------
-- File           : wb_sflow_wb.hdl
-- Author         : auto-generated by wbgen2 from sflow-regs.wb
-- Created        : Thu Mar  1 14:24:54 2012
-- Standard       : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE sflow-regs.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.genram_pkg.all;
use work.wbgen2_pkg.all;

entity wrsw_sflow_wb is
  port (
    rst_n_i                                  : in     std_logic;
    wb_clk_i                                 : in     std_logic;
    wb_addr_i                                : in     std_logic_vector(4 downto 0);
    wb_data_i                                : in     std_logic_vector(31 downto 0);
    wb_data_o                                : out    std_logic_vector(31 downto 0);
    wb_cyc_i                                 : in     std_logic;
    wb_sel_i                                 : in     std_logic_vector(3 downto 0);
    wb_stb_i                                 : in     std_logic;
    wb_we_i                                  : in     std_logic;
    wb_ack_o                                 : out    std_logic;
    wb_irq_o                                 : out    std_logic;
    zbt_clk_i                                : in     std_logic;
-- Port for BIT field: 'sFlow Global Enable' in reg: 'sFlow Global Control Register'
    sflow_gcr_sflow_ena_o                    : out    std_logic;
    irq_nempty_i                             : in     std_logic;
-- FIFO write request
    sflow_dfifo_wr_req_i                     : in     std_logic;
-- FIFO full flag
    sflow_dfifo_wr_full_o                    : out    std_logic;
-- FIFO empty flag
    sflow_dfifo_wr_empty_o                   : out    std_logic;
    sflow_dfifo_dmac_lo_i                    : in     std_logic_vector(31 downto 0);
    sflow_dfifo_dmac_hi_i                    : in     std_logic_vector(15 downto 0);
    sflow_dfifo_smac_lo_i                    : in     std_logic_vector(31 downto 0);
    sflow_dfifo_smac_hi_i                    : in     std_logic_vector(15 downto 0);
    sflow_dfifo_vid_i                        : in     std_logic_vector(11 downto 0);
    sflow_dfifo_in_port_i                    : in     std_logic_vector(5 downto 0);
    sflow_dfifo_out_port_i                   : in     std_logic_vector(5 downto 0);
-- FIFO read request
    sflow_cfifo_rd_req_i                     : in     std_logic;
-- FIFO empty flag
    sflow_cfifo_rd_empty_o                   : out    std_logic;
-- FIFO number of used words
    sflow_cfifo_rd_usedw_o                   : out    std_logic_vector(2 downto 0);
    sflow_cfifo_conf_sflow_o                 : out    std_logic;
    sflow_cfifo_ad_val_o                     : out    std_logic_vector(31 downto 0);
-- Port for BIT field: 'Enable/Disable Counter' in reg: 'Port Control Register 0'
    sflow_pcr0_counter_en_o                  : out    std_logic;
-- Port for BIT field: 'Enable/Disable Sampling' in reg: 'Port Control Register 0'
    sflow_pcr0_sampling_en_o                 : out    std_logic;
-- Port for BIT field: 'Unreconized request behaviour' in reg: 'Port Control Register 0'
    sflow_pcr0_unre_en_o                     : out    std_logic;
-- Port for BIT field: 'Enable/Disable Counter' in reg: 'Port Control Register 1'
    sflow_pcr1_counter_en_o                  : out    std_logic;
-- Port for BIT field: 'Enable/Disable Sampling' in reg: 'Port Control Register 1'
    sflow_pcr1_sampling_en_o                 : out    std_logic;
-- Port for BIT field: 'Unreconized request behaviour' in reg: 'Port Control Register 1'
    sflow_pcr1_unre_en_o                     : out    std_logic;
-- Port for BIT field: 'Enable/Disable Counter' in reg: 'Port Control Register 2'
    sflow_pcr2_counter_en_o                  : out    std_logic;
-- Port for BIT field: 'Enable/Disable Sampling' in reg: 'Port Control Register 2'
    sflow_pcr2_sampling_en_o                 : out    std_logic;
-- Port for BIT field: 'Unreconized request behaviour' in reg: 'Port Control Register 2'
    sflow_pcr2_unre_en_o                     : out    std_logic;
-- Port for BIT field: 'Enable/Disable Counter' in reg: 'Port Control Register 3'
    sflow_pcr3_counter_en_o                  : out    std_logic;
-- Port for BIT field: 'Enable/Disable Sampling' in reg: 'Port Control Register 3'
    sflow_pcr3_sampling_en_o                 : out    std_logic;
-- Port for BIT field: 'Unreconized request behaviour' in reg: 'Port Control Register 3'
    sflow_pcr3_unre_en_o                     : out    std_logic;
-- Port for BIT field: 'Enable/Disable Counter' in reg: 'Port Control Register 4'
    sflow_pcr4_counter_en_o                  : out    std_logic;
-- Port for BIT field: 'Enable/Disable Sampling' in reg: 'Port Control Register 4'
    sflow_pcr4_sampling_en_o                 : out    std_logic;
-- Port for BIT field: 'Unreconized request behaviour' in reg: 'Port Control Register 4'
    sflow_pcr4_unre_en_o                     : out    std_logic;
-- Port for BIT field: 'Enable/Disable Counter' in reg: 'Port Control Register 5'
    sflow_pcr5_counter_en_o                  : out    std_logic;
-- Port for BIT field: 'Enable/Disable Sampling' in reg: 'Port Control Register 5'
    sflow_pcr5_sampling_en_o                 : out    std_logic;
-- Port for BIT field: 'Unreconized request behaviour' in reg: 'Port Control Register 5'
    sflow_pcr5_unre_en_o                     : out    std_logic;
-- Port for BIT field: 'Enable/Disable Counter' in reg: 'Port Control Register 6'
    sflow_pcr6_counter_en_o                  : out    std_logic;
-- Port for BIT field: 'Enable/Disable Sampling' in reg: 'Port Control Register 6'
    sflow_pcr6_sampling_en_o                 : out    std_logic;
-- Port for BIT field: 'Unreconized request behaviour' in reg: 'Port Control Register 6'
    sflow_pcr6_unre_en_o                     : out    std_logic;
-- Port for BIT field: 'Enable/Disable Counter' in reg: 'Port Control Register 7'
    sflow_pcr7_counter_en_o                  : out    std_logic;
-- Port for BIT field: 'Enable/Disable Sampling' in reg: 'Port Control Register 7'
    sflow_pcr7_sampling_en_o                 : out    std_logic;
-- Port for BIT field: 'Unreconized request behaviour' in reg: 'Port Control Register 7'
    sflow_pcr7_unre_en_o                     : out    std_logic;
-- Port for BIT field: 'Enable/Disable Counter' in reg: 'Port Control Register 8'
    sflow_pcr8_counter_en_o                  : out    std_logic;
-- Port for BIT field: 'Enable/Disable Sampling' in reg: 'Port Control Register 8'
    sflow_pcr8_sampling_en_o                 : out    std_logic;
-- Port for BIT field: 'Unreconized request behaviour' in reg: 'Port Control Register 8'
    sflow_pcr8_unre_en_o                     : out    std_logic;
-- Port for BIT field: 'Enable/Disable Counter' in reg: 'Port Control Register 9'
    sflow_pcr9_counter_en_o                  : out    std_logic;
-- Port for BIT field: 'Enable/Disable Sampling' in reg: 'Port Control Register 9'
    sflow_pcr9_sampling_en_o                 : out    std_logic;
-- Port for BIT field: 'Unreconized request behaviour' in reg: 'Port Control Register 9'
    sflow_pcr9_unre_en_o                     : out    std_logic
  );
end wrsw_sflow_wb;

architecture syn of wrsw_sflow_wb is

signal sflow_gcr_sflow_ena_int                  : std_logic      ;
signal sflow_dfifo_in_int                       : std_logic_vector(119 downto 0);
signal sflow_dfifo_out_int                      : std_logic_vector(119 downto 0);
signal sflow_dfifo_rdreq_int                    : std_logic      ;
signal sflow_dfifo_rdreq_int_d0                 : std_logic      ;
signal sflow_cfifo_in_int                       : std_logic_vector(32 downto 0);
signal sflow_cfifo_out_int                      : std_logic_vector(32 downto 0);
signal sflow_cfifo_wrreq_int                    : std_logic      ;
signal sflow_pcr0_counter_en_int                : std_logic      ;
signal sflow_pcr0_sampling_en_int               : std_logic      ;
signal sflow_pcr0_unre_en_int                   : std_logic      ;
signal sflow_pcr1_counter_en_int                : std_logic      ;
signal sflow_pcr1_sampling_en_int               : std_logic      ;
signal sflow_pcr1_unre_en_int                   : std_logic      ;
signal sflow_pcr2_counter_en_int                : std_logic      ;
signal sflow_pcr2_sampling_en_int               : std_logic      ;
signal sflow_pcr2_unre_en_int                   : std_logic      ;
signal sflow_pcr3_counter_en_int                : std_logic      ;
signal sflow_pcr3_sampling_en_int               : std_logic      ;
signal sflow_pcr3_unre_en_int                   : std_logic      ;
signal sflow_pcr4_counter_en_int                : std_logic      ;
signal sflow_pcr4_sampling_en_int               : std_logic      ;
signal sflow_pcr4_unre_en_int                   : std_logic      ;
signal sflow_pcr5_counter_en_int                : std_logic      ;
signal sflow_pcr5_sampling_en_int               : std_logic      ;
signal sflow_pcr5_unre_en_int                   : std_logic      ;
signal sflow_pcr6_counter_en_int                : std_logic      ;
signal sflow_pcr6_sampling_en_int               : std_logic      ;
signal sflow_pcr6_unre_en_int                   : std_logic      ;
signal sflow_pcr7_counter_en_int                : std_logic      ;
signal sflow_pcr7_sampling_en_int               : std_logic      ;
signal sflow_pcr7_unre_en_int                   : std_logic      ;
signal sflow_pcr8_counter_en_int                : std_logic      ;
signal sflow_pcr8_sampling_en_int               : std_logic      ;
signal sflow_pcr8_unre_en_int                   : std_logic      ;
signal sflow_pcr9_counter_en_int                : std_logic      ;
signal sflow_pcr9_sampling_en_int               : std_logic      ;
signal sflow_pcr9_unre_en_int                   : std_logic      ;
signal eic_idr_int                              : std_logic_vector(0 downto 0);
signal eic_idr_write_int                        : std_logic      ;
signal eic_ier_int                              : std_logic_vector(0 downto 0);
signal eic_ier_write_int                        : std_logic      ;
signal eic_imr_int                              : std_logic_vector(0 downto 0);
signal eic_isr_clear_int                        : std_logic_vector(0 downto 0);
signal eic_isr_status_int                       : std_logic_vector(0 downto 0);
signal eic_irq_ack_int                          : std_logic_vector(0 downto 0);
signal eic_isr_write_int                        : std_logic      ;
signal sflow_dfifo_empty_int                    : std_logic      ;
signal sflow_dfifo_usedw_int                    : std_logic_vector(5 downto 0);
signal sflow_cfifo_full_int                     : std_logic      ;
signal sflow_cfifo_empty_int                    : std_logic      ;
signal sflow_cfifo_usedw_int                    : std_logic_vector(2 downto 0);
signal irq_inputs_vector_int                    : std_logic_vector(0 downto 0);
signal ack_sreg                                 : std_logic_vector(9 downto 0);
signal rddata_reg                               : std_logic_vector(31 downto 0);
signal wrdata_reg                               : std_logic_vector(31 downto 0);
signal bwsel_reg                                : std_logic_vector(3 downto 0);
signal rwaddr_reg                               : std_logic_vector(4 downto 0);
signal ack_in_progress                          : std_logic      ;
signal wr_int                                   : std_logic      ;
signal rd_int                                   : std_logic      ;
signal bus_clock_int                            : std_logic      ;
signal allones                                  : std_logic_vector(31 downto 0);
signal allzeros                                 : std_logic_vector(31 downto 0);

begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
  wrdata_reg <= wb_data_i;
  bwsel_reg <= wb_sel_i;
  bus_clock_int <= wb_clk_i;
  rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
  wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
  allones <= (others => '1');
  allzeros <= (others => '0');
-- 
-- Main register bank access process.
  process (bus_clock_int, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      ack_sreg <= "0000000000";
      ack_in_progress <= '0';
      rddata_reg <= "00000000000000000000000000000000";
      sflow_gcr_sflow_ena_int <= '0';
      sflow_pcr0_counter_en_int <= '0';
      sflow_pcr0_sampling_en_int <= '0';
      sflow_pcr0_unre_en_int <= '0';
      sflow_pcr1_counter_en_int <= '0';
      sflow_pcr1_sampling_en_int <= '0';
      sflow_pcr1_unre_en_int <= '0';
      sflow_pcr2_counter_en_int <= '0';
      sflow_pcr2_sampling_en_int <= '0';
      sflow_pcr2_unre_en_int <= '0';
      sflow_pcr3_counter_en_int <= '0';
      sflow_pcr3_sampling_en_int <= '0';
      sflow_pcr3_unre_en_int <= '0';
      sflow_pcr4_counter_en_int <= '0';
      sflow_pcr4_sampling_en_int <= '0';
      sflow_pcr4_unre_en_int <= '0';
      sflow_pcr5_counter_en_int <= '0';
      sflow_pcr5_sampling_en_int <= '0';
      sflow_pcr5_unre_en_int <= '0';
      sflow_pcr6_counter_en_int <= '0';
      sflow_pcr6_sampling_en_int <= '0';
      sflow_pcr6_unre_en_int <= '0';
      sflow_pcr7_counter_en_int <= '0';
      sflow_pcr7_sampling_en_int <= '0';
      sflow_pcr7_unre_en_int <= '0';
      sflow_pcr8_counter_en_int <= '0';
      sflow_pcr8_sampling_en_int <= '0';
      sflow_pcr8_unre_en_int <= '0';
      sflow_pcr9_counter_en_int <= '0';
      sflow_pcr9_sampling_en_int <= '0';
      sflow_pcr9_unre_en_int <= '0';
      eic_idr_write_int <= '0';
      eic_ier_write_int <= '0';
      eic_isr_write_int <= '0';
      sflow_dfifo_rdreq_int <= '0';
      sflow_cfifo_wrreq_int <= '0';
    elsif rising_edge(bus_clock_int) then
-- advance the ACK generator shift register
      ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
      ack_sreg(9) <= '0';
      if (ack_in_progress = '1') then
        if (ack_sreg(0) = '1') then
          eic_idr_write_int <= '0';
          eic_ier_write_int <= '0';
          eic_isr_write_int <= '0';
          sflow_cfifo_wrreq_int <= '0';
          ack_in_progress <= '0';
        else
        end if;
      else
        if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
          case rwaddr_reg(4 downto 0) is
          when "00000" => 
            if (wb_we_i = '1') then
              rddata_reg(0) <= 'X';
              sflow_gcr_sflow_ena_int <= wrdata_reg(0);
            else
              rddata_reg(0) <= sflow_gcr_sflow_ena_int;
              rddata_reg(1) <= 'X';
              rddata_reg(2) <= 'X';
              rddata_reg(3) <= 'X';
              rddata_reg(4) <= 'X';
              rddata_reg(5) <= 'X';
              rddata_reg(6) <= 'X';
              rddata_reg(7) <= 'X';
              rddata_reg(8) <= 'X';
              rddata_reg(9) <= 'X';
              rddata_reg(10) <= 'X';
              rddata_reg(11) <= 'X';
              rddata_reg(12) <= 'X';
              rddata_reg(13) <= 'X';
              rddata_reg(14) <= 'X';
              rddata_reg(15) <= 'X';
              rddata_reg(16) <= 'X';
              rddata_reg(17) <= 'X';
              rddata_reg(18) <= 'X';
              rddata_reg(19) <= 'X';
              rddata_reg(20) <= 'X';
              rddata_reg(21) <= 'X';
              rddata_reg(22) <= 'X';
              rddata_reg(23) <= 'X';
              rddata_reg(24) <= 'X';
              rddata_reg(25) <= 'X';
              rddata_reg(26) <= 'X';
              rddata_reg(27) <= 'X';
              rddata_reg(28) <= 'X';
              rddata_reg(29) <= 'X';
              rddata_reg(30) <= 'X';
              rddata_reg(31) <= 'X';
            end if;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "00001" => 
            if (wb_we_i = '1') then
              rddata_reg(0) <= 'X';
              sflow_pcr0_counter_en_int <= wrdata_reg(0);
              rddata_reg(1) <= 'X';
              sflow_pcr0_sampling_en_int <= wrdata_reg(1);
              rddata_reg(2) <= 'X';
              sflow_pcr0_unre_en_int <= wrdata_reg(2);
            else
              rddata_reg(0) <= sflow_pcr0_counter_en_int;
              rddata_reg(1) <= sflow_pcr0_sampling_en_int;
              rddata_reg(2) <= sflow_pcr0_unre_en_int;
              rddata_reg(3) <= 'X';
              rddata_reg(4) <= 'X';
              rddata_reg(5) <= 'X';
              rddata_reg(6) <= 'X';
              rddata_reg(7) <= 'X';
              rddata_reg(8) <= 'X';
              rddata_reg(9) <= 'X';
              rddata_reg(10) <= 'X';
              rddata_reg(11) <= 'X';
              rddata_reg(12) <= 'X';
              rddata_reg(13) <= 'X';
              rddata_reg(14) <= 'X';
              rddata_reg(15) <= 'X';
              rddata_reg(16) <= 'X';
              rddata_reg(17) <= 'X';
              rddata_reg(18) <= 'X';
              rddata_reg(19) <= 'X';
              rddata_reg(20) <= 'X';
              rddata_reg(21) <= 'X';
              rddata_reg(22) <= 'X';
              rddata_reg(23) <= 'X';
              rddata_reg(24) <= 'X';
              rddata_reg(25) <= 'X';
              rddata_reg(26) <= 'X';
              rddata_reg(27) <= 'X';
              rddata_reg(28) <= 'X';
              rddata_reg(29) <= 'X';
              rddata_reg(30) <= 'X';
              rddata_reg(31) <= 'X';
            end if;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "00010" => 
            if (wb_we_i = '1') then
              rddata_reg(0) <= 'X';
              sflow_pcr1_counter_en_int <= wrdata_reg(0);
              rddata_reg(1) <= 'X';
              sflow_pcr1_sampling_en_int <= wrdata_reg(1);
              rddata_reg(2) <= 'X';
              sflow_pcr1_unre_en_int <= wrdata_reg(2);
            else
              rddata_reg(0) <= sflow_pcr1_counter_en_int;
              rddata_reg(1) <= sflow_pcr1_sampling_en_int;
              rddata_reg(2) <= sflow_pcr1_unre_en_int;
              rddata_reg(3) <= 'X';
              rddata_reg(4) <= 'X';
              rddata_reg(5) <= 'X';
              rddata_reg(6) <= 'X';
              rddata_reg(7) <= 'X';
              rddata_reg(8) <= 'X';
              rddata_reg(9) <= 'X';
              rddata_reg(10) <= 'X';
              rddata_reg(11) <= 'X';
              rddata_reg(12) <= 'X';
              rddata_reg(13) <= 'X';
              rddata_reg(14) <= 'X';
              rddata_reg(15) <= 'X';
              rddata_reg(16) <= 'X';
              rddata_reg(17) <= 'X';
              rddata_reg(18) <= 'X';
              rddata_reg(19) <= 'X';
              rddata_reg(20) <= 'X';
              rddata_reg(21) <= 'X';
              rddata_reg(22) <= 'X';
              rddata_reg(23) <= 'X';
              rddata_reg(24) <= 'X';
              rddata_reg(25) <= 'X';
              rddata_reg(26) <= 'X';
              rddata_reg(27) <= 'X';
              rddata_reg(28) <= 'X';
              rddata_reg(29) <= 'X';
              rddata_reg(30) <= 'X';
              rddata_reg(31) <= 'X';
            end if;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "00011" => 
            if (wb_we_i = '1') then
              rddata_reg(0) <= 'X';
              sflow_pcr2_counter_en_int <= wrdata_reg(0);
              rddata_reg(1) <= 'X';
              sflow_pcr2_sampling_en_int <= wrdata_reg(1);
              rddata_reg(2) <= 'X';
              sflow_pcr2_unre_en_int <= wrdata_reg(2);
            else
              rddata_reg(0) <= sflow_pcr2_counter_en_int;
              rddata_reg(1) <= sflow_pcr2_sampling_en_int;
              rddata_reg(2) <= sflow_pcr2_unre_en_int;
              rddata_reg(3) <= 'X';
              rddata_reg(4) <= 'X';
              rddata_reg(5) <= 'X';
              rddata_reg(6) <= 'X';
              rddata_reg(7) <= 'X';
              rddata_reg(8) <= 'X';
              rddata_reg(9) <= 'X';
              rddata_reg(10) <= 'X';
              rddata_reg(11) <= 'X';
              rddata_reg(12) <= 'X';
              rddata_reg(13) <= 'X';
              rddata_reg(14) <= 'X';
              rddata_reg(15) <= 'X';
              rddata_reg(16) <= 'X';
              rddata_reg(17) <= 'X';
              rddata_reg(18) <= 'X';
              rddata_reg(19) <= 'X';
              rddata_reg(20) <= 'X';
              rddata_reg(21) <= 'X';
              rddata_reg(22) <= 'X';
              rddata_reg(23) <= 'X';
              rddata_reg(24) <= 'X';
              rddata_reg(25) <= 'X';
              rddata_reg(26) <= 'X';
              rddata_reg(27) <= 'X';
              rddata_reg(28) <= 'X';
              rddata_reg(29) <= 'X';
              rddata_reg(30) <= 'X';
              rddata_reg(31) <= 'X';
            end if;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "00100" => 
            if (wb_we_i = '1') then
              rddata_reg(0) <= 'X';
              sflow_pcr3_counter_en_int <= wrdata_reg(0);
              rddata_reg(1) <= 'X';
              sflow_pcr3_sampling_en_int <= wrdata_reg(1);
              rddata_reg(2) <= 'X';
              sflow_pcr3_unre_en_int <= wrdata_reg(2);
            else
              rddata_reg(0) <= sflow_pcr3_counter_en_int;
              rddata_reg(1) <= sflow_pcr3_sampling_en_int;
              rddata_reg(2) <= sflow_pcr3_unre_en_int;
              rddata_reg(3) <= 'X';
              rddata_reg(4) <= 'X';
              rddata_reg(5) <= 'X';
              rddata_reg(6) <= 'X';
              rddata_reg(7) <= 'X';
              rddata_reg(8) <= 'X';
              rddata_reg(9) <= 'X';
              rddata_reg(10) <= 'X';
              rddata_reg(11) <= 'X';
              rddata_reg(12) <= 'X';
              rddata_reg(13) <= 'X';
              rddata_reg(14) <= 'X';
              rddata_reg(15) <= 'X';
              rddata_reg(16) <= 'X';
              rddata_reg(17) <= 'X';
              rddata_reg(18) <= 'X';
              rddata_reg(19) <= 'X';
              rddata_reg(20) <= 'X';
              rddata_reg(21) <= 'X';
              rddata_reg(22) <= 'X';
              rddata_reg(23) <= 'X';
              rddata_reg(24) <= 'X';
              rddata_reg(25) <= 'X';
              rddata_reg(26) <= 'X';
              rddata_reg(27) <= 'X';
              rddata_reg(28) <= 'X';
              rddata_reg(29) <= 'X';
              rddata_reg(30) <= 'X';
              rddata_reg(31) <= 'X';
            end if;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "00101" => 
            if (wb_we_i = '1') then
              rddata_reg(0) <= 'X';
              sflow_pcr4_counter_en_int <= wrdata_reg(0);
              rddata_reg(1) <= 'X';
              sflow_pcr4_sampling_en_int <= wrdata_reg(1);
              rddata_reg(2) <= 'X';
              sflow_pcr4_unre_en_int <= wrdata_reg(2);
            else
              rddata_reg(0) <= sflow_pcr4_counter_en_int;
              rddata_reg(1) <= sflow_pcr4_sampling_en_int;
              rddata_reg(2) <= sflow_pcr4_unre_en_int;
              rddata_reg(3) <= 'X';
              rddata_reg(4) <= 'X';
              rddata_reg(5) <= 'X';
              rddata_reg(6) <= 'X';
              rddata_reg(7) <= 'X';
              rddata_reg(8) <= 'X';
              rddata_reg(9) <= 'X';
              rddata_reg(10) <= 'X';
              rddata_reg(11) <= 'X';
              rddata_reg(12) <= 'X';
              rddata_reg(13) <= 'X';
              rddata_reg(14) <= 'X';
              rddata_reg(15) <= 'X';
              rddata_reg(16) <= 'X';
              rddata_reg(17) <= 'X';
              rddata_reg(18) <= 'X';
              rddata_reg(19) <= 'X';
              rddata_reg(20) <= 'X';
              rddata_reg(21) <= 'X';
              rddata_reg(22) <= 'X';
              rddata_reg(23) <= 'X';
              rddata_reg(24) <= 'X';
              rddata_reg(25) <= 'X';
              rddata_reg(26) <= 'X';
              rddata_reg(27) <= 'X';
              rddata_reg(28) <= 'X';
              rddata_reg(29) <= 'X';
              rddata_reg(30) <= 'X';
              rddata_reg(31) <= 'X';
            end if;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "00110" => 
            if (wb_we_i = '1') then
              rddata_reg(0) <= 'X';
              sflow_pcr5_counter_en_int <= wrdata_reg(0);
              rddata_reg(1) <= 'X';
              sflow_pcr5_sampling_en_int <= wrdata_reg(1);
              rddata_reg(2) <= 'X';
              sflow_pcr5_unre_en_int <= wrdata_reg(2);
            else
              rddata_reg(0) <= sflow_pcr5_counter_en_int;
              rddata_reg(1) <= sflow_pcr5_sampling_en_int;
              rddata_reg(2) <= sflow_pcr5_unre_en_int;
              rddata_reg(3) <= 'X';
              rddata_reg(4) <= 'X';
              rddata_reg(5) <= 'X';
              rddata_reg(6) <= 'X';
              rddata_reg(7) <= 'X';
              rddata_reg(8) <= 'X';
              rddata_reg(9) <= 'X';
              rddata_reg(10) <= 'X';
              rddata_reg(11) <= 'X';
              rddata_reg(12) <= 'X';
              rddata_reg(13) <= 'X';
              rddata_reg(14) <= 'X';
              rddata_reg(15) <= 'X';
              rddata_reg(16) <= 'X';
              rddata_reg(17) <= 'X';
              rddata_reg(18) <= 'X';
              rddata_reg(19) <= 'X';
              rddata_reg(20) <= 'X';
              rddata_reg(21) <= 'X';
              rddata_reg(22) <= 'X';
              rddata_reg(23) <= 'X';
              rddata_reg(24) <= 'X';
              rddata_reg(25) <= 'X';
              rddata_reg(26) <= 'X';
              rddata_reg(27) <= 'X';
              rddata_reg(28) <= 'X';
              rddata_reg(29) <= 'X';
              rddata_reg(30) <= 'X';
              rddata_reg(31) <= 'X';
            end if;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "00111" => 
            if (wb_we_i = '1') then
              rddata_reg(0) <= 'X';
              sflow_pcr6_counter_en_int <= wrdata_reg(0);
              rddata_reg(1) <= 'X';
              sflow_pcr6_sampling_en_int <= wrdata_reg(1);
              rddata_reg(2) <= 'X';
              sflow_pcr6_unre_en_int <= wrdata_reg(2);
            else
              rddata_reg(0) <= sflow_pcr6_counter_en_int;
              rddata_reg(1) <= sflow_pcr6_sampling_en_int;
              rddata_reg(2) <= sflow_pcr6_unre_en_int;
              rddata_reg(3) <= 'X';
              rddata_reg(4) <= 'X';
              rddata_reg(5) <= 'X';
              rddata_reg(6) <= 'X';
              rddata_reg(7) <= 'X';
              rddata_reg(8) <= 'X';
              rddata_reg(9) <= 'X';
              rddata_reg(10) <= 'X';
              rddata_reg(11) <= 'X';
              rddata_reg(12) <= 'X';
              rddata_reg(13) <= 'X';
              rddata_reg(14) <= 'X';
              rddata_reg(15) <= 'X';
              rddata_reg(16) <= 'X';
              rddata_reg(17) <= 'X';
              rddata_reg(18) <= 'X';
              rddata_reg(19) <= 'X';
              rddata_reg(20) <= 'X';
              rddata_reg(21) <= 'X';
              rddata_reg(22) <= 'X';
              rddata_reg(23) <= 'X';
              rddata_reg(24) <= 'X';
              rddata_reg(25) <= 'X';
              rddata_reg(26) <= 'X';
              rddata_reg(27) <= 'X';
              rddata_reg(28) <= 'X';
              rddata_reg(29) <= 'X';
              rddata_reg(30) <= 'X';
              rddata_reg(31) <= 'X';
            end if;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "01000" => 
            if (wb_we_i = '1') then
              rddata_reg(0) <= 'X';
              sflow_pcr7_counter_en_int <= wrdata_reg(0);
              rddata_reg(1) <= 'X';
              sflow_pcr7_sampling_en_int <= wrdata_reg(1);
              rddata_reg(2) <= 'X';
              sflow_pcr7_unre_en_int <= wrdata_reg(2);
            else
              rddata_reg(0) <= sflow_pcr7_counter_en_int;
              rddata_reg(1) <= sflow_pcr7_sampling_en_int;
              rddata_reg(2) <= sflow_pcr7_unre_en_int;
              rddata_reg(3) <= 'X';
              rddata_reg(4) <= 'X';
              rddata_reg(5) <= 'X';
              rddata_reg(6) <= 'X';
              rddata_reg(7) <= 'X';
              rddata_reg(8) <= 'X';
              rddata_reg(9) <= 'X';
              rddata_reg(10) <= 'X';
              rddata_reg(11) <= 'X';
              rddata_reg(12) <= 'X';
              rddata_reg(13) <= 'X';
              rddata_reg(14) <= 'X';
              rddata_reg(15) <= 'X';
              rddata_reg(16) <= 'X';
              rddata_reg(17) <= 'X';
              rddata_reg(18) <= 'X';
              rddata_reg(19) <= 'X';
              rddata_reg(20) <= 'X';
              rddata_reg(21) <= 'X';
              rddata_reg(22) <= 'X';
              rddata_reg(23) <= 'X';
              rddata_reg(24) <= 'X';
              rddata_reg(25) <= 'X';
              rddata_reg(26) <= 'X';
              rddata_reg(27) <= 'X';
              rddata_reg(28) <= 'X';
              rddata_reg(29) <= 'X';
              rddata_reg(30) <= 'X';
              rddata_reg(31) <= 'X';
            end if;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "01001" => 
            if (wb_we_i = '1') then
              rddata_reg(0) <= 'X';
              sflow_pcr8_counter_en_int <= wrdata_reg(0);
              rddata_reg(1) <= 'X';
              sflow_pcr8_sampling_en_int <= wrdata_reg(1);
              rddata_reg(2) <= 'X';
              sflow_pcr8_unre_en_int <= wrdata_reg(2);
            else
              rddata_reg(0) <= sflow_pcr8_counter_en_int;
              rddata_reg(1) <= sflow_pcr8_sampling_en_int;
              rddata_reg(2) <= sflow_pcr8_unre_en_int;
              rddata_reg(3) <= 'X';
              rddata_reg(4) <= 'X';
              rddata_reg(5) <= 'X';
              rddata_reg(6) <= 'X';
              rddata_reg(7) <= 'X';
              rddata_reg(8) <= 'X';
              rddata_reg(9) <= 'X';
              rddata_reg(10) <= 'X';
              rddata_reg(11) <= 'X';
              rddata_reg(12) <= 'X';
              rddata_reg(13) <= 'X';
              rddata_reg(14) <= 'X';
              rddata_reg(15) <= 'X';
              rddata_reg(16) <= 'X';
              rddata_reg(17) <= 'X';
              rddata_reg(18) <= 'X';
              rddata_reg(19) <= 'X';
              rddata_reg(20) <= 'X';
              rddata_reg(21) <= 'X';
              rddata_reg(22) <= 'X';
              rddata_reg(23) <= 'X';
              rddata_reg(24) <= 'X';
              rddata_reg(25) <= 'X';
              rddata_reg(26) <= 'X';
              rddata_reg(27) <= 'X';
              rddata_reg(28) <= 'X';
              rddata_reg(29) <= 'X';
              rddata_reg(30) <= 'X';
              rddata_reg(31) <= 'X';
            end if;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "01010" => 
            if (wb_we_i = '1') then
              rddata_reg(0) <= 'X';
              sflow_pcr9_counter_en_int <= wrdata_reg(0);
              rddata_reg(1) <= 'X';
              sflow_pcr9_sampling_en_int <= wrdata_reg(1);
              rddata_reg(2) <= 'X';
              sflow_pcr9_unre_en_int <= wrdata_reg(2);
            else
              rddata_reg(0) <= sflow_pcr9_counter_en_int;
              rddata_reg(1) <= sflow_pcr9_sampling_en_int;
              rddata_reg(2) <= sflow_pcr9_unre_en_int;
              rddata_reg(3) <= 'X';
              rddata_reg(4) <= 'X';
              rddata_reg(5) <= 'X';
              rddata_reg(6) <= 'X';
              rddata_reg(7) <= 'X';
              rddata_reg(8) <= 'X';
              rddata_reg(9) <= 'X';
              rddata_reg(10) <= 'X';
              rddata_reg(11) <= 'X';
              rddata_reg(12) <= 'X';
              rddata_reg(13) <= 'X';
              rddata_reg(14) <= 'X';
              rddata_reg(15) <= 'X';
              rddata_reg(16) <= 'X';
              rddata_reg(17) <= 'X';
              rddata_reg(18) <= 'X';
              rddata_reg(19) <= 'X';
              rddata_reg(20) <= 'X';
              rddata_reg(21) <= 'X';
              rddata_reg(22) <= 'X';
              rddata_reg(23) <= 'X';
              rddata_reg(24) <= 'X';
              rddata_reg(25) <= 'X';
              rddata_reg(26) <= 'X';
              rddata_reg(27) <= 'X';
              rddata_reg(28) <= 'X';
              rddata_reg(29) <= 'X';
              rddata_reg(30) <= 'X';
              rddata_reg(31) <= 'X';
            end if;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "10000" => 
            if (wb_we_i = '1') then
              eic_idr_write_int <= '1';
            else
              rddata_reg(0) <= 'X';
              rddata_reg(1) <= 'X';
              rddata_reg(2) <= 'X';
              rddata_reg(3) <= 'X';
              rddata_reg(4) <= 'X';
              rddata_reg(5) <= 'X';
              rddata_reg(6) <= 'X';
              rddata_reg(7) <= 'X';
              rddata_reg(8) <= 'X';
              rddata_reg(9) <= 'X';
              rddata_reg(10) <= 'X';
              rddata_reg(11) <= 'X';
              rddata_reg(12) <= 'X';
              rddata_reg(13) <= 'X';
              rddata_reg(14) <= 'X';
              rddata_reg(15) <= 'X';
              rddata_reg(16) <= 'X';
              rddata_reg(17) <= 'X';
              rddata_reg(18) <= 'X';
              rddata_reg(19) <= 'X';
              rddata_reg(20) <= 'X';
              rddata_reg(21) <= 'X';
              rddata_reg(22) <= 'X';
              rddata_reg(23) <= 'X';
              rddata_reg(24) <= 'X';
              rddata_reg(25) <= 'X';
              rddata_reg(26) <= 'X';
              rddata_reg(27) <= 'X';
              rddata_reg(28) <= 'X';
              rddata_reg(29) <= 'X';
              rddata_reg(30) <= 'X';
              rddata_reg(31) <= 'X';
            end if;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "10001" => 
            if (wb_we_i = '1') then
              eic_ier_write_int <= '1';
            else
              rddata_reg(0) <= 'X';
              rddata_reg(1) <= 'X';
              rddata_reg(2) <= 'X';
              rddata_reg(3) <= 'X';
              rddata_reg(4) <= 'X';
              rddata_reg(5) <= 'X';
              rddata_reg(6) <= 'X';
              rddata_reg(7) <= 'X';
              rddata_reg(8) <= 'X';
              rddata_reg(9) <= 'X';
              rddata_reg(10) <= 'X';
              rddata_reg(11) <= 'X';
              rddata_reg(12) <= 'X';
              rddata_reg(13) <= 'X';
              rddata_reg(14) <= 'X';
              rddata_reg(15) <= 'X';
              rddata_reg(16) <= 'X';
              rddata_reg(17) <= 'X';
              rddata_reg(18) <= 'X';
              rddata_reg(19) <= 'X';
              rddata_reg(20) <= 'X';
              rddata_reg(21) <= 'X';
              rddata_reg(22) <= 'X';
              rddata_reg(23) <= 'X';
              rddata_reg(24) <= 'X';
              rddata_reg(25) <= 'X';
              rddata_reg(26) <= 'X';
              rddata_reg(27) <= 'X';
              rddata_reg(28) <= 'X';
              rddata_reg(29) <= 'X';
              rddata_reg(30) <= 'X';
              rddata_reg(31) <= 'X';
            end if;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "10010" => 
            if (wb_we_i = '1') then
            else
              rddata_reg(0) <= eic_imr_int(0);
              rddata_reg(1) <= 'X';
              rddata_reg(2) <= 'X';
              rddata_reg(3) <= 'X';
              rddata_reg(4) <= 'X';
              rddata_reg(5) <= 'X';
              rddata_reg(6) <= 'X';
              rddata_reg(7) <= 'X';
              rddata_reg(8) <= 'X';
              rddata_reg(9) <= 'X';
              rddata_reg(10) <= 'X';
              rddata_reg(11) <= 'X';
              rddata_reg(12) <= 'X';
              rddata_reg(13) <= 'X';
              rddata_reg(14) <= 'X';
              rddata_reg(15) <= 'X';
              rddata_reg(16) <= 'X';
              rddata_reg(17) <= 'X';
              rddata_reg(18) <= 'X';
              rddata_reg(19) <= 'X';
              rddata_reg(20) <= 'X';
              rddata_reg(21) <= 'X';
              rddata_reg(22) <= 'X';
              rddata_reg(23) <= 'X';
              rddata_reg(24) <= 'X';
              rddata_reg(25) <= 'X';
              rddata_reg(26) <= 'X';
              rddata_reg(27) <= 'X';
              rddata_reg(28) <= 'X';
              rddata_reg(29) <= 'X';
              rddata_reg(30) <= 'X';
              rddata_reg(31) <= 'X';
            end if;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "10011" => 
            if (wb_we_i = '1') then
              eic_isr_write_int <= '1';
            else
              rddata_reg(0) <= eic_isr_status_int(0);
              rddata_reg(1) <= 'X';
              rddata_reg(2) <= 'X';
              rddata_reg(3) <= 'X';
              rddata_reg(4) <= 'X';
              rddata_reg(5) <= 'X';
              rddata_reg(6) <= 'X';
              rddata_reg(7) <= 'X';
              rddata_reg(8) <= 'X';
              rddata_reg(9) <= 'X';
              rddata_reg(10) <= 'X';
              rddata_reg(11) <= 'X';
              rddata_reg(12) <= 'X';
              rddata_reg(13) <= 'X';
              rddata_reg(14) <= 'X';
              rddata_reg(15) <= 'X';
              rddata_reg(16) <= 'X';
              rddata_reg(17) <= 'X';
              rddata_reg(18) <= 'X';
              rddata_reg(19) <= 'X';
              rddata_reg(20) <= 'X';
              rddata_reg(21) <= 'X';
              rddata_reg(22) <= 'X';
              rddata_reg(23) <= 'X';
              rddata_reg(24) <= 'X';
              rddata_reg(25) <= 'X';
              rddata_reg(26) <= 'X';
              rddata_reg(27) <= 'X';
              rddata_reg(28) <= 'X';
              rddata_reg(29) <= 'X';
              rddata_reg(30) <= 'X';
              rddata_reg(31) <= 'X';
            end if;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "10100" => 
            if (wb_we_i = '1') then
            else
              if (sflow_dfifo_rdreq_int_d0 = '0') then
                sflow_dfifo_rdreq_int <= not sflow_dfifo_rdreq_int;
              else
                rddata_reg(31 downto 0) <= sflow_dfifo_out_int(31 downto 0);
                ack_in_progress <= '1';
                ack_sreg(0) <= '1';
              end if;
            end if;
          when "10101" => 
            if (wb_we_i = '1') then
            else
              rddata_reg(15 downto 0) <= sflow_dfifo_out_int(47 downto 32);
              rddata_reg(16) <= 'X';
              rddata_reg(17) <= 'X';
              rddata_reg(18) <= 'X';
              rddata_reg(19) <= 'X';
              rddata_reg(20) <= 'X';
              rddata_reg(21) <= 'X';
              rddata_reg(22) <= 'X';
              rddata_reg(23) <= 'X';
              rddata_reg(24) <= 'X';
              rddata_reg(25) <= 'X';
              rddata_reg(26) <= 'X';
              rddata_reg(27) <= 'X';
              rddata_reg(28) <= 'X';
              rddata_reg(29) <= 'X';
              rddata_reg(30) <= 'X';
              rddata_reg(31) <= 'X';
            end if;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "10110" => 
            if (wb_we_i = '1') then
            else
              rddata_reg(31 downto 0) <= sflow_dfifo_out_int(79 downto 48);
            end if;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "10111" => 
            if (wb_we_i = '1') then
            else
              rddata_reg(15 downto 0) <= sflow_dfifo_out_int(95 downto 80);
              rddata_reg(16) <= 'X';
              rddata_reg(17) <= 'X';
              rddata_reg(18) <= 'X';
              rddata_reg(19) <= 'X';
              rddata_reg(20) <= 'X';
              rddata_reg(21) <= 'X';
              rddata_reg(22) <= 'X';
              rddata_reg(23) <= 'X';
              rddata_reg(24) <= 'X';
              rddata_reg(25) <= 'X';
              rddata_reg(26) <= 'X';
              rddata_reg(27) <= 'X';
              rddata_reg(28) <= 'X';
              rddata_reg(29) <= 'X';
              rddata_reg(30) <= 'X';
              rddata_reg(31) <= 'X';
            end if;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "11000" => 
            if (wb_we_i = '1') then
            else
              rddata_reg(11 downto 0) <= sflow_dfifo_out_int(107 downto 96);
              rddata_reg(12) <= 'X';
              rddata_reg(13) <= 'X';
              rddata_reg(14) <= 'X';
              rddata_reg(15) <= 'X';
              rddata_reg(16) <= 'X';
              rddata_reg(17) <= 'X';
              rddata_reg(18) <= 'X';
              rddata_reg(19) <= 'X';
              rddata_reg(20) <= 'X';
              rddata_reg(21) <= 'X';
              rddata_reg(22) <= 'X';
              rddata_reg(23) <= 'X';
              rddata_reg(24) <= 'X';
              rddata_reg(25) <= 'X';
              rddata_reg(26) <= 'X';
              rddata_reg(27) <= 'X';
              rddata_reg(28) <= 'X';
              rddata_reg(29) <= 'X';
              rddata_reg(30) <= 'X';
              rddata_reg(31) <= 'X';
            end if;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "11001" => 
            if (wb_we_i = '1') then
            else
              rddata_reg(5 downto 0) <= sflow_dfifo_out_int(113 downto 108);
              rddata_reg(6) <= 'X';
              rddata_reg(7) <= 'X';
              rddata_reg(8) <= 'X';
              rddata_reg(9) <= 'X';
              rddata_reg(10) <= 'X';
              rddata_reg(11) <= 'X';
              rddata_reg(12) <= 'X';
              rddata_reg(13) <= 'X';
              rddata_reg(14) <= 'X';
              rddata_reg(15) <= 'X';
              rddata_reg(16) <= 'X';
              rddata_reg(17) <= 'X';
              rddata_reg(18) <= 'X';
              rddata_reg(19) <= 'X';
              rddata_reg(20) <= 'X';
              rddata_reg(21) <= 'X';
              rddata_reg(22) <= 'X';
              rddata_reg(23) <= 'X';
              rddata_reg(24) <= 'X';
              rddata_reg(25) <= 'X';
              rddata_reg(26) <= 'X';
              rddata_reg(27) <= 'X';
              rddata_reg(28) <= 'X';
              rddata_reg(29) <= 'X';
              rddata_reg(30) <= 'X';
              rddata_reg(31) <= 'X';
            end if;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "11010" => 
            if (wb_we_i = '1') then
            else
              rddata_reg(5 downto 0) <= sflow_dfifo_out_int(119 downto 114);
              rddata_reg(6) <= 'X';
              rddata_reg(7) <= 'X';
              rddata_reg(8) <= 'X';
              rddata_reg(9) <= 'X';
              rddata_reg(10) <= 'X';
              rddata_reg(11) <= 'X';
              rddata_reg(12) <= 'X';
              rddata_reg(13) <= 'X';
              rddata_reg(14) <= 'X';
              rddata_reg(15) <= 'X';
              rddata_reg(16) <= 'X';
              rddata_reg(17) <= 'X';
              rddata_reg(18) <= 'X';
              rddata_reg(19) <= 'X';
              rddata_reg(20) <= 'X';
              rddata_reg(21) <= 'X';
              rddata_reg(22) <= 'X';
              rddata_reg(23) <= 'X';
              rddata_reg(24) <= 'X';
              rddata_reg(25) <= 'X';
              rddata_reg(26) <= 'X';
              rddata_reg(27) <= 'X';
              rddata_reg(28) <= 'X';
              rddata_reg(29) <= 'X';
              rddata_reg(30) <= 'X';
              rddata_reg(31) <= 'X';
            end if;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "11011" => 
            if (wb_we_i = '1') then
            else
              rddata_reg(17) <= sflow_dfifo_empty_int;
              rddata_reg(5 downto 0) <= sflow_dfifo_usedw_int;
              rddata_reg(6) <= 'X';
              rddata_reg(7) <= 'X';
              rddata_reg(8) <= 'X';
              rddata_reg(9) <= 'X';
              rddata_reg(10) <= 'X';
              rddata_reg(11) <= 'X';
              rddata_reg(12) <= 'X';
              rddata_reg(13) <= 'X';
              rddata_reg(14) <= 'X';
              rddata_reg(15) <= 'X';
              rddata_reg(16) <= 'X';
              rddata_reg(18) <= 'X';
              rddata_reg(19) <= 'X';
              rddata_reg(20) <= 'X';
              rddata_reg(21) <= 'X';
              rddata_reg(22) <= 'X';
              rddata_reg(23) <= 'X';
              rddata_reg(24) <= 'X';
              rddata_reg(25) <= 'X';
              rddata_reg(26) <= 'X';
              rddata_reg(27) <= 'X';
              rddata_reg(28) <= 'X';
              rddata_reg(29) <= 'X';
              rddata_reg(30) <= 'X';
              rddata_reg(31) <= 'X';
            end if;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "11100" => 
            if (wb_we_i = '1') then
              sflow_cfifo_in_int(0) <= wrdata_reg(0);
            else
              rddata_reg(0) <= 'X';
              rddata_reg(1) <= 'X';
              rddata_reg(2) <= 'X';
              rddata_reg(3) <= 'X';
              rddata_reg(4) <= 'X';
              rddata_reg(5) <= 'X';
              rddata_reg(6) <= 'X';
              rddata_reg(7) <= 'X';
              rddata_reg(8) <= 'X';
              rddata_reg(9) <= 'X';
              rddata_reg(10) <= 'X';
              rddata_reg(11) <= 'X';
              rddata_reg(12) <= 'X';
              rddata_reg(13) <= 'X';
              rddata_reg(14) <= 'X';
              rddata_reg(15) <= 'X';
              rddata_reg(16) <= 'X';
              rddata_reg(17) <= 'X';
              rddata_reg(18) <= 'X';
              rddata_reg(19) <= 'X';
              rddata_reg(20) <= 'X';
              rddata_reg(21) <= 'X';
              rddata_reg(22) <= 'X';
              rddata_reg(23) <= 'X';
              rddata_reg(24) <= 'X';
              rddata_reg(25) <= 'X';
              rddata_reg(26) <= 'X';
              rddata_reg(27) <= 'X';
              rddata_reg(28) <= 'X';
              rddata_reg(29) <= 'X';
              rddata_reg(30) <= 'X';
              rddata_reg(31) <= 'X';
            end if;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "11101" => 
            if (wb_we_i = '1') then
              sflow_cfifo_in_int(32 downto 1) <= wrdata_reg(31 downto 0);
              sflow_cfifo_wrreq_int <= '1';
            else
              rddata_reg(0) <= 'X';
              rddata_reg(1) <= 'X';
              rddata_reg(2) <= 'X';
              rddata_reg(3) <= 'X';
              rddata_reg(4) <= 'X';
              rddata_reg(5) <= 'X';
              rddata_reg(6) <= 'X';
              rddata_reg(7) <= 'X';
              rddata_reg(8) <= 'X';
              rddata_reg(9) <= 'X';
              rddata_reg(10) <= 'X';
              rddata_reg(11) <= 'X';
              rddata_reg(12) <= 'X';
              rddata_reg(13) <= 'X';
              rddata_reg(14) <= 'X';
              rddata_reg(15) <= 'X';
              rddata_reg(16) <= 'X';
              rddata_reg(17) <= 'X';
              rddata_reg(18) <= 'X';
              rddata_reg(19) <= 'X';
              rddata_reg(20) <= 'X';
              rddata_reg(21) <= 'X';
              rddata_reg(22) <= 'X';
              rddata_reg(23) <= 'X';
              rddata_reg(24) <= 'X';
              rddata_reg(25) <= 'X';
              rddata_reg(26) <= 'X';
              rddata_reg(27) <= 'X';
              rddata_reg(28) <= 'X';
              rddata_reg(29) <= 'X';
              rddata_reg(30) <= 'X';
              rddata_reg(31) <= 'X';
            end if;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "11110" => 
            if (wb_we_i = '1') then
            else
              rddata_reg(16) <= sflow_cfifo_full_int;
              rddata_reg(17) <= sflow_cfifo_empty_int;
              rddata_reg(2 downto 0) <= sflow_cfifo_usedw_int;
              rddata_reg(3) <= 'X';
              rddata_reg(4) <= 'X';
              rddata_reg(5) <= 'X';
              rddata_reg(6) <= 'X';
              rddata_reg(7) <= 'X';
              rddata_reg(8) <= 'X';
              rddata_reg(9) <= 'X';
              rddata_reg(10) <= 'X';
              rddata_reg(11) <= 'X';
              rddata_reg(12) <= 'X';
              rddata_reg(13) <= 'X';
              rddata_reg(14) <= 'X';
              rddata_reg(15) <= 'X';
              rddata_reg(18) <= 'X';
              rddata_reg(19) <= 'X';
              rddata_reg(20) <= 'X';
              rddata_reg(21) <= 'X';
              rddata_reg(22) <= 'X';
              rddata_reg(23) <= 'X';
              rddata_reg(24) <= 'X';
              rddata_reg(25) <= 'X';
              rddata_reg(26) <= 'X';
              rddata_reg(27) <= 'X';
              rddata_reg(28) <= 'X';
              rddata_reg(29) <= 'X';
              rddata_reg(30) <= 'X';
              rddata_reg(31) <= 'X';
            end if;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when others =>
-- prevent the slave from hanging the bus on invalid address
            ack_in_progress <= '1';
            ack_sreg(0) <= '1';
          end case;
        end if;
      end if;
    end if;
  end process;
  
  
-- Drive the data output bus
  wb_data_o <= rddata_reg;
-- sFlow Global Enable
  sflow_gcr_sflow_ena_o <= sflow_gcr_sflow_ena_int;
-- extra code for reg/fifo/mem: Counter or Sampling information
  sflow_dfifo_in_int(31 downto 0) <= sflow_dfifo_dmac_lo_i;
  sflow_dfifo_in_int(47 downto 32) <= sflow_dfifo_dmac_hi_i;
  sflow_dfifo_in_int(79 downto 48) <= sflow_dfifo_smac_lo_i;
  sflow_dfifo_in_int(95 downto 80) <= sflow_dfifo_smac_hi_i;
  sflow_dfifo_in_int(107 downto 96) <= sflow_dfifo_vid_i;
  sflow_dfifo_in_int(113 downto 108) <= sflow_dfifo_in_port_i;
  sflow_dfifo_in_int(119 downto 114) <= sflow_dfifo_out_port_i;
  sflow_dfifo_INST : wbgen2_fifo_sync
    generic map (
      g_size               => 64,
      g_width              => 120,
      g_usedw_size         => 6
    )
    port map (
      wr_req_i             => sflow_dfifo_wr_req_i,
      wr_full_o            => sflow_dfifo_wr_full_o,
      wr_empty_o           => sflow_dfifo_wr_empty_o,
      rd_full_o            => open,
      rd_empty_o           => sflow_dfifo_empty_int,
      rd_usedw_o           => sflow_dfifo_usedw_int,
      rd_req_i             => sflow_dfifo_rdreq_int,
      clk_i                => bus_clock_int,
      wr_data_i            => sflow_dfifo_in_int,
      rd_data_o            => sflow_dfifo_out_int
    );
  
-- extra code for reg/fifo/mem: Configuration CPU access FIFO (CFIFO)
  sflow_cfifo_conf_sflow_o <= sflow_cfifo_out_int(0);
  sflow_cfifo_ad_val_o <= sflow_cfifo_out_int(32 downto 1);
  sflow_cfifo_INST : wbgen2_fifo_async
    generic map (
      g_size               => 8,
      g_width              => 33,
      g_usedw_size         => 3
    )
    port map (
      rd_req_i             => sflow_cfifo_rd_req_i,
      rd_empty_o           => sflow_cfifo_rd_empty_o,
      rd_usedw_o           => sflow_cfifo_rd_usedw_o,
      wr_full_o            => sflow_cfifo_full_int,
      wr_empty_o           => sflow_cfifo_empty_int,
      wr_usedw_o           => sflow_cfifo_usedw_int,
      wr_req_i             => sflow_cfifo_wrreq_int,
      rd_clk_i             => zbt_clk_i,
      wr_clk_i             => bus_clock_int,
      wr_data_i            => sflow_cfifo_in_int,
      rd_data_o            => sflow_cfifo_out_int
    );
  
-- Enable/Disable Counter  
  sflow_pcr0_counter_en_o <= sflow_pcr0_counter_en_int;
-- Enable/Disable Sampling
  sflow_pcr0_sampling_en_o <= sflow_pcr0_sampling_en_int;
-- Unreconized request behaviour
  sflow_pcr0_unre_en_o <= sflow_pcr0_unre_en_int;
-- Enable/Disable Counter
  sflow_pcr1_counter_en_o <= sflow_pcr1_counter_en_int;
-- Enable/Disable Sampling
  sflow_pcr1_sampling_en_o <= sflow_pcr1_sampling_en_int;
-- Unreconized request behaviour
  sflow_pcr1_unre_en_o <= sflow_pcr1_unre_en_int;
-- Enable/Disable Counter
  sflow_pcr2_counter_en_o <= sflow_pcr2_counter_en_int;
-- Enable/Disable Sampling
  sflow_pcr2_sampling_en_o <= sflow_pcr2_sampling_en_int;
-- Unreconized request behaviour
  sflow_pcr2_unre_en_o <= sflow_pcr2_unre_en_int;
-- Enable/Disable Counter
  sflow_pcr3_counter_en_o <= sflow_pcr3_counter_en_int;
-- Enable/Disable Sampling
  sflow_pcr3_sampling_en_o <= sflow_pcr3_sampling_en_int;
-- Unreconized request behaviour
  sflow_pcr3_unre_en_o <= sflow_pcr3_unre_en_int;
-- Enable/Disable Counter
  sflow_pcr4_counter_en_o <= sflow_pcr4_counter_en_int;
-- Enable/Disable Sampling
  sflow_pcr4_sampling_en_o <= sflow_pcr4_sampling_en_int;
-- Unreconized request behaviour
  sflow_pcr4_unre_en_o <= sflow_pcr4_unre_en_int;
-- Enable/Disable Counter
  sflow_pcr5_counter_en_o <= sflow_pcr5_counter_en_int;
-- Enable/Disable Sampling
  sflow_pcr5_sampling_en_o <= sflow_pcr5_sampling_en_int;
-- Unreconized request behaviour
  sflow_pcr5_unre_en_o <= sflow_pcr5_unre_en_int;
-- Enable/Disable Counter
  sflow_pcr6_counter_en_o <= sflow_pcr6_counter_en_int;
-- Enable/Disable Sampling
  sflow_pcr6_sampling_en_o <= sflow_pcr6_sampling_en_int;
-- Unreconized request behaviour
  sflow_pcr6_unre_en_o <= sflow_pcr6_unre_en_int;
-- Enable/Disable Counter
  sflow_pcr7_counter_en_o <= sflow_pcr7_counter_en_int;
-- Enable/Disable Sampling
  sflow_pcr7_sampling_en_o <= sflow_pcr7_sampling_en_int;
-- Unreconized request behaviour
  sflow_pcr7_unre_en_o <= sflow_pcr7_unre_en_int;
-- Enable/Disable Counter
  sflow_pcr8_counter_en_o <= sflow_pcr8_counter_en_int;
-- Enable/Disable Sampling
  sflow_pcr8_sampling_en_o <= sflow_pcr8_sampling_en_int;
-- Unreconized request behaviour
  sflow_pcr8_unre_en_o <= sflow_pcr8_unre_en_int;
-- Enable/Disable Counter
  sflow_pcr9_counter_en_o <= sflow_pcr9_counter_en_int;
-- Enable/Disable Sampling
  sflow_pcr9_sampling_en_o <= sflow_pcr9_sampling_en_int;
-- Unreconized request behaviour
  sflow_pcr9_unre_en_o <= sflow_pcr9_unre_en_int;
-- extra code for reg/fifo/mem: Interrupt disable register
  eic_idr_int(0) <= wrdata_reg(0);
-- extra code for reg/fifo/mem: Interrupt enable register
  eic_ier_int(0) <= wrdata_reg(0);
-- extra code for reg/fifo/mem: Interrupt status register
  eic_isr_clear_int(0) <= wrdata_reg(0);
-- extra code for reg/fifo/mem: IRQ_CONTROLLER
  eic_irq_controller_inst : wbgen2_eic
    generic map (
      g_num_interrupts     => 1,
      g_irq00_mode         => 2,
      g_irq01_mode         => 0,
      g_irq02_mode         => 0,
      g_irq03_mode         => 0,
      g_irq04_mode         => 0,
      g_irq05_mode         => 0,
      g_irq06_mode         => 0,
      g_irq07_mode         => 0,
      g_irq08_mode         => 0,
      g_irq09_mode         => 0,
      g_irq0a_mode         => 0,
      g_irq0b_mode         => 0,
      g_irq0c_mode         => 0,
      g_irq0d_mode         => 0,
      g_irq0e_mode         => 0,
      g_irq0f_mode         => 0,
      g_irq10_mode         => 0,
      g_irq11_mode         => 0,
      g_irq12_mode         => 0,
      g_irq13_mode         => 0,
      g_irq14_mode         => 0,
      g_irq15_mode         => 0,
      g_irq16_mode         => 0,
      g_irq17_mode         => 0,
      g_irq18_mode         => 0,
      g_irq19_mode         => 0,
      g_irq1a_mode         => 0,
      g_irq1b_mode         => 0,
      g_irq1c_mode         => 0,
      g_irq1d_mode         => 0,
      g_irq1e_mode         => 0,
      g_irq1f_mode         => 0
    )
    port map (
      clk_i                => bus_clock_int,
      rst_n_i              => rst_n_i,
      irq_i                => irq_inputs_vector_int,
      irq_ack_o            => eic_irq_ack_int,
      reg_imr_o            => eic_imr_int,
      reg_ier_i            => eic_ier_int,
      reg_ier_wr_stb_i     => eic_ier_write_int,
      reg_idr_i            => eic_idr_int,
      reg_idr_wr_stb_i     => eic_idr_write_int,
      reg_isr_o            => eic_isr_status_int,
      reg_isr_i            => eic_isr_clear_int,
      reg_isr_wr_stb_i     => eic_isr_write_int,
      wb_irq_o             => wb_irq_o
    );
  
  irq_inputs_vector_int(0) <= irq_nempty_i;
-- extra code for reg/fifo/mem: FIFO 'Counter or Sampling information' data output register 0
  process (bus_clock_int, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      sflow_dfifo_rdreq_int_d0 <= '0';
    elsif rising_edge(bus_clock_int) then
      sflow_dfifo_rdreq_int_d0 <= sflow_dfifo_rdreq_int;
    end if;
  end process;
  
  
-- extra code for reg/fifo/mem: FIFO 'Counter or Sampling information' data output register 1
-- extra code for reg/fifo/mem: FIFO 'Counter or Sampling information' data output register 2
-- extra code for reg/fifo/mem: FIFO 'Counter or Sampling information' data output register 3
-- extra code for reg/fifo/mem: FIFO 'Counter or Sampling information' data output register 4
-- extra code for reg/fifo/mem: FIFO 'Counter or Sampling information' data output register 5
-- extra code for reg/fifo/mem: FIFO 'Counter or Sampling information' data output register 6
-- extra code for reg/fifo/mem: FIFO 'Configuration CPU access FIFO (CFIFO)' data input register 0
-- extra code for reg/fifo/mem: FIFO 'Configuration CPU access FIFO (CFIFO)' data input register 1
  rwaddr_reg <= wb_addr_i;
-- ACK signal generation. Just pass the LSB of ACK counter.
  wb_ack_o <= ack_sreg(0);
end syn;
