library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;


-- The word, "word" is reserved for encoded data 24 bits
-- The word. "data" is reserved for non-encoded data 12 btis
entity linear_block_decoder_tb is
    end linear_block_decoder_tb;



architecture behavioral of linear_block_decoder_tb is

    signal clk         :   std_logic:= '0';
    signal reset       :   std_logic:= '1';
    signal data_in     :   std_logic_vector(23 downto 0);
    signal decoded_out :   std_logic_vector(11 downto 0):=(others =>'0');
    signal errorDecoded_out: std_logic:= '0';
    constant period : time := 8 ns;    

    component linear_block_decoder 
        port(
                clk:         in  std_logic;
                reset:       in  std_logic;
                data_in:     in   std_logic_vector(23 downto 0);
                decoded_out: out  std_logic_vector(11 downto 0);
                errorDecoded_out:out std_logic
            );
    end component;

begin

    decoder_tb : linear_block_decoder
    port map(
                clk         => clk,
                reset       => reset,
                data_in     => data_in,
                decoded_out => decoded_out,
                errorDecoded_out => errorDecoded_out);

    clk_proc    : process
    begin
        clk <= '0';
        wait for period/2;  --for 0.5 ns signal is '0'.
        clk <= '1';
        wait for period/2;  --for next 0.5 ns
    end process;

    count_proc: process
    begin   
        reset <= '1';      
        data_in <= (others=>'0'); 
        wait for period;
        reset <= '0';
        -- error checks state machine till step 4, three bit error
        data_in <= to_stdlogicvector(x"54524a");
        wait for period*8;
        ------------------------------------------------------------------        
        reset <= '1';      
        data_in <= (others=>'0'); 
        wait for period;
        reset <= '0';
        -- error checks state machine till fail, four bit error
        data_in <= to_stdlogicvector(x"54d24a");
        wait for period*8;
        ---------------------------------------------------------------
        reset <= '1'; 
        data_in <= (others=>'0');      
        wait for period;
        reset <= '0';
        -- error checks state machine till step 1, one bit error
        data_in <= to_stdlogicvector(x"55725e");
        wait for period*8;
        reset <= '1'; 
        data_in <= (others=>'0');      
        wait for period;
        reset <= '0';
        -- error checks state machine till step 1, two bit errors
        data_in <= to_stdlogicvector(x"55f25e");
        wait for period*8;
        reset <= '1';       
        data_in <= (others=>'0');
        wait for period;
        reset <= '0';
        -- error checks state machine till step 1, three bit errors
        data_in <= to_stdlogicvector(x"45f25e");
        wait for period*8;
        reset <= '1';       
        data_in <= (others=>'0');
        wait for period;
        reset <= '0';
        -- error checks state machine till step 2, one error
        data_in <= to_stdlogicvector(x"55527e");
        wait for period*8;
        reset <= '1';
        data_in <= (others=>'0');       
        wait for period;
        reset <= '0';
        -- error checks state machine till step 3, two errors
        data_in <= to_stdlogicvector(x"55537e");
        wait for period*8;
        reset <= '1';
        data_in <= (others=>'0');       
        wait for period;
        reset <= '0';
        -- error checks state machine till step 3, three errors
        data_in <= to_stdlogicvector(x"55517e");
        wait for period*8;
        reset <= '1';
        data_in <= (others=>'0');       
        wait for period;
        reset <= '0';
        -- error checks state machine till step 2, two errors
        data_in <= to_stdlogicvector(x"55127e");
        wait for period*8;
        reset <= '1';
        data_in <= (others=>'0');       
        wait for period;
        reset <= '0';
        -- error checks state machine till step 4, three errors
        data_in <= to_stdlogicvector(x"55107e");
        wait for period*8;
        reset <= '1';
        data_in <= (others=>'0');       
        wait for period;
        reset <= '0';
        -- error checks state machine till step fail, four errors
        data_in <= to_stdlogicvector(x"55907e");
        wait for period*8;



    end process;



end behavioral;
