wrsw_sflow_wb Project Status (03/05/2012 - 11:54:10)
Project File: sflow.xise Parser Errors: No Errors
Module Name: wrsw_sflow_wb Implementation State: Translated
Target Device: xc6vlx130t-1ff1156
  • Errors:
X 2 Errors (2 new)
Product Version:ISE 13.2
  • Warnings:
64 Warnings (64 new)
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
  
 
Device Utilization Summary (estimated values) [-]
Logic UtilizationUsedAvailableUtilization
Number of Slice Registers 110 160000 0%
Number of Slice LUTs 215 80000 0%
Number of fully used LUT-FF pairs 108 217 49%
Number of bonded IOBs 270 600 45%
Number of BUFG/BUFGCTRLs 1 32 3%
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentMo. Mrz 5 13:27:34 2012064 Warnings (64 new)32 Infos (32 new)
Translation ReportCurrentMo. Mrz 5 13:27:41 2012X 2 Errors (2 new)00
Map Report     
Place and Route Report     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated

Date Generated: 03/05/2012 - 13:32:47