Memory map summary
Trigger Unit Registers
HW address | Type | Name | HDL name |
---|---|---|---|
0x00 |
REG |
status |
status |
0x02 |
REG |
control |
control |
0x04 |
REG |
configOffline |
configOffline |
0x08 |
REG |
bValueOffline |
bValueOffline |
0x10 |
REG |
htValueOffline |
htValueOffline |
0x18 |
REG |
wValueOffline |
wValueOffline |
0x20 |
REG |
configOnline |
configOnline |
0x28 |
REG |
bValueOnline |
bValueOnline |
0x30 |
REG |
htValueOnline |
htValueOnline |
0x38 |
REG |
wValueOnline |
wValueOnline |
0x40 |
REG |
syncIDelay |
syncIDelay |
0x42 |
REG |
trigODelay |
trigODelay |
0x50-0x5f |
SUBMAP |
trigdiag |
trigdiag |
0x50 |
REG |
trigdiag.control |
trigdiag_control |
0x52 |
REG |
trigdiag.generation |
trigdiag_generation |
0x54 |
REG |
trigdiag.freq |
trigdiag_freq |
0x58 |
REG |
trigdiag.counter |
trigdiag_counter |
Registers description
status
HDL name |
status |
address |
0x0 |
block offset |
0x0 |
access mode |
ro |
VTU status
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
- |
- |
- |
- |
- |
- |
- |
- |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
missValid |
missReady |
startReady |
running |
wrongBvalue |
wrongHTvalue |
wrongWvalue |
- |
- missValid
-
The start pulse hasn’t been transferred to the VTU because the parameters were not valid. The configOffline.valid bit was set to 0 when the pulse arrived. Changed when the next start pulse is detected.
- missReady
-
The start pulse hasn’t been transferred to the VTU because it wasn’t ready. Either the RF clock was not present, or the start pulse came too early. Changed when the next start pulse is detected.
- startReady
-
Should be 1. Set to 0 when a start pulse has been detected and not yet transfered to the VTU. If stuck to 0, there is no RF clock.
- running
-
VTU core running
- wrongBvalue
-
Wrong B value for the current mode
- wrongHTvalue
-
Wrong HT value for the current mode
- wrongWvalue
-
Wrong W value for the current mode
control
HDL name |
control |
address |
0x2 |
block offset |
0x2 |
access mode |
wo |
Control signals
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
- |
- |
- |
- |
- |
- |
- |
- |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
- |
- |
- |
- |
- |
vtuReset |
stopSoftTrigger |
startSoftTrigger |
- vtuReset
-
Keep VTU and I/O serdes under reset
- stopSoftTrigger
-
Force stop
- startSoftTrigger
-
Force start.
configOffline
HDL name |
configOffline |
address |
0x4 |
block offset |
0x4 |
access mode |
rw |
Control signals
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
- |
- |
- |
- |
- |
- |
- |
- |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
- |
mode[2:0] |
- |
- |
htSwitchingEnable |
valid |
- mode
-
Running mode selector
- htSwitchingEnable
-
Switch between HT and HT+1 values while running
- valid
-
To be set when all offline values are set and coherent. The hardware will use them at the next start. User shouldn’t modify the offline values once this bit is set.
bValueOffline
HDL name |
bValueOffline |
address |
0x8 |
block offset |
0x8 |
access mode |
rw |
Number of RF clock cycles to delay (B)
63 |
62 |
61 |
60 |
59 |
58 |
57 |
56 |
bValueOffline[63:56] |
|||||||
55 |
54 |
53 |
52 |
51 |
50 |
49 |
48 |
bValueOffline[55:48] |
|||||||
47 |
46 |
45 |
44 |
43 |
42 |
41 |
40 |
bValueOffline[47:40] |
|||||||
39 |
38 |
37 |
36 |
35 |
34 |
33 |
32 |
bValueOffline[39:32] |
|||||||
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
bValueOffline[31:24] |
|||||||
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
bValueOffline[23:16] |
|||||||
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
bValueOffline[15:8] |
|||||||
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
bValueOffline[7:0] |
htValueOffline
HDL name |
htValueOffline |
address |
0x10 |
block offset |
0x10 |
access mode |
rw |
Number of RF clock cycles to delay (HT)
63 |
62 |
61 |
60 |
59 |
58 |
57 |
56 |
htValueOffline[63:56] |
|||||||
55 |
54 |
53 |
52 |
51 |
50 |
49 |
48 |
htValueOffline[55:48] |
|||||||
47 |
46 |
45 |
44 |
43 |
42 |
41 |
40 |
htValueOffline[47:40] |
|||||||
39 |
38 |
37 |
36 |
35 |
34 |
33 |
32 |
htValueOffline[39:32] |
|||||||
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
htValueOffline[31:24] |
|||||||
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
htValueOffline[23:16] |
|||||||
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
htValueOffline[15:8] |
|||||||
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
htValueOffline[7:0] |
wValueOffline
HDL name |
wValueOffline |
address |
0x18 |
block offset |
0x18 |
access mode |
rw |
Window value: number of output pulses (W)
63 |
62 |
61 |
60 |
59 |
58 |
57 |
56 |
wValueOffline[63:56] |
|||||||
55 |
54 |
53 |
52 |
51 |
50 |
49 |
48 |
wValueOffline[55:48] |
|||||||
47 |
46 |
45 |
44 |
43 |
42 |
41 |
40 |
wValueOffline[47:40] |
|||||||
39 |
38 |
37 |
36 |
35 |
34 |
33 |
32 |
wValueOffline[39:32] |
|||||||
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
wValueOffline[31:24] |
|||||||
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
wValueOffline[23:16] |
|||||||
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
wValueOffline[15:8] |
|||||||
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
wValueOffline[7:0] |
configOnline
HDL name |
configOnline |
address |
0x20 |
block offset |
0x20 |
access mode |
ro |
Control signals
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
- |
- |
- |
- |
- |
- |
- |
- |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
- |
mode[2:0] |
- |
- |
htSwitchingEnable |
- |
- mode
-
Running mode selector
- htSwitchingEnable
-
Switch between HT and HT+1 values while running
bValueOnline
HDL name |
bValueOnline |
address |
0x28 |
block offset |
0x28 |
access mode |
ro |
Number of RF clock cycles to delay (B)
63 |
62 |
61 |
60 |
59 |
58 |
57 |
56 |
bValueOnline[63:56] |
|||||||
55 |
54 |
53 |
52 |
51 |
50 |
49 |
48 |
bValueOnline[55:48] |
|||||||
47 |
46 |
45 |
44 |
43 |
42 |
41 |
40 |
bValueOnline[47:40] |
|||||||
39 |
38 |
37 |
36 |
35 |
34 |
33 |
32 |
bValueOnline[39:32] |
|||||||
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
bValueOnline[31:24] |
|||||||
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
bValueOnline[23:16] |
|||||||
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
bValueOnline[15:8] |
|||||||
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
bValueOnline[7:0] |
htValueOnline
HDL name |
htValueOnline |
address |
0x30 |
block offset |
0x30 |
access mode |
ro |
Number of RF clock cycles to delay (HT)
63 |
62 |
61 |
60 |
59 |
58 |
57 |
56 |
htValueOnline[63:56] |
|||||||
55 |
54 |
53 |
52 |
51 |
50 |
49 |
48 |
htValueOnline[55:48] |
|||||||
47 |
46 |
45 |
44 |
43 |
42 |
41 |
40 |
htValueOnline[47:40] |
|||||||
39 |
38 |
37 |
36 |
35 |
34 |
33 |
32 |
htValueOnline[39:32] |
|||||||
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
htValueOnline[31:24] |
|||||||
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
htValueOnline[23:16] |
|||||||
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
htValueOnline[15:8] |
|||||||
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
htValueOnline[7:0] |
wValueOnline
HDL name |
wValueOnline |
address |
0x38 |
block offset |
0x38 |
access mode |
ro |
Window value: number of output pulses (W)
63 |
62 |
61 |
60 |
59 |
58 |
57 |
56 |
wValueOnline[63:56] |
|||||||
55 |
54 |
53 |
52 |
51 |
50 |
49 |
48 |
wValueOnline[55:48] |
|||||||
47 |
46 |
45 |
44 |
43 |
42 |
41 |
40 |
wValueOnline[47:40] |
|||||||
39 |
38 |
37 |
36 |
35 |
34 |
33 |
32 |
wValueOnline[39:32] |
|||||||
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
wValueOnline[31:24] |
|||||||
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
wValueOnline[23:16] |
|||||||
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
wValueOnline[15:8] |
|||||||
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
wValueOnline[7:0] |
syncIDelay
HDL name |
syncIDelay |
address |
0x40 |
block offset |
0x40 |
access mode |
rw |
Delay on the sync input
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
- |
- |
- |
- |
- |
- |
- |
- |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
- |
- |
- |
delay[4:0] |
- delay
-
value
trigODelay
HDL name |
trigODelay |
address |
0x42 |
block offset |
0x42 |
access mode |
rw |
Delay on the trigger output
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
- |
- |
- |
- |
- |
- |
- |
- |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
- |
- |
- |
delay[4:0] |
- delay
-
value
trigdiag.control
HDL name |
trigdiag_control |
address |
0x50 |
block offset |
0x0 |
access mode |
rw |
Control register
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
- |
- |
- |
- |
- |
- |
- |
- |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
- |
- |
- |
- |
- |
- |
window[1:0] |
- window
-
Select the window to measure the frequency. A change to this value is taken into account at the end of the current window. 00: 500us; 01: 50ms; 10: 5s; 11: 20s
trigdiag.generation
HDL name |
trigdiag_generation |
address |
0x52 |
block offset |
0x2 |
access mode |
ro |
Result number
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
generation[15:8] |
|||||||
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
generation[7:0] |
trigdiag.freq
HDL name |
trigdiag_freq |
address |
0x54 |
block offset |
0x4 |
access mode |
ro |
Frequency
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
freq[31:24] |
|||||||
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
freq[23:16] |
|||||||
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
freq[15:8] |
|||||||
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
freq[7:0] |
trigdiag.counter
HDL name |
trigdiag_counter |
address |
0x58 |
block offset |
0x8 |
access mode |
ro |
Pulse counter
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
counter[31:24] |
|||||||
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
counter[23:16] |
|||||||
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
counter[15:8] |
|||||||
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
counter[7:0] |