Sequence to initialise the board
-
FPGA boot (automatic)
- Setup FPGA clock - DMTD clock should be present at FPGA boot
- Initialise SPI
- Check presence of PLL LTC6950
- Program the PLL LTC6950
- Wait for stable clock
- Switch FPGA clocks using BUFGMUX select
-
Disable outputs
- Clock 10 MHz
- PPS out
- RF 1 + 2 out
- Triggers T1, T2 (*2)
- CLK1, CLK2
- IO[1:4]
- xxx
-
Initialise delay control cells, for each IO bank:
- Perform IDELAYCONTROL calibration, until RDY is asserted by the IDELAYCONTROL
- Program each of the IDELAY and ODELAY cells with their associated value. In nearly all cases these will be determined by calibration during board bring-up.
-
Initialise AD9910 (DDS providing the Local Oscillator input to the Mixer)
- Program fixed frequency mode 223.5 MHz
- Initialise mode of operation to provide precise sync'ing by the FPGA
-
Initialise AD9783 DACs which provides an IQ Intermediate Frequency to the Mixer.
- Optimise the parallel port timing. IQ data from FPGA is registered by the AD9783. Use calibration sequence to determine delays for SET, HLD and SMP delay lines
- build timing data array to determine best positioning of SEEK and the values for SMP, SET and HLD.
-
WRC Initialisation
- Should not start before FPGA clock is setup ?
- dac ctrl (dmtd, ocxo)
- WR link
- wait until sync