Past due
Milestone
expired on Feb 12, 2021
Layout V2
Unstarted Issues (open and unassigned)
1
Ongoing Issues (open and assigned)
0
Completed Issues (closed)
15
- RF signal, distributed to trigger unit flip flops looks awful
- Unconnected 5V power rail
- Front panel cannot be fitted
- Front-panel design and fabrication
- OCXO sense goes to FPGA digital input
- EXT REF I/O: PPS / 10M mux direction line needs opposite polarity
- SFP LEDs are on when FPGA is not programmed
- Cross check PCB labelling with front panel for the SFP indexing
- V2: change EP195 delay line to SY89295UMG
- Change electrolytic caps to more reliable series
- Front panel: J9 very close to the front panel handle
- Front panel middle fastening not aligned with PCB
- The PCB labelling of the SFP connectors is inconsistent with front panel labelling
- WRC eeprom are too small
- Change license to CERN-OHL-W