IQ DAC timing
Sometimes - the firmware to configure and set the HLD, SMP and SET delays for the IQ DACs data to clock timing relationship fails. To be investigated whether all cards behave the same. Certainly, it seems to work for IQDAC 1 on the board tested but not IQDAC 2...
dac 2: smp set hld seek
0 11 13 1
1 14 10 1
2 15 8 1
3 15 6 1
4 15 4 1
5 15 2 1
6 1 15 0
7 3 15 0
8 6 15 0
9 8 15 0
10 9 15 0
11 12 15 0
12 14 14 0
13 15 12 0
14 15 10 0
15 15 7 0
16 15 6 0
17 15 3 0
18 15 2 0
19 1 15 1
20 3 15 1
21 6 15 1
22 8 15 1
23 10 14 1
24 12 12 1
25 14 9 1
26 15 8 1
27 15 6 1
28 15 4 1
29 15 4 1
30 15 5 1
31 15 4 1
dac 2: no 1-to-0 transition