Commit de08f586 authored by John Robert Gill's avatar John Robert Gill

Added software to read rfframe timestamps and updated version.

parent 3fe0ae97
......@@ -343,7 +343,7 @@ unsigned libwr2rf_read_fwversion(struct libwr2rf_dev *dev)
int libwr2rf_check_fwversion(struct libwr2rf_dev *dev)
{
return !(libwr2rf_read_fwversion(dev) == 0x00001200);
return !(libwr2rf_read_fwversion(dev) == 0x00001300);
}
void libwr2rf_read_nco_ipinfo(struct libwr2rf_dev *dev,
......@@ -1391,3 +1391,46 @@ libwr2rf_set_nco_reset_ignore (struct libwr2rf_dev *dev, unsigned ignore)
libwr2rf_write16(dev, ncoctrl_addr, ncoctrl);
}
int
libwr2rf_rfframerx_ts(struct libwr2rf_dev *dev, unsigned ts_nco_reset, uint64_t *ts_tai, uint32_t *ts_cycles)
{
uint64_t tai = 0;
uint32_t cyc = 0;
unsigned update_addr = WR2RF_VME_REGS_INIT + WR2RF_INIT_REGS_WRS_RXFRAME_RFFRAME_TS;
unsigned tai_addr = WR2RF_VME_REGS_INIT;
unsigned cyc_addr = WR2RF_VME_REGS_INIT;
switch (ts_nco_reset) {
case LIBWR2RF_RFFRAME_TS:
tai_addr += WR2RF_INIT_REGS_WRS_RXFRAME_TAI;
cyc_addr += WR2RF_INIT_REGS_WRS_RXFRAME_CYCLES;
break;
case LIBWR2RF_RFFRAME_TS_NCO_RESET:
tai_addr += WR2RF_INIT_REGS_WRS_RXFRAME_NCO_RESET_TAI;
cyc_addr += WR2RF_INIT_REGS_WRS_RXFRAME_NCO_RESET_CYCLES;
break;
default:
return LIBWR2RF_ERROR_BAD_PARAM;
}
// Update the timestamps for reading
libwr2rf_write16(dev, update_addr, WR2RF_INIT_REGS_WRS_RXFRAME_RFFRAME_TS_UPDATE);
tai = (((uint64_t)libwr2rf_read16(dev, tai_addr + 2)) << 32) |
(((uint64_t)libwr2rf_read16(dev, tai_addr + 4)) << 16) |
(((uint64_t)libwr2rf_read16(dev, tai_addr + 6)) << 0);
cyc = (((uint64_t)libwr2rf_read16(dev, cyc_addr + 2)) << 32) |
(((uint64_t)libwr2rf_read16(dev, cyc_addr + 4)) << 16) |
(((uint64_t)libwr2rf_read16(dev, cyc_addr + 6)) << 0);
/* printf("tai %02x %02x %02x %02x %04x %04x\n", libwr2rf_read16(dev, tai_addr + 0), */
/* libwr2rf_read16(dev, tai_addr + 2), libwr2rf_read16(dev, tai_addr + 4), */
/* libwr2rf_read16(dev, tai_addr + 6), tai_addr, update_addr); */
/* printf("cyc %02x %02x %02x %02x %04x %04x\n", libwr2rf_read16(dev, cyc_addr + 0), */
/* libwr2rf_read16(dev, tai_addr + 2), libwr2rf_read16(dev, tai_addr + 4), */
/* libwr2rf_read16(dev, tai_addr + 6), cyc_addr, update_addr); */
*ts_tai = tai;
*ts_cycles = cyc;
return 0;
}
......@@ -98,7 +98,7 @@ libwr2rf_host_init_by_slot_verbose (unsigned int slot, int verbose)
/* MAP A24.
By convention, the base address is SLOT * 1MB. */
return setup_map (0x39, slot << 20, ~((512 << 10) - 1), verbose);
return setup_map (0x39, slot << 19, ~((512 << 10) - 1), verbose);
}
struct libwr2rf_dev *
......
......@@ -163,7 +163,7 @@ libwr2rf_nco_wrcfg (struct libwr2rf_dev *dev, unsigned ch)
libwr2rf_16x32_write64(dev, base + RFNCO_FTW_LO0, LO0);
libwr2rf_16x32_write64(dev, base + RFNCO_FTW_LO1, LO1);
libwr2rf_16x32_write32(dev, base + RFNCO_FTW_H, harmonic);
libwr2rf_16x32_write32(dev, base + RFNCO_INPUTS_H, harmonic);
libwr2rf_16x32_write32(dev, base + RFNCO_CONTROL, control);
return 0;
......
......@@ -273,4 +273,13 @@ unsigned libwr2rf_get_wrs_timeout_latency (struct libwr2rf_dev *dev);
/* Ignore NCO reset from WR if IGNORE is set. */
void libwr2rf_set_nco_reset_ignore (struct libwr2rf_dev *dev, unsigned ignore);
#define LIBWR2RF_RFFRAME_TS 0
#define LIBWR2RF_RFFRAME_TS_NCO_RESET 1
/* Read the timestamp that is recorded for each incoming RF frame. If ts_nco_reset=1,
then the timestamp will reflect the last RF frame. TAI reflects the number of seconds
that have elapsed in the current TAI epoch and cycles is the number of WR clock cycles
(16 ns) that have elapsed within the current second. */
int libwr2rf_rfframerx_ts (struct libwr2rf_dev *dev, unsigned ts_nco_reset, uint64_t *ts_tai, uint32_t *ts_cycles);
#endif /* __LIBWR2RF__API__H_ */
......@@ -593,11 +593,11 @@ nco_lcfg (struct libwr2rf_dev *dev, int argc, char **argv)
unsigned harmonic = 4620;
unsigned control = RFNCO_CONTROL_SOFTLOAD;
unsigned nco_ftw_addr = RFNCO_FTW_H1;
unsigned nco_harmonic_addr = RFNCO_FTW_H;
unsigned nco_harmonic_addr = RFNCO_INPUTS_H;
unsigned nco_LO0_addr = RFNCO_FTW_LO0;
unsigned nco_LO1_addr = RFNCO_FTW_LO1;
unsigned nco_ftw_on_addr = RFNCO_FTW_ON;
unsigned nco_ftw_offsetfsk_addr = RFNCO_FTW_OFFSETFSK;
unsigned nco_ftw_offsetfsk_addr = RFNCO_INPUTS_OFFSETFSK;
unsigned nco_ftw_slip_addr = RFNCO_FTW_SLIP;
unsigned nco_control_addr = RFNCO_CONTROL;
......@@ -705,11 +705,11 @@ nco_wrcfg (struct libwr2rf_dev *dev, int argc, char **argv)
unsigned harmonic = 4620;
unsigned control = RFNCO_CONTROL_SELFTWH1 | RFNCO_CONTROL_EXTRESETENABLE | RFNCO_CONTROL_SELLOAD |
RFNCO_CONTROL_SELWRFTWH1;
unsigned nco_harmonic_addr = RFNCO_FTW_H;
unsigned nco_harmonic_addr = RFNCO_INPUTS_H;
unsigned nco_LO0_addr = RFNCO_FTW_LO0;
unsigned nco_LO1_addr = RFNCO_FTW_LO1;
unsigned nco_ftw_on_addr = RFNCO_FTW_ON;
unsigned nco_ftw_offsetfsk_addr = RFNCO_FTW_OFFSETFSK;
unsigned nco_ftw_offsetfsk_addr = RFNCO_INPUTS_OFFSETFSK;
unsigned nco_ftw_slip_addr = RFNCO_FTW_SLIP;
unsigned nco_control_addr = RFNCO_CONTROL;
......@@ -764,13 +764,13 @@ nco_status (struct libwr2rf_dev *dev, int argc, char **argv)
{
unsigned off = WR2RF_VME_REGS_CTRL;
unsigned nco_ftw_addr = RFNCO_FTW;
unsigned nco_harmonic_addr = RFNCO_FTW_H;
unsigned nco_harmonic_addr = RFNCO_INPUTS_H;
unsigned nco_phaseh1_addr = RFNCO_PHASES_H1;
unsigned nco_phaseh1main_addr = RFNCO_PHASES_H1MAIN;
unsigned nco_phaseif0_addr = RFNCO_PHASES_IF0;
unsigned nco_phaseif1_addr = RFNCO_PHASES_IF1;
unsigned nco_ftw_on_addr = RFNCO_FTW_ON;
unsigned nco_ftw_offsetfsk_addr = RFNCO_FTW_OFFSETFSK;
unsigned nco_ftw_offsetfsk_addr = RFNCO_INPUTS_OFFSETFSK;
unsigned nco_ftw_slip_addr = RFNCO_FTW_SLIP;
unsigned nco_ftw_lo0_addr = RFNCO_FTW_LO0;
unsigned nco_ftw_lo1_addr = RFNCO_FTW_LO1;
......@@ -864,7 +864,7 @@ nco_status (struct libwr2rf_dev *dev, int argc, char **argv)
static void
nco_cablecomp (struct libwr2rf_dev *dev, int argc, char **argv)
{
unsigned cablecomp_addr = RFNCO_DELAYCOMP;
unsigned cablecomp_addr = RFNCO_INPUTS_DELAYCOMP;
unsigned cablecomp = 0;
unsigned off;
......@@ -3853,10 +3853,8 @@ api_rfnco_read32 (struct libwr2rf_dev *dev, int argc, char **argv)
if (addr_off >= max_off)
goto usage;
if (libwr2rf_rfnco_read32 (dev, rfnco_idx, addr_off) != 0) {
printf ("ERROR\n");
return;
}
printf ("addr=%03x val=%08x \n", addr_off, libwr2rf_rfnco_read32 (dev, rfnco_idx, addr_off));
return;
usage:
......@@ -3975,6 +3973,30 @@ usage:
printf (" fdelay in 0..15; odelay in 0..31\n");
}
static void
api_rfframerx_ts (struct libwr2rf_dev *dev, int argc, char **argv)
{
uint64_t tai = 0;
uint32_t cycles = 0;
if (argc != 2)
goto usage;
unsigned ts_nco_reset = strtoul(argv[1], NULL, 0);
if (ts_nco_reset != 0 && ts_nco_reset != 1)
goto usage;
if (libwr2rf_rfframerx_ts(dev, ts_nco_reset, &tai, &cycles))
printf ("ERROR\n");
printf("Timestamp %s: 0x%012lx 0x%08x\n", ts_nco_reset == 1 ? "nco_reset rfframe" : "last frame", tai, cycles);
return;
usage:
printf ("Usage: %s [0|1], where 1 indicates the rx'd frame must contain nco_reset\n", argv[0]);
}
static void
api_tmgclk (struct libwr2rf_dev *dev, int argc, char **argv)
......@@ -4096,6 +4118,7 @@ static struct cmds cmds[] =
{ "reconfigure", reconfigure, "reset the fpga" },
{ "api-init", api_init, "init the board"},
{ "api-dds-ioupdate-delay", api_dds_ioupdate_delay, "Sets the delay from the FPGA for the dds ioupdate signal" },
{ "api-rfframerx-ts", api_rfframerx_ts, "Displays the timestamp for received RF frames" },
{ "api-vtu-start-lemo", api_vtu_start_lemo, "select start lemo for a vtu"},
{ "api-vtu-stop-lemo", api_vtu_stop_lemo, "select stop lemo for a vtu"},
{ "api-vtu-output-ff-delay", api_vtu_output_ff_delay, "set vtu output delay chip value"},
......
#!/bin/bash
slot=$1
chan=$2
#ftw_LO0
./wr2rf -s $slot api-rfnco-write32 $chan 0x98 0x5E300000
./wr2rf -s $slot api-rfnco-write32 $chan 0x9c 0x0001C9BA
#ftw_LO1
./wr2rf -s $slot api-rfnco-write32 $chan 0xa0 0x5E300000
./wr2rf -s $slot api-rfnco-write32 $chan 0xa4 0x0001C9BA
#ftw_h1
./wr2rf -s $slot api-rfnco-write32 $chan 0x80 0x87012C85
./wr2rf -s $slot api-rfnco-write32 $chan 0x84 0x00000016
#ftw_h1_on
./wr2rf -s $slot api-rfnco-write32 $chan 0x90 0xB8BD9D1F
./wr2rf -s $slot api-rfnco-write32 $chan 0x94 0x00000016
#offset h1
./wr2rf -s $slot api-rfnco-write32 $chan 0x100 0x0
#rate
./wr2rf -s $slot api-rfnco-write32 $chan 0x108 0x1
#harmonic
./wr2rf -s $slot api-rfnco-write32 $chan 0x10c 4620
#offset fsk
./wr2rf -s $slot api-rfnco-write32 $chan 0x110 0x0
#slip
./wr2rf -s $slot api-rfnco-write32 $chan 0xa8 0x0
#enable fsk and external reset
./wr2rf -s $slot api-rfnco-write32 $chan 0x20 0x104000
#softload
./wr2rf -s $slot api-rfnco-write32 $chan 0x20 0x104002
#!/bin/bash
slot=$1
chan=$2
#ftw_LO0
./wr2rf -s $slot api-rfnco-write32 $chan 0x98 0x5E300000
./wr2rf -s $slot api-rfnco-write32 $chan 0x9c 0x0001C9BA
#ftw_LO1
./wr2rf -s $slot api-rfnco-write32 $chan 0xa0 0x5E300000
./wr2rf -s $slot api-rfnco-write32 $chan 0xa4 0x0001C9BA
#ftw_h1
./wr2rf -s $slot api-rfnco-write32 $chan 0x80 0xB24A8FB7
./wr2rf -s $slot api-rfnco-write32 $chan 0x84 0x00000016
#offset h1
./wr2rf -s $slot api-rfnco-write32 $chan 0x100 0x0
#harmonic
./wr2rf -s $slot api-rfnco-write32 $chan 0x10c 4620
#control
./wr2rf -s $slot api-rfnco-write32 $chan 0x20 0x2
#!/bin/bash
slot=$1
chan=$2
#ftw_LO0
./wr2rf -s $slot api-rfnco-write32 $chan 0x98 0x5E300000
./wr2rf -s $slot api-rfnco-write32 $chan 0x9c 0x0001C9BA
#ftw_LO1
./wr2rf -s $slot api-rfnco-write32 $chan 0xa0 0x5E300000
./wr2rf -s $slot api-rfnco-write32 $chan 0xa4 0x0001C9BA
#ftw_h1
./wr2rf -s $slot api-rfnco-write32 $chan 0x80 0x438C6CE8
./wr2rf -s $slot api-rfnco-write32 $chan 0x84 0x00000017
#offset h1
./wr2rf -s $slot api-rfnco-write32 $chan 0x100 0x0
#harmonic
./wr2rf -s $slot api-rfnco-write32 $chan 0x10c 4620
#softload
./wr2rf -s $slot api-rfnco-write32 $chan 0x20 0x2
#!/bin/bash
slot=$1
chan=$2
#ftw_LO0
./wr2rf -s $slot api-rfnco-write32 $chan 0x98 0x5E300000
./wr2rf -s $slot api-rfnco-write32 $chan 0x9c 0x0001C9BA
#ftw_LO1
./wr2rf -s $slot api-rfnco-write32 $chan 0xa0 0x5E300000
./wr2rf -s $slot api-rfnco-write32 $chan 0xa4 0x0001C9BA
#ftw_h1
./wr2rf -s $slot api-rfnco-write32 $chan 0x80 0xC8BD9D1F
./wr2rf -s $slot api-rfnco-write32 $chan 0x84 0x00000016
#ftw_h1_on
./wr2rf -s $slot api-rfnco-write32 $chan 0x90 0xB8BD9D1F
./wr2rf -s $slot api-rfnco-write32 $chan 0x94 0x00000016
#offset h1
./wr2rf -s $slot api-rfnco-write32 $chan 0x100 0x0
#rate
./wr2rf -s $slot api-rfnco-write32 $chan 0x108 0x1
#harmonic
./wr2rf -s $slot api-rfnco-write32 $chan 0x10c 4620
#offset fsk
./wr2rf -s $slot api-rfnco-write32 $chan 0x110 0x0
#slip
./wr2rf -s $slot api-rfnco-write32 $chan 0xa8 0x0
#enable fsk and external reset
./wr2rf -s $slot api-rfnco-write32 $chan 0x20 0x104000
#softload
./wr2rf -s $slot api-rfnco-write32 $chan 0x20 0x104002
......@@ -9,7 +9,7 @@ slot=$1
./wr2rf -s $slot pll-init
# Dynamically load wrpc-sw to start the WR link
#./wr2rf -s $slot fw-load /user/jgill/wrc-wr2rf-enabled-snmp-and-auxdiags.bin
./wr2rf -s $slot fw-load /user/jgill/wrc-wr2rf-enabled-snmp-and-auxdiags.bin
# sleep until wrpc has started
sleep 1
......
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