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wr2rf-vme
Commits
ca8834f2
Commit
ca8834f2
authored
May 22, 2020
by
Tristan Gingold
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Plain Diff
Add registers to control mmcm shift.
parent
4da46223
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Showing
5 changed files
with
107 additions
and
13 deletions
+107
-13
wr2rf_core.vhd
hdl/rtl/wr2rf_core.vhd
+9
-0
wr2rf_init_regs.cheby
hdl/rtl/wr2rf_init_regs.cheby
+17
-0
wr2rf_sysclks.vhd
hdl/rtl/wr2rf_sysclks.vhd
+26
-5
wr2rf_vme_regs.vhd
hdl/rtl/wr2rf_vme_regs.vhd
+44
-8
wr2rf_vme.vhd
hdl/top/wr2rf_vme.vhd
+11
-0
No files found.
hdl/rtl/wr2rf_core.vhd
View file @
ca8834f2
...
@@ -52,6 +52,10 @@ entity wr2rf_core is
...
@@ -52,6 +52,10 @@ entity wr2rf_core is
clk_sel_o
:
out
std_logic
;
clk_sel_o
:
out
std_logic
;
clk_sys_reset_o
:
out
std_logic
;
clk_sys_reset_o
:
out
std_logic
;
mmcm_shift_incdec_o
:
out
std_logic
;
mmcm_shift_en_o
:
out
std_logic
;
mmcm_shift_busy_i
:
in
std_logic
;
tmg_clk_term_en_o
:
out
std_logic_vector
(
2
downto
1
);
tmg_clk_term_en_o
:
out
std_logic_vector
(
2
downto
1
);
tmg_io_term_en_o
:
out
std_logic_vector
(
4
downto
1
);
tmg_io_term_en_o
:
out
std_logic_vector
(
4
downto
1
);
tmg_clk_oe_o
:
out
std_logic_vector
(
1
downto
0
);
tmg_clk_oe_o
:
out
std_logic_vector
(
1
downto
0
);
...
@@ -132,6 +136,11 @@ begin
...
@@ -132,6 +136,11 @@ begin
init_clock_status_mmcm_locked_i
=>
mmcm_locked_i
,
init_clock_status_mmcm_locked_i
=>
mmcm_locked_i
,
init_clock_ctrl_clk_sel_o
=>
clk_sel_o
,
init_clock_ctrl_clk_sel_o
=>
clk_sel_o
,
init_clock_ctrl_mmcm_reset_o
=>
clk_sys_reset_o
,
init_clock_ctrl_mmcm_reset_o
=>
clk_sys_reset_o
,
init_mmcm_shift_incdec_o
=>
mmcm_shift_incdec_o
,
init_mmcm_shift_wr_o
=>
mmcm_shift_en_o
,
init_clock_status_shift_busy_i
=>
mmcm_shift_busy_i
,
init_tmg_io_term_o
=>
tmg_io_term_en_o
,
init_tmg_io_term_o
=>
tmg_io_term_en_o
,
init_tmg_clk_term_o
=>
tmg_clk_term_en_o
,
init_tmg_clk_term_o
=>
tmg_clk_term_en_o
,
init_tmg_clk_oe_o
=>
tmg_clk_oe_o
,
init_tmg_clk_oe_o
=>
tmg_clk_oe_o
,
...
...
hdl/rtl/wr2rf_init_regs.cheby
View file @
ca8834f2
...
@@ -18,6 +18,19 @@ memory-map:
...
@@ -18,6 +18,19 @@ memory-map:
description: Reset the system pll
description: Reset the system pll
range: 1
range: 1
preset: 1
preset: 1
- reg:
name: mmcm_shift
description: Adjust the mmcm shift for the 10Mhz external clock
access: wo
width: 16
x-hdl:
write-strobe: True
children:
- field:
name: incdec
description: Adjust the mmcm shift
comment: "1: increase, 0: descrease. Step: TBD"
range: 0
- reg:
- reg:
name: clock_status
name: clock_status
description: Status register for system clock
description: Status register for system clock
...
@@ -28,6 +41,10 @@ memory-map:
...
@@ -28,6 +41,10 @@ memory-map:
name: mmcm_locked
name: mmcm_locked
description: lock status of the mmcm
description: lock status of the mmcm
range: 0
range: 0
- field:
name: shift_busy
description: Shift adjustment in progress
range: 1
- reg:
- reg:
name: tmg
name: tmg
description: timing io grouping of signals
description: timing io grouping of signals
...
...
hdl/rtl/wr2rf_sysclks.vhd
View file @
ca8834f2
...
@@ -34,6 +34,10 @@ entity wr2rf_sysclks is
...
@@ -34,6 +34,10 @@ entity wr2rf_sysclks is
clk_sys_i
:
in
std_logic
;
clk_sys_i
:
in
std_logic
;
reset_i
:
in
std_logic
;
reset_i
:
in
std_logic
;
mmcm_shift_incdec_i
:
in
std_logic
;
mmcm_shift_en_i
:
in
std_logic
;
mmcm_shift_busy_o
:
out
std_logic
;
locked_o
:
out
std_logic
;
locked_o
:
out
std_logic
;
clk62m5_o
:
out
std_logic
;
clk62m5_o
:
out
std_logic
;
...
@@ -86,6 +90,8 @@ architecture rtl of wr2rf_sysclks is
...
@@ -86,6 +90,8 @@ architecture rtl of wr2rf_sysclks is
signal
rsts_n
:
std_logic_vector
(
3
downto
0
);
signal
rsts_n
:
std_logic_vector
(
3
downto
0
);
signal
locked
:
std_logic
;
signal
locked
:
std_logic
;
signal
mmcm_shift_done
:
std_logic
;
attribute
keep_hierarchy
:
STRING
;
attribute
keep_hierarchy
:
STRING
;
attribute
keep_hierarchy
of
inst_aasd
:
label
is
"yes"
;
attribute
keep_hierarchy
of
inst_aasd
:
label
is
"yes"
;
...
@@ -120,7 +126,7 @@ begin
...
@@ -120,7 +126,7 @@ begin
CLKOUT4_DIVIDE
=>
100
,
CLKOUT4_DIVIDE
=>
100
,
CLKOUT4_PHASE
=>
-135
.
000
,
CLKOUT4_PHASE
=>
-135
.
000
,
CLKOUT4_DUTY_CYCLE
=>
0
.
500
,
CLKOUT4_DUTY_CYCLE
=>
0
.
500
,
CLKOUT4_USE_FINE_PS
=>
FALSE
,
CLKOUT4_USE_FINE_PS
=>
True
,
CLKIN1_PERIOD
=>
16
.
000
)
CLKIN1_PERIOD
=>
16
.
000
)
port
map
(
-- Output clocks
port
map
(
-- Output clocks
CLKFBOUT
=>
clkfbout
,
CLKFBOUT
=>
clkfbout
,
...
@@ -151,10 +157,10 @@ begin
...
@@ -151,10 +157,10 @@ begin
DRDY
=>
drdy_unused
,
DRDY
=>
drdy_unused
,
DWE
=>
'0'
,
DWE
=>
'0'
,
-- Ports for dynamic phase shift
-- Ports for dynamic phase shift
PSCLK
=>
'0'
,
PSCLK
=>
clk_sys_i
,
PSEN
=>
'0'
,
PSEN
=>
mmcm_shift_en_i
,
PSINCDEC
=>
'0'
,
PSINCDEC
=>
mmcm_shift_incdec_i
,
PSDONE
=>
psdone_unused
,
PSDONE
=>
mmcm_shift_done
,
-- Other control and status signals
-- Other control and status signals
LOCKED
=>
locked
,
LOCKED
=>
locked
,
CLKINSTOPPED
=>
clkinstopped_unused
,
CLKINSTOPPED
=>
clkinstopped_unused
,
...
@@ -162,6 +168,21 @@ begin
...
@@ -162,6 +168,21 @@ begin
PWRDWN
=>
'0'
,
PWRDWN
=>
'0'
,
RST
=>
reset_i
);
RST
=>
reset_i
);
process
(
clk_sys_i
)
begin
if
rising_edge
(
clk_sys_i
)
then
if
reset_i
=
'1'
then
mmcm_shift_busy_o
<=
'0'
;
else
if
mmcm_shift_en_i
=
'1'
then
mmcm_shift_busy_o
<=
'1'
;
elsif
mmcm_shift_done
=
'1'
then
mmcm_shift_busy_o
<=
'0'
;
end
if
;
end
if
;
end
if
;
end
process
;
clkf_buf
:
BUFG
clkf_buf
:
BUFG
port
map
(
port
map
(
I
=>
clkfbout
,
I
=>
clkfbout
,
...
...
hdl/rtl/wr2rf_vme_regs.vhd
View file @
ca8834f2
-- Do not edit. Generated on
Wed May 20 15:05:48
2020 by tgingold
-- Do not edit. Generated on
Fri May 22 12:11:59
2020 by tgingold
-- With Cheby 1.4.dev0 and these options:
-- With Cheby 1.4.dev0 and these options:
-- -i wr2rf_vme_regs.cheby --gen-hdl wr2rf_vme_regs.vhd
-- -i wr2rf_vme_regs.cheby --gen-hdl wr2rf_vme_regs.vhd
...
@@ -35,9 +35,16 @@ entity wr2rf_vme_regs is
...
@@ -35,9 +35,16 @@ entity wr2rf_vme_regs is
-- Reset the system pll
-- Reset the system pll
init_clock_ctrl_mmcm_reset_o
:
out
std_logic
;
init_clock_ctrl_mmcm_reset_o
:
out
std_logic
;
-- Adjust the mmcm shift for the 10Mhz external clock
-- 1: increase, 0: descrease. Step: TBD
init_mmcm_shift_incdec_o
:
out
std_logic
;
init_mmcm_shift_wr_o
:
out
std_logic
;
-- Status register for system clock
-- Status register for system clock
-- lock status of the mmcm
-- lock status of the mmcm
init_clock_status_mmcm_locked_i
:
in
std_logic
;
init_clock_status_mmcm_locked_i
:
in
std_logic
;
-- Shift adjustment in progress
init_clock_status_shift_busy_i
:
in
std_logic
;
-- timing io grouping of signals
-- timing io grouping of signals
-- terminations for UBT
-- terminations for UBT
...
@@ -113,6 +120,9 @@ architecture syn of wr2rf_vme_regs is
...
@@ -113,6 +120,9 @@ architecture syn of wr2rf_vme_regs is
signal
init_clock_ctrl_mmcm_reset_reg
:
std_logic
;
signal
init_clock_ctrl_mmcm_reset_reg
:
std_logic
;
signal
init_clock_ctrl_wreq
:
std_logic
;
signal
init_clock_ctrl_wreq
:
std_logic
;
signal
init_clock_ctrl_wack
:
std_logic
;
signal
init_clock_ctrl_wack
:
std_logic
;
signal
init_mmcm_shift_incdec_reg
:
std_logic
;
signal
init_mmcm_shift_wreq
:
std_logic
;
signal
init_mmcm_shift_wack
:
std_logic
;
signal
init_tmg_io_term_reg
:
std_logic_vector
(
3
downto
0
);
signal
init_tmg_io_term_reg
:
std_logic_vector
(
3
downto
0
);
signal
init_tmg_clk_term_reg
:
std_logic_vector
(
1
downto
0
);
signal
init_tmg_clk_term_reg
:
std_logic_vector
(
1
downto
0
);
signal
init_tmg_clk_oe_reg
:
std_logic_vector
(
1
downto
0
);
signal
init_tmg_clk_oe_reg
:
std_logic_vector
(
1
downto
0
);
...
@@ -309,6 +319,23 @@ begin
...
@@ -309,6 +319,23 @@ begin
end
if
;
end
if
;
end
process
;
end
process
;
-- Register init_mmcm_shift
init_mmcm_shift_incdec_o
<=
init_mmcm_shift_incdec_reg
;
process
(
clk_i
)
begin
if
rising_edge
(
clk_i
)
then
if
rst_n_i
=
'0'
then
init_mmcm_shift_incdec_reg
<=
'0'
;
init_mmcm_shift_wack
<=
'0'
;
else
if
init_mmcm_shift_wreq
=
'1'
then
init_mmcm_shift_incdec_reg
<=
wr_dat_d0
(
0
);
end
if
;
init_mmcm_shift_wack
<=
init_mmcm_shift_wreq
;
end
if
;
end
if
;
end
process
;
init_mmcm_shift_wr_o
<=
init_mmcm_shift_wack
;
-- Register init_clock_status
-- Register init_clock_status
-- Register init_tmg
-- Register init_tmg
...
@@ -463,12 +490,13 @@ begin
...
@@ -463,12 +490,13 @@ begin
init_wrpc_o
.
dat
(
15
downto
0
)
<=
wr_dat_d0
;
init_wrpc_o
.
dat
(
15
downto
0
)
<=
wr_dat_d0
;
-- Process for write requests.
-- Process for write requests.
process
(
wr_adr_d0
,
wr_req_d0
,
ctrl_rf1_vtus_wack
,
ctrl_rf2_vtus_wack
,
ctrl_reg1_wack
,
ctrl_reg2_wack
,
init_clock_ctrl_wack
,
init_tmg_wack
,
init_pin_ctrl_wack
,
init_pll_spi_wack
,
init_rf_spi_wack
,
init_fw_update_wack
,
init_rf_wack
,
init_wrpc_wack
)
begin
process
(
wr_adr_d0
,
wr_req_d0
,
ctrl_rf1_vtus_wack
,
ctrl_rf2_vtus_wack
,
ctrl_reg1_wack
,
ctrl_reg2_wack
,
init_clock_ctrl_wack
,
init_
mmcm_shift_wack
,
init_
tmg_wack
,
init_pin_ctrl_wack
,
init_pll_spi_wack
,
init_rf_spi_wack
,
init_fw_update_wack
,
init_rf_wack
,
init_wrpc_wack
)
begin
ctrl_rf1_vtus_we
<=
'0'
;
ctrl_rf1_vtus_we
<=
'0'
;
ctrl_rf2_vtus_we
<=
'0'
;
ctrl_rf2_vtus_we
<=
'0'
;
ctrl_reg1_wreq
<=
'0'
;
ctrl_reg1_wreq
<=
'0'
;
ctrl_reg2_wreq
<=
'0'
;
ctrl_reg2_wreq
<=
'0'
;
init_clock_ctrl_wreq
<=
'0'
;
init_clock_ctrl_wreq
<=
'0'
;
init_mmcm_shift_wreq
<=
'0'
;
init_tmg_wreq
<=
'0'
;
init_tmg_wreq
<=
'0'
;
init_pin_ctrl_wreq
<=
'0'
;
init_pin_ctrl_wreq
<=
'0'
;
init_pll_spi_we
<=
'0'
;
init_pll_spi_we
<=
'0'
;
...
@@ -512,13 +540,17 @@ begin
...
@@ -512,13 +540,17 @@ begin
init_clock_ctrl_wreq
<=
wr_req_d0
;
init_clock_ctrl_wreq
<=
wr_req_d0
;
wr_ack_int
<=
init_clock_ctrl_wack
;
wr_ack_int
<=
init_clock_ctrl_wack
;
when
"0001"
=>
when
"0001"
=>
-- Reg init_mmcm_shift
init_mmcm_shift_wreq
<=
wr_req_d0
;
wr_ack_int
<=
init_mmcm_shift_wack
;
when
"0010"
=>
-- Reg init_clock_status
-- Reg init_clock_status
wr_ack_int
<=
wr_req_d0
;
wr_ack_int
<=
wr_req_d0
;
when
"001
0
"
=>
when
"001
1
"
=>
-- Reg init_tmg
-- Reg init_tmg
init_tmg_wreq
<=
wr_req_d0
;
init_tmg_wreq
<=
wr_req_d0
;
wr_ack_int
<=
init_tmg_wack
;
wr_ack_int
<=
init_tmg_wack
;
when
"0
011
"
=>
when
"0
100
"
=>
-- Reg init_pin_ctrl
-- Reg init_pin_ctrl
init_pin_ctrl_wreq
<=
wr_req_d0
;
init_pin_ctrl_wreq
<=
wr_req_d0
;
wr_ack_int
<=
init_pin_ctrl_wack
;
wr_ack_int
<=
init_pin_ctrl_wack
;
...
@@ -554,7 +586,7 @@ begin
...
@@ -554,7 +586,7 @@ begin
end
process
;
end
process
;
-- Process for read requests.
-- Process for read requests.
process
(
adr_int
,
rd_req_int
,
ctrl_rf1_vtus_i
.
dat
,
ctrl_rf1_vtus_rack
,
ctrl_rf2_vtus_i
.
dat
,
ctrl_rf2_vtus_rack
,
ctrl_reg1_reg
,
ctrl_reg2_reg
,
init_clock_ctrl_clk_sel_reg
,
init_clock_ctrl_mmcm_reset_reg
,
init_clock_status_mmcm_locked_i
,
init_tmg_io_term_reg
,
init_tmg_clk_term_reg
,
init_tmg_clk_oe_reg
,
init_tmg_io_dir_reg
,
init_pin_ctrl_ext_ref_dir_reg
,
init_pll_spi_i
.
dat
,
init_pll_spi_rack
,
init_rf_spi_i
.
dat
,
init_rf_spi_rack
,
init_fw_update_i
.
dat
,
init_fw_update_rack
,
init_rf_i
.
dat
,
init_rf_rack
,
init_wrpc_i
.
dat
,
init_wrpc_rack
)
begin
process
(
adr_int
,
rd_req_int
,
ctrl_rf1_vtus_i
.
dat
,
ctrl_rf1_vtus_rack
,
ctrl_rf2_vtus_i
.
dat
,
ctrl_rf2_vtus_rack
,
ctrl_reg1_reg
,
ctrl_reg2_reg
,
init_clock_ctrl_clk_sel_reg
,
init_clock_ctrl_mmcm_reset_reg
,
init_clock_status_mmcm_locked_i
,
init_
clock_status_shift_busy_i
,
init_
tmg_io_term_reg
,
init_tmg_clk_term_reg
,
init_tmg_clk_oe_reg
,
init_tmg_io_dir_reg
,
init_pin_ctrl_ext_ref_dir_reg
,
init_pll_spi_i
.
dat
,
init_pll_spi_rack
,
init_rf_spi_i
.
dat
,
init_rf_spi_rack
,
init_fw_update_i
.
dat
,
init_fw_update_rack
,
init_rf_i
.
dat
,
init_rf_rack
,
init_wrpc_i
.
dat
,
init_wrpc_rack
)
begin
-- By default ack read requests
-- By default ack read requests
rd_dat_d0
<=
(
others
=>
'X'
);
rd_dat_d0
<=
(
others
=>
'X'
);
ctrl_rf1_vtus_re
<=
'0'
;
ctrl_rf1_vtus_re
<=
'0'
;
...
@@ -604,11 +636,15 @@ begin
...
@@ -604,11 +636,15 @@ begin
rd_dat_d0
(
1
)
<=
init_clock_ctrl_mmcm_reset_reg
;
rd_dat_d0
(
1
)
<=
init_clock_ctrl_mmcm_reset_reg
;
rd_dat_d0
(
15
downto
2
)
<=
(
others
=>
'0'
);
rd_dat_d0
(
15
downto
2
)
<=
(
others
=>
'0'
);
when
"0001"
=>
when
"0001"
=>
-- Reg init_mmcm_shift
rd_ack_d0
<=
rd_req_int
;
when
"0010"
=>
-- Reg init_clock_status
-- Reg init_clock_status
rd_ack_d0
<=
rd_req_int
;
rd_ack_d0
<=
rd_req_int
;
rd_dat_d0
(
0
)
<=
init_clock_status_mmcm_locked_i
;
rd_dat_d0
(
0
)
<=
init_clock_status_mmcm_locked_i
;
rd_dat_d0
(
15
downto
1
)
<=
(
others
=>
'0'
);
rd_dat_d0
(
1
)
<=
init_clock_status_shift_busy_i
;
when
"0010"
=>
rd_dat_d0
(
15
downto
2
)
<=
(
others
=>
'0'
);
when
"0011"
=>
-- Reg init_tmg
-- Reg init_tmg
rd_ack_d0
<=
rd_req_int
;
rd_ack_d0
<=
rd_req_int
;
rd_dat_d0
(
3
downto
0
)
<=
init_tmg_io_term_reg
;
rd_dat_d0
(
3
downto
0
)
<=
init_tmg_io_term_reg
;
...
@@ -617,7 +653,7 @@ begin
...
@@ -617,7 +653,7 @@ begin
rd_dat_d0
(
9
downto
8
)
<=
init_tmg_clk_oe_reg
;
rd_dat_d0
(
9
downto
8
)
<=
init_tmg_clk_oe_reg
;
rd_dat_d0
(
10
)
<=
init_tmg_io_dir_reg
;
rd_dat_d0
(
10
)
<=
init_tmg_io_dir_reg
;
rd_dat_d0
(
15
downto
11
)
<=
(
others
=>
'0'
);
rd_dat_d0
(
15
downto
11
)
<=
(
others
=>
'0'
);
when
"0
011
"
=>
when
"0
100
"
=>
-- Reg init_pin_ctrl
-- Reg init_pin_ctrl
rd_ack_d0
<=
rd_req_int
;
rd_ack_d0
<=
rd_req_int
;
rd_dat_d0
(
0
)
<=
init_pin_ctrl_ext_ref_dir_reg
;
rd_dat_d0
(
0
)
<=
init_pin_ctrl_ext_ref_dir_reg
;
...
...
hdl/top/wr2rf_vme.vhd
View file @
ca8834f2
...
@@ -376,6 +376,9 @@ architecture rtl of wr2rf_vme is
...
@@ -376,6 +376,9 @@ architecture rtl of wr2rf_vme is
signal
tmg_io_in
:
std_logic_vector
(
4
downto
1
);
signal
tmg_io_in
:
std_logic_vector
(
4
downto
1
);
signal
tmg_io_dir
:
std_logic
;
signal
tmg_io_dir
:
std_logic
;
signal
mmcm_shift_incdec
:
std_logic
;
signal
mmcm_shift_en
:
std_logic
;
signal
mmcm_shift_busy
:
std_logic
;
begin
begin
-- Poweron reset.
-- Poweron reset.
...
@@ -728,6 +731,10 @@ begin
...
@@ -728,6 +731,10 @@ begin
clk_sys_i
=>
clk_sys_62m5_in
,
clk_sys_i
=>
clk_sys_62m5_in
,
reset_i
=>
clk_sys_reset
,
reset_i
=>
clk_sys_reset
,
mmcm_shift_incdec_i
=>
mmcm_shift_incdec
,
mmcm_shift_en_i
=>
mmcm_shift_en
,
mmcm_shift_busy_o
=>
mmcm_shift_busy
,
clk62m5_o
=>
clk62m5
,
-- could remove ?
clk62m5_o
=>
clk62m5
,
-- could remove ?
rst_clk62m5_n_o
=>
rst_clk62m5_n
,
rst_clk62m5_n_o
=>
rst_clk62m5_n
,
...
@@ -880,6 +887,10 @@ begin
...
@@ -880,6 +887,10 @@ begin
clk_sel_o
=>
clk_sys_select
,
clk_sel_o
=>
clk_sys_select
,
clk_sys_reset_o
=>
clk_sys_reset
,
clk_sys_reset_o
=>
clk_sys_reset
,
mmcm_shift_incdec_o
=>
mmcm_shift_incdec
,
mmcm_shift_en_o
=>
mmcm_shift_en
,
mmcm_shift_busy_i
=>
mmcm_shift_busy
,
tmg_clk_term_en_o
=>
tmg_clk_term_en_o
,
tmg_clk_term_en_o
=>
tmg_clk_term_en_o
,
tmg_io_term_en_o
=>
tmg_io_term_en_o
,
tmg_io_term_en_o
=>
tmg_io_term_en_o
,
tmg_clk_oe_o
=>
tmg_clk_oen_o
,
tmg_clk_oe_o
=>
tmg_clk_oen_o
,
...
...
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