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wr2rf-vme
Commits
c1df0ce9
Commit
c1df0ce9
authored
Jan 20, 2021
by
John Robert Gill
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Almost a beta firmware, was merged...
parent
cdaf22f2
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.gitignore
.gitignore
+4
-0
wr2rf.c
software/initseq/wr2rf.c
+460
-67
wr2rf_init.sh
software/scripts/wr2rf_init.sh
+49
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.gitignore
View file @
c1df0ce9
...
...
@@ -19,5 +19,9 @@ _xmsgs/
*.d
*.log
*.jou
*.a
spi_echo
software/initseq/wr2rf
software/initseq/wrc
software/initseq/show_pll
software/initseq/show_nco
software/initseq/wr2rf.c
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c1df0ce9
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software/scripts/wr2rf_init.sh
0 → 100644
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c1df0ce9
#!/bin/bash
slot
=
$1
# Check we have basic access to the register space over VME
/user/jgill/wr2rf
-s
$slot
hwver
# Initialise the OCXO and PLL. Switch over clocking functions...
/user/jgill/wr2rf
-s
$slot
pll-init
# Initialise the AD9910 dds to generate the 223.5 MHz required for the mixer
/user/jgill/wr2rf
-s
$slot
dds-init
# Dynamically load wrpc-sw to start the WR link
/user/jgill/wr2rf
-s
$slot
fw-load /user/jgill/wrc_tom_dec11.bin
# Load the IQ SetPoints
/user/jgill/wr2rf
-s
$slot
dac-iqsetpoint 1 0x4000 0x0
/user/jgill/wr2rf
-s
$slot
dac-iqsetpoint 2 0x4000 0x0
# Configure the IQ DACs
/user/jgill/wr2rf
-s
$slot
dac-init 1
/user/jgill/wr2rf
-s
$slot
dac-init 2
# Calibrate the IQ DAC timing delays for SET, HLD, CLK
/user/jgill/wr2rf
-s
$slot
dac-timing 1
/user/jgill/wr2rf
-s
$slot
dac-timing 2
# Configure the output driving the IQ DACs to come from the RFNCO->IQmod block or xilinx DDS test chip
/user/jgill/wr2rf
-s
$slot
dac-iqctrl 1 rfnco
/user/jgill/wr2rf
-s
$slot
dac-iqctrl 2 rfnco
# Place the front panel RF MUXes to output the MIXED LO - IQ.
/user/jgill/wr2rf
-s
$slot
set-rfout 1 mix
/user/jgill/wr2rf
-s
$slot
set-rfout 2 mix
# Select whether you want the source of RFNCO operation to be "network" or "local", default is "local"
/user/jgill/wr2rf
-s
$slot
nco-source network
# Configure TMG IO for RF trigger units default operation
# TU starts are input on tmg_clk[2:1]
/user/jgill/wr2rf
-s
$slot
tmgclk-oe 0x0
/user/jgill/wr2rf
-s
$slot
tmgclk-term 0x3
# TU stops are input on tmg_io[2:1]
# RF sync signals are output on tmg_io[4:3]
/user/jgill/wr2rf
-s
$slot
tmgio-oe 0xC
/user/jgill/wr2rf
-s
$slot
tmgio-term 0x3
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