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wr2rf-vme
Commits
9907a6aa
Commit
9907a6aa
authored
May 04, 2020
by
Tristan Gingold
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vtuCore: cleanup for high-freq.
parent
1df96bbf
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4 deletions
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vtuCore.vhd
dependencies/vtu/rtl/vtuCore.vhd
+3
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dependencies/vtu/rtl/vtuCore.vhd
View file @
9907a6aa
...
...
@@ -1422,14 +1422,12 @@ begin
signal
Fdly
:
unsigned
(
3
downto
0
);
signal
Ndly
:
unsigned
(
3
downto
0
);
signal
Sht
:
unsigned
(
3
downto
0
);
signal
Plen
:
unsigned
(
3
downto
0
);
signal
pattern
:
std_logic_vector
(
15
downto
0
);
signal
waveform
:
std_logic_vector
(
15
downto
0
);
signal
prev_dataout
:
std_logic_vector
(
7
downto
0
);
begin
process
(
Clk
)
variable
tmp
:
std_logic_vector
(
15
downto
0
);
variable
tsht
:
unsigned
(
4
downto
0
);
begin
if
rising_edge
(
Clk
)
then
if
Rst
=
'1'
or
Stop
=
'1'
then
...
...
@@ -1466,7 +1464,7 @@ begin
Run_HF
<=
'0'
;
DataOutHighFreq
<=
x"00"
;
-- But prepare the pattern.
Plen
<=
unsigned
(
htValue
(
3
downto
0
));
-- Ndly is where the first byte appears in the second byte as number of shift to the right.
case
htValue
(
3
downto
0
)
is
when
"0010"
=>
pattern
<=
"10101010"
&
"10101010"
;
...
...
@@ -1516,13 +1514,14 @@ begin
end
if
;
else
-- Running.
-- Generate the output byte. We need to also shift from the initial delay.
tmp
:
=
std_logic_vector
(
shift_right
(
unsigned
(
waveform
),
to_integer
(
unsigned
(
Fdly
))));
DataOutHighFreq
<=
prev_dataout
or
tmp
(
15
downto
8
);
prev_dataout
<=
tmp
(
7
downto
0
);
-- Prepare the next byte.
tmp
:
=
std_logic_vector
(
shift_right
(
unsigned
(
Waveform
),
to_integer
(
unsigned
(
Ndly
))));
waveform
<=
waveform
(
7
downto
0
)
&
tmp
(
7
downto
0
);
Tsht
:
=
(
'0'
&
Sht
)
+
(
'0'
&
Ndly
);
Sht
<=
Sht
+
Ndly
;
end
if
;
end
if
;
...
...
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