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wr2rf-vme
Commit 7fa5e847 authored by John Robert Gill's avatar John Robert Gill
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Added code to initialise the trigger unit delay lines and avoid restarting the… 

Added code to initialise the trigger unit delay lines and avoid restarting the LT6950 PLL if already started.
parent 006f6988
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Showing with 29 additions and 32 deletions
software/libwr2rf/init.c
View file @ 7fa5e847
......@@ -112,43 +112,33 @@ libwr2rf_ltc6950_sync (struct libwr2rf_dev *dev)
void
libwr2rf_clock_init (struct libwr2rf_dev *dev)
{
unsigned ctrl;
/* Note: The OCXO must have been enabled. */
/* 1. the PLL (ltc6950). */
/* 1.1 the SPI control for the PLL. */
libwr2rf_pll_spi_init(dev);
/* 1.2 the PLL itself. */
libwr2rf_ltc6950_init (dev);
/* 1.3 sync the PLL */
libwr2rf_ltc6950_sync (dev);
/* 2. FPGA clock. */
libwr2rf_clock_select_dds (dev);
#if 0
/* 3. DDS (ad9910). */
libwr2rf_dds_spi_init(dev);
libwr2rf_dds_init(dev, 0);
/* 4. RF DAC. */
for (unsigned i = 0; i < 2; i++) {
/* 4.1 Init registers. */
libwr2rf_dac_init(dev, i);
/* 4.2 Set timing for inputs. */
libwr2rf_dac_port_timing(dev, i);
/* we have to check if the PLL has already been initialised and the clock select set */
ctrl = libwr2rf_read16(dev, WR2RF_VME_REGS_INIT + WR2RF_INIT_REGS_CLOCK_CTRL);
if ((ctrl & WR2RF_INIT_REGS_CLOCK_CTRL_CLK_SEL) == 0)
{
/* 1. the PLL (ltc6950). */
/* 1.1 the SPI control for the PLL. */
libwr2rf_pll_spi_init(dev);
/* 1.2 the PLL itself. */
libwr2rf_ltc6950_init (dev);
/* 1.3 sync the PLL */
libwr2rf_ltc6950_sync (dev);
/* 2. FPGA clock. */
libwr2rf_clock_select_dds (dev);
/* 5. WR-Core */
libwr2rf_wrcore_init(dev);
/* 6. IOdelays */
libwr2rf_iodelay_init(dev);
}
#endif
/* 5. WR-Core */
libwr2rf_wrcore_init(dev);
/* 6. IOdelays */
libwr2rf_iodelay_init(dev);
}
static int
libwr2rf_nco_wrcfg (struct libwr2rf_dev *dev, unsigned ch)
{
......@@ -284,6 +274,13 @@ libwr2rf_api_init (struct libwr2rf_dev *dev)
/* Set the rf reset offset delay wrt nco_reset_cdelayed */
libwr2rf_vtu_rf_reset_offset(dev, LIBWR2RF_RF1_CHANNEL_ID, 10);
libwr2rf_vtu_rf_reset_offset(dev, LIBWR2RF_RF2_CHANNEL_ID, 10);
/* Initialise the trigger unit flip-flop delay lines */
libwr2rf_vtu_output_ff_delay(dev, LIBWR2RF_TRIG_ID_RF_1_TRIG_1, 0);
libwr2rf_vtu_output_ff_delay(dev, LIBWR2RF_TRIG_ID_RF_1_TRIG_2, 0);
libwr2rf_vtu_output_ff_delay(dev, LIBWR2RF_TRIG_ID_RF_2_TRIG_1, 0);
libwr2rf_vtu_output_ff_delay(dev, LIBWR2RF_TRIG_ID_RF_2_TRIG_2, 0);
return 0;
}
......
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