vtuCore: add highfreq generation + testbench

5f618a93 · Tristan Gingold · 9aa10a21 · 5f618a93 · 5f618a93
Commit 5f618a93 authored Apr 29, 2020 by Tristan Gingold
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Showing with 193 additions and 5 deletions

vtuCore.vhd dependencies/vtu/rtl/vtuCore.vhd +121 -4

tb_vtu.vhd hdl/testbench/vtu/tb_vtu.vhd +72 -1

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--- a/dependencies/vtu/rtl/vtuCore.vhd
+++ b/dependencies/vtu/rtl/vtuCore.vhd
@@ -35,6 +35,7 @@ package MemMap_ctuAsVtu is
 	constant C_Code_ctuAsVtu_control2_mode_syncLessOperation : std_logic_vector(7 downto 5) := "011";
 	constant C_Code_ctuAsVtu_control2_mode_lowFreqGeneration : std_logic_vector(7 downto 5) := "100";
 	constant C_Code_ctuAsVtu_control2_mode_playMemory   : std_logic_vector(7 downto 5) := "101";
+	constant C_Code_ctuAsVtu_control2_mode_HighFreqGeneration : std_logic_vector(7 downto 5) := "110";

 end;
 -- EOF
@@ -961,6 +962,7 @@ architecture vtuCore of vtuCore is
  signal DataOutPlayMem : std_logic_vector(7 downto 0 );
  signal DataOut_seq : std_logic_vector(7 downto 0 );
  signal DataOutHTSyncLess : std_logic_vector(7 downto 0 );
+  signal DataOutHighFreq : std_logic_vector(7 downto 0 );
  signal DataOut_B : std_logic_vector(7 downto 0 );

  signal OE_SyncLess : std_logic;
@@ -1407,10 +1409,125 @@ begin
    DataOutLowFreq <= DataFilled when ClkValueSwitch = '0' else not DataFilled;
  end block blk_lowfreq;

-  DataOut <= DataOutHTSyncLess when Mode = C_Code_ctuAsVtu_control2_mode_syncLessOperation else
-             DataOutLowFreq when Mode = C_Code_ctuAsVtu_control2_mode_lowFreqGeneration else
-             DataOutPlayMem when Mode = C_Code_ctuAsVtu_control2_mode_playMemory else
-             DataOut_seq;
+  blk_highfreq: block
+    --  True if running.
+    signal Run_HF : std_logic;
+    signal Fdly : unsigned(3 downto 0);
+    signal Ndly : unsigned(3 downto 0);
+    signal Sht : unsigned(3 downto 0);
+    signal Plen : unsigned(3 downto 0);
+    signal pattern : std_logic_vector (15 downto 0);
+    signal waveform : std_logic_vector(15 downto 0);
+    signal prev_dataout : std_logic_vector(7 downto 0);
+  begin
+    process (Clk)
+      variable tmp : std_logic_vector(15 downto 0);
+      variable tsht : unsigned(4 downto 0);
+    begin
+      if rising_edge (Clk) then
+        if Rst = '1' or Stop = '1' then
+          Run_HF <= '0';
+          waveform <= (others => '0');
+          prev_dataout <= (others => '0');
+          Sht <= "0000";
+        else
+          if Run_HF = '0' then
+            --  Ready to run: wait for sync.  Will clear these signals if no sync.
+            Run_HF <= '1';
+            waveform <= pattern;
+            Sht <= Ndly;
+
+            if DataOut_B (7) = '1' then
+              Fdly <= "0001";
+            elsif DataOut_B (6) = '1' then
+              Fdly <= "0010";
+            elsif DataOut_B (5) = '1' then
+              Fdly <= "0011";
+            elsif DataOut_B (4) = '1' then
+              Fdly <= "0100";
+            elsif DataOut_B (3) = '1' then
+              Fdly <= "0101";
+            elsif DataOut_B (2) = '1' then
+              Fdly <= "0110";
+            elsif DataOut_B (1) = '1' then
+              Fdly <= "0111";
+            elsif DataOut_B (0) = '1' then
+              Fdly <= "1000";
+            else
+              --  No pulse, don't run.
+              Run_HF <= '0';
+              DataOutHighFreq <= x"00";
+              --  But prepare the pattern.
+              Plen <= unsigned (htValue(3 downto 0));
+              case htValue(3 downto 0) is
+                when "0010" =>
+                  pattern <= "10101010" & "10101010";
+                  Ndly <= "0000";
+                when "0011" =>
+                  pattern <= "11011011" & "01101101";
+                  Ndly <= "0001";
+                when "0100" =>
+                  pattern <= "11001100" & "11001100";
+                  Ndly <= "0000";
+                when "0101" =>
+                  pattern <= "11100111" & "00111001";
+                  Ndly <= "0010";
+                when "0110" =>
+                  pattern <= "11100011" & "10001110";
+                  Ndly <= "0100";
+                when "0111" =>
+                  pattern <= "11110001" & "11100011";
+                  Ndly <= "0110";
+                when "1000" =>
+                  pattern <= "11110000" & "11110000";
+                  Ndly <= "0000";
+                when "1001" =>
+                  pattern <= "11111000" & "01111100";
+                  Ndly <= "0001";
+                when "1010" =>
+                  pattern <= "11111000" & "00111110";
+                  Ndly <= "0010";
+                when "1011" =>
+                  pattern <= "11111100" & "00011111";
+                  Ndly <= "0011";
+                when "1100" =>
+                  pattern <= "11111100" & "00001111";
+                  Ndly <= "0100";
+                when "1101" =>
+                  pattern <= "11111110" & "00000111";
+                  Ndly <= "0101";
+                when "1110" =>
+                  pattern <= "11111110" & "00000011";
+                  Ndly <= "0110";
+                when "1111" =>
+                  pattern <= "11111111" & "00000001";
+                  Ndly <= "0111";
+                when others =>
+                  pattern <= "00000000" & "00000000";
+              end case;
+            end if;
+          else
+            --  Running.
+            tmp := std_logic_vector(shift_right(unsigned(waveform), to_integer(unsigned(Fdly))));
+            DataOutHighFreq <= prev_dataout or tmp (15 downto 8);
+            prev_dataout <= tmp (7 downto 0);
+
+            tmp := std_logic_vector(shift_right(unsigned(Waveform), to_integer(unsigned(Ndly))));
+            waveform <= waveform(7 downto 0) & tmp (7 downto 0);
+            Tsht := ('0' & Sht) + ('0' & Ndly);
+            Sht <= Sht + Ndly;
+          end if;
+        end if;
+      end if;
+    end process;
+  end block;
+
+  with Mode select 
+    DataOut <= DataOutHTSyncLess when C_Code_ctuAsVtu_control2_mode_syncLessOperation,
+              DataOutLowFreq when C_Code_ctuAsVtu_control2_mode_lowFreqGeneration,
+              DataOutHighFreq when C_Code_ctuAsVtu_control2_mode_highFreqGeneration,
+              DataOutPlayMem when C_Code_ctuAsVtu_control2_mode_playMemory,
+              DataOut_seq when others;

  --  Pulse detected.
  SyncPulse <= SyncPulse_i;

--- a/hdl/testbench/vtu/tb_vtu.vhd
+++ b/hdl/testbench/vtu/tb_vtu.vhd
@@ -394,6 +394,72 @@ begin
          report "test lowfreq: done";
        end test_lowfreq;

+        procedure test_highfreq (bval : natural; htval : natural)
+         is
+          variable val : std_logic_vector(15 downto 0);
+          variable cnt : natural;
+          variable dly_exp : natural;
+        begin
+          report "test highfreq - setup vtu ht:" & natural'image(htval);
+          --  Program the vtu
+          wait until rising_edge(clk_sys);
+          --  Delay between start and the first pulse.
+          write64be_pl (clk_sys, wb_in, wb_out, ADDR_TRIGUNIT_REGS_BVALUEOFFLINE,
+                        std_logic_vector(to_unsigned(bval, 64)));
+          --  Delay between the pulses.
+          write64be_pl (clk_sys, wb_in, wb_out, ADDR_TRIGUNIT_REGS_HTVALUEOFFLINE,
+                        std_logic_vector(to_unsigned(htval, 64)));
+          --  Number of pulses (unused).
+          write64be_pl (clk_sys, wb_in, wb_out, ADDR_TRIGUNIT_REGS_WVALUEOFFLINE, x"0000_0000_0000_0014");
+
+          --  Lowfreq generation, enable.
+          write16_pl (clk_sys, wb_in, wb_out, ADDR_TRIGUNIT_REGS_CONFIGOFFLINE, x"0061");
+
+          --  Set expected results.
+          observer_cmd <= (count => 24, infinite => true, square => False);
+
+          report "test highfreq - start pulse";
+          start_pulse;
+
+          read_status(val);
+          assert val (TRIGUNIT_REGS_STATUS_MISSVALID_OFFSET) = '0' severity error;
+
+          --  Sync pulse.
+          sync_pulse;
+
+          --  Check ...
+          read_status(val);
+          assert val (TRIGUNIT_REGS_STATUS_STARTREADY_OFFSET) = '1' severity error;
+          assert val (TRIGUNIT_REGS_STATUS_RUNNING_OFFSET) = '1' severity error;
+
+          --  Wait until end of generation.
+          wait on observer_state;
+          --  Check observer status.
+          assert observer_state = OBS_DONE severity error;
+          assert observer_period = htval * 5 ns;
+          report "highfreq delay:" & natural'image(observer_delay);
+          dly_exp := (8 + bval + 8 + 8 + 16 + 1);
+          assert observer_delay = dly_exp
+            report "highfreq test: bad delay:" & natural'image(observer_delay) & ", expect:" & natural'image (dly_exp)
+            severity error;
+
+          --  Stop counter.  Synchronize to
+          wait until rising_edge(clk_vtu);
+          stop <= '1';
+          wait for 40 ns;
+          stop <= '0';
+
+          --  Wait a little bit (2 full periods)
+          wait for 2 * 2 * observer_period;
+
+          cnt := observer_count;
+
+          --  Wait  for 2 full periods.
+          wait for 2 * 2 * observer_period;
+
+          report "test highfreq: done";
+        end test_highfreq;
+
        variable val : std_logic_vector(15 downto 0);
    begin
        sync <= '0';
@@ -419,11 +485,16 @@ begin

        -------------------------------------------------------------------------------------------------

-        --  Test 3: Program the vtu
+        --  Test 3: Low-freq
        test_lowfreq (29, 17);

        test_lowfreq (12, 20);

+        --  Test 4: high-freq
+        for i in 2 to 15 loop
+          test_highfreq(16, i);
+        end loop;
+
        report "end of tests";
        wait;
    end process;